CN112053722A - Memory device - Google Patents

Abstract

There is provided a memory device, the memory device including: a memory cell array disposed in the first semiconductor layer, the memory cell array including a plurality of word lines extending in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of transfer transistors provided in the first semiconductor layer, wherein a first transfer transistor of the plurality of transfer transistors is provided between a first signal line of the plurality of signal lines and a first word line of the plurality of word lines, and wherein the plurality of signal lines are arranged at the same level as the common source line.

Description

Memory device

This application claims priority from korean patent application No. 10-2019-0066996, filed by the korean intellectual property office at 5.6.2019, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The present inventive concept relates to a memory device, and more particularly, to a non-volatile memory device having a Cell Over Peripheral (COP) structure.

Background

As information communication devices become more multifunctional, memory devices that are highly integrated and have a large capacity are required. As the size of memory cells has been reduced to increase the integration of memory devices, the operating circuit and/or wiring structure of the memory devices has become complicated. Accordingly, techniques for designing highly integrated memory devices having superior electrical characteristics are being developed. In particular, in order to increase the integration of the memory device, the number of word lines stacked on the substrate in the vertical direction may be increased. However, in this case, the number of transfer transistors connected to the word line increases, and thus the chip size may increase.

Disclosure of Invention

According to an exemplary embodiment of the inventive concept, there is provided a memory device including: a memory cell array disposed in the first semiconductor layer, the memory cell array including a plurality of word lines extending in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of transfer transistors provided in the first semiconductor layer, wherein a first transfer transistor of the plurality of transfer transistors is provided between a first signal line of the plurality of signal lines and a first word line of the plurality of word lines, wherein the plurality of signal lines are arranged at the same level as the common source line.

According to an exemplary embodiment of the inventive concept, there is provided a memory device including: a memory cell array including a plurality of word lines stacked in a vertical direction; and a plurality of vertical transfer transistors, wherein a first vertical transfer transistor of the plurality of vertical transfer transistors includes a first vertical channel extending in a vertical direction between a first driving signal line and a first word line of the plurality of word lines, wherein the first vertical channel is disposed near an end of the first word line, and wherein the first driving signal line and the common source line are arranged in a same layer.

According to an exemplary embodiment of the inventive concept, there is provided a memory device including a first semiconductor layer including: a memory cell array including a plurality of word lines stacked in a vertical direction; and a plurality of transfer transistors, a first transfer transistor of the plurality of transfer transistors being connected to a driving signal line, wherein the driving signal line is connected to a gate electrode arranged on the same layer as the ground selection line.

Drawings

The above and other features of the inventive concept will be more clearly understood by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

fig. 1 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept;

fig. 2 illustrates a structure of a memory device according to an exemplary embodiment of the inventive concept;

fig. 3 illustrates a memory cell array according to an exemplary embodiment of the inventive concept;

fig. 4 illustrates an equivalent circuit of a memory block according to an exemplary embodiment of the inventive concept;

FIG. 5 illustrates a row decoder and pass transistor circuit according to an exemplary embodiment of the inventive concepts;

fig. 6 is a cross-sectional view illustrating a memory device including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concepts;

fig. 7 is a cross-sectional view illustrating a memory device including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concept;

FIG. 8 illustrates a row decoder and pass transistor circuit according to an exemplary embodiment of the inventive concepts;

fig. 9 is a cross-sectional view illustrating a memory device including the pass transistor circuit of fig. 8 according to an exemplary embodiment of the inventive concept;

fig. 10 is a top view illustrating a memory device including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concepts;

fig. 11 is a sectional view taken along line XI-XI' of fig. 10 according to an exemplary embodiment of the inventive concept;

fig. 12 is a cross-sectional view illustrating a memory device including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concepts;

fig. 13 is a cross-sectional view illustrating a memory device including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concepts;

fig. 14 is a top view illustrating a memory device including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concepts;

fig. 15 is a cross-sectional view taken along line XV-XV' of fig. 14, according to an exemplary embodiment of the inventive concept;

fig. 16 is a cross-sectional view taken along line XVI-XVI' of fig. 14, according to an exemplary embodiment of the inventive concept;

fig. 17 illustrates voltages applied to word line driving signal lines through a memory operation according to an exemplary embodiment of the inventive concepts;

fig. 18 illustrates a row decoder and pass transistor circuit according to an exemplary embodiment of the inventive concepts;

fig. 19 is a cross-sectional view illustrating a memory device including the pass transistor circuit of fig. 18 according to an exemplary embodiment of the inventive concepts;

fig. 20, 21, and 22 are perspective views respectively illustrating a memory device according to an exemplary embodiment of the inventive concept;

fig. 23 illustrates a top surface of a memory device according to a comparative example and a top surface of a memory device according to an exemplary embodiment of the inventive concepts;

FIG. 24 is an enlarged view of the first and second regions of FIG. 23;

fig. 25 is a top view illustrating a first surface of a first semiconductor layer included in a memory device according to an exemplary embodiment of the inventive concept;

fig. 26 and 27 illustrate a memory device according to an exemplary embodiment of the inventive concept;

fig. 28 illustrates a structure of a memory device according to an exemplary embodiment of the inventive concepts;

fig. 29 is a cross-sectional view illustrating the memory device of fig. 28, according to an exemplary embodiment of the inventive concept; and is

Fig. 30 is a block diagram illustrating an example in which a memory device according to an exemplary embodiment of the inventive concept is applied to a Solid State Drive (SSD) system.

Detailed Description

Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals may refer to like elements.

Fig. 1 is a block diagram illustrating a memory device 10 according to an exemplary embodiment of the inventive concept.

Referring to fig. 1, a memory device 10 may include a memory cell array 100 and peripheral circuitry 200. The peripheral circuit 200 may include a pass transistor circuit 210, a row decoder 220, control logic 230, and a page buffer 240. The peripheral circuit 200 may also include a voltage generator, data input and output circuitry, input and output interfaces, column logic, pre-decoders, temperature sensors, command decoders, or address decoders. In an exemplary embodiment of the inventive concept, the memory device 10 may be a non-volatile memory device. Hereinafter, the "memory device" may be referred to as a nonvolatile memory device.

In one exemplary embodiment of the inventive concept, the memory cell array 100, the pass transistor circuit 210, and the row decoder 220 may be disposed in an upper semiconductor layer (e.g., L1 of fig. 2), and the control logic 230 and the page buffer 240 may be disposed in a lower semiconductor layer (e.g., L2 of fig. 2). However, the inventive concept is not limited thereto. In another exemplary embodiment of the inventive concept, the memory cell array 100 and the pass transistor circuit 210 may be disposed in an upper semiconductor layer, and the row decoder 220, the control logic 230, and the page buffer 240 may be disposed in a lower semiconductor layer. In another exemplary embodiment of the inventive concept, some circuits of the circuits configuring the row decoder 220 may be disposed in an upper semiconductor layer together with the memory cell array 100 and the pass transistor circuit 210, and the control logic 230, the page buffer 240, and other parts of the circuits configuring the row decoder 220 may be disposed in a lower semiconductor layer.

In an exemplary embodiment of the inventive concept, the transfer transistor circuit 210 may include a plurality of vertical transfer transistors (e.g., TR1 to TRs of fig. 6). For example, a plurality of vertical transfer transistors may be disposed in the upper semiconductor layer. In an exemplary embodiment of the inventive concept, the transfer transistor circuit 210 may include a plurality of vertical transfer transistors (e.g., TR1 to TRm of fig. 22) and a plurality of common transfer transistors (e.g., TRn of fig. 22). For example, a plurality of vertical transfer transistors may be disposed in the upper semiconductor layer, and a plurality of common transfer transistors may be disposed in the lower semiconductor layer. In this case, the first portion of the transfer transistor circuit 210 may be disposed on the upper semiconductor layer, and the second portion of the transfer transistor circuit 210 may be disposed on the lower semiconductor layer.

The memory cell array 100 may be connected to the page buffer 240 through a bit line BL, and may be connected to the pass transistor circuit 210 through a word line WL, a string selection line SSL, and a ground selection line GSL. Further, the transfer transistor circuit 210 may be connected to the row decoder 220 through a block selection signal line BS, a string selection line driving signal line SS, a word line driving signal line SI, and a ground selection line driving signal line GS. The string selection line driving signal line SS, the word line driving signal line SI, and the ground selection line driving signal line GS may be referred to as "driving signal lines".

In addition, the memory cell array 100 may include a plurality of memory cells, and the memory cells may be, for example, flash memory cells. Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to an example in which a plurality of memory cells are NAND flash memory cells. However, the inventive concept is not limited thereto. In some exemplary embodiments of the inventive concept, the plurality of memory cells may be resistive memory cells, such as resistive random access memory (ReRAM), phase change ram (pram), or magnetic ram (mram).

In example embodiments of the inventive concepts, the memory cell array 100 may include a three-dimensional memory cell array, the three-dimensional memory cell array may include a plurality of NAND strings, and each of the NAND strings may include memory cells respectively connected to word lines vertically stacked on a substrate. Such a configuration will be described with reference to fig. 3 and 4. The following patent documents, incorporated herein by reference in their entirety, describe the construction of three-dimensional memory arrays, wherein the three-dimensional memory array is constructed in multiple layers, with word lines and/or bit lines shared between the multiple layers: U.S. patent nos. 7,679,133, 8,553,466, 8,654,587 and 8,559,235 and U.S. publication No. 2011/0233648. However, the inventive concept is not limited thereto. In some exemplary embodiments of the inventive concepts, the memory cell array 100 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged in row and column directions.

The control logic 230 may generate various control signals for programming data to the memory cell array 100, reading data from the memory cell array 100, or erasing data stored in the memory cell array 100, based on the command CMD, the address ADDR, and the control signal CTRL. For example, control logic 230 may output row addresses X-ADDR to row decoder 220 and may output column addresses Y-ADDR to page buffer 240. Thus, control logic 230 may control various operations in memory device 10.

In response to the row address X-ADDR, the row decoder 220 may output a block selection signal for selecting one of the plurality of memory blocks to the block selection signal line BS. Further, in response to the row address X-ADDR, the row decoder 220 outputs a word line driving signal for selecting one of the word lines WL of the selected memory block to the word line driving signal lines SI, outputs a string selection line driving signal for selecting one of the string selection lines SSL to the string selection line driving signal lines SS, and may output a ground selection line driving signal for selecting one of the ground selection lines GSL to the ground selection line driving signal lines GS. In response to the column address Y-ADDR, the page buffer 240 may select a part of the bit lines among the bit lines BL. For example, the page buffer 240 operates as a write driver or a sense amplifier according to an operation mode.

As the number of stages of memory cells arranged in the memory cell array 100 increases, in other words, as the number of word lines WL stacked in the vertical direction increases, the number of vertical transfer transistors for driving the word lines WL increases. Therefore, the area occupied by the transfer transistor circuit 210 increases. On the other hand, as the number of word lines WL stacked in the vertical direction increases, the area of the memory cell array 100 decreases. In the case where the memory device 10 is implemented by a Cell On Periphery (COP) structure, when the area of the memory cell array 100 is reduced, since the area of the peripheral circuit disposed under the memory cell array 100 is also reduced, the entire peripheral circuit 200 may not be disposed under the memory cell array 100.

According to the present embodiment of the inventive concept, the pass transistor circuit 210 may be arranged in a staircase region (e.g., SA of fig. 6) of the word line WL. In other words, the pass transistor circuit 210 may be located in a region in which the word line WL has a staircase shape. In an exemplary embodiment of the inventive concept, the transfer transistor circuit 210 may include a plurality of vertical transfer transistors arranged in a staircase region of the word line WL. Therefore, since the region in which the transfer transistor circuit 210 is arranged overlaps the stepped region of the word lines WL, even if the number of vertical transfer transistors is increased according to an increase in the number of stacked word lines WL, it is possible to prevent an increase in the chip size of the memory device 10.

Fig. 2 illustrates a structure of the memory device 10 according to an exemplary embodiment of the inventive concept.

Referring to fig. 1 and 2, the memory device 10 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked on the second semiconductor layer L2 in the vertical direction VD. For example, the second semiconductor layer L2 may be disposed below the first semiconductor layer L1 in the vertical direction VD.

In one exemplary embodiment of the inventive concept, the memory cell array 100, the transfer transistor circuit 210, and the row decoder 220 may be formed in the first semiconductor layer L1, and the control logic 230 and the page buffer 240 may be formed in the second semiconductor layer L2. Therefore, the memory device 10 may have a structure in which the memory cell array 100 is arranged on a part of the peripheral circuit, in other words, the memory device 10 may have a COP structure. In the COP structure, the area in the horizontal direction can be reduced, and the degree of integration of the memory device 10 can be increased.

In exemplary embodiments of the inventive concept, the second semiconductor layer L2 may include a substrate. A circuit including the control logic 230 and the page buffer 240 may be formed in the second semiconductor layer L2 by forming semiconductor devices such as transistors and a pattern for wiring the semiconductor devices on a substrate. After forming circuits in the second semiconductor layer L2, the first semiconductor layer L1 including the memory cell array 100, the pass transistor circuit 210, and the row decoder 220 may be formed, and a pattern for electrically connecting the bit lines BL of the memory cell array 100 to the circuits formed in the second semiconductor layer L2 or a pattern for electrically connecting the row decoder 220 to the circuits formed in the second semiconductor layer L2 may be formed.

Fig. 3 illustrates a memory cell array 100 according to an exemplary embodiment of the inventive concepts.

Referring to fig. 3, the memory cell array 100 may include a plurality of memory blocks BLK1 through BLKi ("i" may be a positive integer). Each of the plurality of memory blocks BLK1 through BLKi may have a three-dimensional structure (or a vertical structure). For example, each of the plurality of memory blocks BLK1 through BLKi may include a plurality of NAND strings extending in the vertical direction VD. In this case, the plurality of NAND strings may be spaced apart from each other by a distance in the first and second horizontal directions HD1 and HD 2. A plurality of memory blocks BLK1 through BLKi may be selected by the row decoder (220 of fig. 1). For example, the row decoder 220 may select a memory block corresponding to a block address among the plurality of memory blocks BLK1 through BLKi.

Fig. 4 illustrates an equivalent circuit of the memory block BLK according to an exemplary embodiment of the inventive concept. For example, memory block BLK may correspond to one of the plurality of memory blocks BLK1 through BLKi of fig. 3.

Referring to fig. 4, the memory block BLK may include: the NAND memory device includes a plurality of NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33, a plurality of word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, a plurality of bit lines BL1, BL2, and BL3, a plurality of ground select lines GSL1, GSL2, and GSL3, a plurality of string select lines SSL1, SSL2, and SSL3, and a common source line CSL. Here, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may vary according to exemplary embodiments of the inventive concepts.

The NAND strings NS11, NS21, and NS31 are disposed between the first bit line BL1 and the common source line CSL, the NAND strings NS12, NS22, and NS32 are disposed between the second bit line BL2 and the common source line CSL, and the NAND strings NS13, NS23, and NS33 are disposed between the third bit line BL3 and the common source line CSL. Each NAND string (e.g., NS11) may include a string selection transistor SST, a plurality of memory cells MCs, and a ground selection transistor GST connected in series with each other.

The string selection transistors SST are connected to corresponding string selection lines SSL1 to SSL 3. The plurality of memory cells MCs are connected to corresponding word lines WL1 to WL8, respectively. The ground selection transistor GST is connected to the corresponding ground selection lines GSL1 to GSL 3. The string selection transistors SST are connected to corresponding bit lines BL1 to BL3, and the ground selection transistors GST are connected to a common source line CSL.

In the present embodiment of the inventive concept, word lines (e.g., WL1) having the same height are commonly connected, string selection lines SSL1 through SSL3 are separated from each other, and ground selection lines GSL1 through GSL3 are separated from each other. In fig. 4, it is shown that the string selection lines SSL1 through SSL3 share word lines having the same height. However, the inventive concept is not limited thereto. For example, two string select lines may share a word line having the same height. In another example, four string select lines may share word lines having the same height.

Fig. 5 illustrates a row decoder 220a and a pass transistor circuit 210a according to an exemplary embodiment of the inventive concept.

Referring to fig. 5, the memory block BLKa may correspond to one of the memory blocks BLK1 through BLKi of fig. 3, and "a" may be a positive integer. The row decoder 220a may be an example of the row decoder 220 of fig. 1 and the pass transistor circuit 210a may be an example of the pass transistor circuit 210 of fig. 1. Therefore, the contents described in detail above with reference to fig. 1 to 4 may be applied to the current embodiment.

The row decoder 220a may include a block decoder 221 and a driving signal line decoder 222 a. The transfer transistor circuit 210a may include a plurality of vertical transfer transistors TRs, TR1 to TRm, and TRg, and "m" may be a positive integer. The transfer transistor circuit 210a may be provided in each of the memory blocks (BLK 1 to BLKi of fig. 3), and the block decoder 221 and the driving signal line decoder 222a may be provided in common to the memory blocks (BLK 1 to BLKi of fig. 3).

The block decoder 221 may be connected to the transfer transistor circuit 210a through a block selection signal line BS. For example, the block selection signal line BS may be connected to the gates of the plurality of vertical transfer transistors TRs, TR1 to TRm, and TRg. For example, when a block selection signal supplied through the block selection signal line BS is activated, the plurality of vertical transfer transistors TRs, TR1 to TRm, and TRg are turned on. Thus, the memory block BLKa may be selected.

The drive signal line decoder 222a may be connected to the transfer transistor circuit 210a through a string selection line drive signal line SS, word line drive signal lines SI1 to SIm, and a ground selection line drive signal line GS. For example, the string selection line driving signal line SS, the word line driving signal lines SI1 to SIm, and the ground selection line driving signal line GS may be connected to the sources of the plurality of vertical transfer transistors TRs, TR1 to TRm, and TRg, respectively.

The pass transistor circuit 210a may be connected to the memory block BLKa through a ground selection line GSL, a plurality of word lines WL1 to WLm, and a string selection line SSL. The vertical transfer transistors TR1 to TRm may connect the plurality of word lines WL1 to WLm to the corresponding word line driving signal lines SI1 to SIm, respectively. The vertical transfer transistors TRs may connect the string selection lines SSL to the corresponding string selection line driving signal lines SS. The vertical transfer transistor TRg may connect the ground selection line GSL to the corresponding ground selection line driving signal line GS. Drains of the vertical transfer transistors TRs, TR1 to TRm, and TRg may be connected to the memory block BLKa. For example, when the block selection signal is activated, the vertical transfer transistors TRs, TR1 to TRm, and TRg may supply driving signals supplied through the string selection line driving signal line SS, the word line driving signal lines SI1 to SIm, and the ground selection line driving signal line GS to the string selection line SSL, the plurality of word lines WL1 to WLm, and the ground selection line GSL, respectively.

In exemplary embodiments of the inventive concept, the vertical transfer transistors TRs and TR1 to TRm may be implemented by vertical transfer transistors. In the present specification, a "vertical transfer transistor" may be a transistor including a vertical channel. For example, the vertical transfer transistors TRs and TR1 to TRm may be arranged in a staircase region (e.g., SA of fig. 6) of the word line. In one exemplary embodiment of the inventive concept, the vertical pass transistor TRg may be implemented by a common pass transistor. In the present specification, a "normal transfer transistor" may be a transistor including a horizontal channel. For example, the vertical transfer transistor TRg may be disposed in a decoder area (e.g., DAa of fig. 23), which will be described in detail with reference to fig. 6 to 8.

Fig. 6 is a cross-sectional view illustrating a memory device 10a including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concepts.

Referring to fig. 6, the memory device 10a may include a memory cell array 100a, a plurality of vertical transfer transistors TR1 to TRm and TRs, and a plurality of driving signal lines SI1 to SIm and SS. For example, the memory device 10a may correspond to a portion of the first semiconductor layer L1 of fig. 2, and the page buffer or the control logic may be disposed below the memory cell array 100a, the plurality of vertical transfer transistors TR1 to TRm and TRs, and the plurality of driving signal lines SI1 to SIm and SS in the vertical direction VD.

The memory cell array 100a may be arranged in the cell region CA, and may include a plurality of word lines WL1 to WLm. The plurality of word lines WL1 to WLm may be stacked in the vertical direction VD and may extend in the first horizontal direction HD 1. The plurality of word lines WL1 to WLm may be electrically insulated by a plurality of insulating layers. One end of each of the plurality of word lines WL1 to WLm in the first horizontal direction HD1 may be implemented in a stepped shape. In the present specification, the stepped shape is located in the stepped region SA.

In addition, the memory cell array 100a may further include a common source line CSL disposed below the plurality of word lines WL1 to WLm. In an exemplary embodiment of the inventive concept, the common source line CSL and the plurality of driving signal lines SI1 through SIm and SS may be disposed at the same level. For example, the common source line CSL and the plurality of driving signal lines SI1 to SIm and SS may be arranged at the same level in the first horizontal direction HD 1. In an exemplary embodiment of the inventive concept, the common source line CSL and the plurality of driving signal lines SI1 through SIm and SS may be implemented by the metal layer MT. For example, the common source line CSL may be implemented by a metal plate or a conductive flat plate of the metal layer MT.

In addition, the memory cell array 100a may further include a vertical channel structure VP. The vertical channel structure VP may extend in a vertical direction VD and may pass through a plurality of word lines WL1 to WLm and a plurality of insulating layers. The vertical channel structure VP may be referred to as a vertical pillar. In exemplary embodiments of the inventive concept, the vertical channel structure VP may have a first width W1 in the first horizontal direction HD 1. For example, the plurality of vertical channel structures VP may be annularly formed. In this case, the first width W1 may correspond to a first channel hole size. However, the inventive concept is not limited thereto. The vertical channel structures VP may be in the form of elliptical or rectangular columns. The plurality of vertical channel structures VP may be spaced apart from each other along the first horizontal direction HD1 and the second horizontal direction HD 2.

In one exemplary embodiment of the inventive concept, the vertical channel structure VP may include a charge storage layer CS, a channel layer CL, and an inner layer I. The channel layer CL may include a first type (e.g., p-type) silicon material, and may serve as a channel region. The inner layer I may comprise an insulating material such as silicon oxide or an air gap. The charge storage layer CS may include a gate insulating layer (also referred to as a "tunneling insulating layer"), a charge trap layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure.

Drain or drain contacts DR are respectively arranged on the plurality of vertical channel structures VP. For example, the drain or drain contact DR may include a silicon material doped with a second type (e.g., n-type) impurity. The bit lines BL may be disposed above the drain contacts DR and may be connected to the drain contacts DR through bit line contacts BLC, respectively.

In addition, the memory cell array 100a may further include a ground selection line GSL between the plurality of word lines WL1 to WLm and the common source line CSL and a string selection line SSL arranged above the plurality of word lines WL1 to WLm. In fig. 6, it is shown that the memory device 10a includes one string select line SSL. However, the inventive concept is not limited thereto. In some embodiments of the inventive concept, the memory device 10a may include two string selection lines (e.g., SSLu and SSLd of fig. 12) stacked in the vertical direction VD.

The plurality of vertical transfer transistors TR1 to TRm and TRs may be arranged in the staircase region SA of the plurality of word lines WL1 to WLm. A plurality of vertical transfer transistors TR1 to TRm may be respectively connected between the corresponding word line and the corresponding word line driving signal line. For example, the first vertical transfer transistor TR1 may be connected between the first word line WL1 and the first word line driving signal line SI1, the second vertical transfer transistor TR2 may be connected between the second word line WL2 and the second word line driving signal line SI2, and the mth vertical transfer transistor TRm may be connected between the mth word line WLm and the mth word line driving signal line SIm. The vertical transfer transistor TRs may be connected between a string selection line SSL and a string selection line driving signal line SS.

Each of the plurality of vertical transfer transistors TR1 to TRm and TRs may include a vertical channel VC extending in the vertical direction VD. For example, the vertical channel VC of the first vertical transfer transistor TR1 may extend vertically from the first word line driving signal line SI 1. The vertical channel VC may have a second width W2 greater than the first width W1 on the same level, and the width of the vertical channel VC between the gate GT and the first word line WL1 may be greater than the width of the vertical channel VC under the gate GT. Therefore, the breakdown (breakdown) problem associated with the plurality of vertical transfer transistors TR1 to TRm and TRs can be solved. For example, the second width W2 may be no less than about twice the first width W1. However, the inventive concept is not limited thereto. According to an exemplary embodiment of the inventive concept, the first width W1 and the second width W2 may vary. In an exemplary embodiment of the inventive concept, heights of the plurality of vertical channels VC in the vertical direction VD may be equal to each other as the first height H1. In an exemplary embodiment of the inventive concept, the top surface level of the plurality of vertical channels VC may be lower than the bottom surface level of the first word line WL 1. In an exemplary embodiment of the inventive concept, the top surface levels of the plurality of vertical channels VC may be disposed between the bottom surface level of the first word line WL1 and the gate GT.

In an exemplary embodiment of the inventive concept, the vertical channel VC may be formed to have the same structure as that of the vertical channel structure VP through the same process as that of the vertical channel structure VP. Accordingly, the vertical channel VC may also include a charge storage layer CS, a channel layer CL, and an inner layer I. However, the inventive concept is not limited thereto. In some embodiments of the inventive concept, the vertical channel VC may include only the channel layer CL and the inner layer I.

Further, the vertical channels VC respectively included in the plurality of vertical transfer transistors TR1 to TRm and TRs may be commonly connected to the gate GT. In the current embodiment, the gate GT commonly connected to the plurality of vertical transfer transistors TR1 to TRm and TRs may be arranged at the same level as that of the ground selection line GSL. In some embodiments of the inventive concept, the vertical channels VC included in the plurality of vertical transfer transistors TR1 to TRm and TRs may be respectively connected to different gates GT, and lengths of the different gates GT in the vertical direction VD may be different from each other. Therefore, the driving capabilities of the plurality of vertical transfer transistors TR1 to TRm and TRs may be different from each other.

In some embodiments of the inventive concept, the length of the gate GT in the vertical direction VD may be equal to the length of the ground selection line GSL in the vertical direction VD. However, the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, the length of the gate GT in the vertical direction VD may be equal to the length of each of the word line WL1 to the word line WLm in the vertical direction VD. However, the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, a length of the gate GT in the vertical direction VD may be equal to a length of the string selection line SSL in the vertical direction VD. However, the inventive concept is not limited thereto.

The plurality of contacts CP1 to CPm and CPs may be arranged on the plurality of vertical transfer transistors TR1 to TRm and TRs, respectively. The plurality of vertical transfer transistors TR1 to TRm may be connected to the corresponding word lines WL1 to WLm through corresponding contacts CP1 to CPm, respectively, and the vertical transfer transistors TRs may be connected to the string selection line SSL through contacts CPs. In an exemplary embodiment of the inventive concept, heights of the plurality of contacts CP1 to CPm and CPs in the vertical direction VD may be equal to each other as a second height H2. For example, the top surface level of the plurality of contacts CP1 to CPm and CPs may be equal to the top surface level of the string select line SSL.

In one exemplary embodiment of the inventive concept, the row decoder 220a may be adjacent to the plurality of vertical transfer transistors TR1 to TRm and TRs in the first horizontal direction HD1 or the second horizontal direction HD 2. However, the inventive concept is not limited thereto. At least one of the block decoder 221 and the driving signal line decoder 222a may be disposed below the plurality of vertical transfer transistors TR1 to TRm and TRs in the vertical direction VD.

Fig. 7 is a cross-sectional view illustrating a memory device 10b including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concepts.

Referring to fig. 7, the memory device 10b may include a first semiconductor layer L1 and a second semiconductor layer L2, and may correspond to a modification of the memory device 10a shown in fig. 6. The second semiconductor layer L2 may include a substrate SUB, a first lower insulating layer IL21, and a second lower insulating layer IL 22. For example, the control logic 230 or the page buffer 240 of fig. 1 may be disposed in the second semiconductor layer L2.

The substrate SUB may be a semiconductor substrate including a semiconductor material such as single crystal silicon or single crystal germanium (Ge), and may be manufactured from a silicon wafer. The first and second lower insulating layers IL21 and IL22 may be formed of an insulating material such as silicon oxide by a Chemical Vapor Deposition (CVD) process or a spin-on process. A plurality of semiconductor devices including the transistors TR may be formed on the substrate SUB included in the second semiconductor layer L2. The transistor TR may be electrically connected to the metal pattern MP21 formed in the second lower insulating layer IL22 through a contact CP21, the contact CP21 passing through the first lower insulating layer IL 21.

The first semiconductor layer L1 may be stacked on the second semiconductor layer L2. For example, the pass transistor circuit 210a and the memory block BLKa of fig. 5 may be disposed in the first semiconductor layer L1. The first semiconductor layer L1 may include a base layer BP and an upper insulating layer IL 1. In exemplary embodiments of the inventive concept, the base layer BP may be formed of polycrystalline silicon through a sputtering process, a CVD process, an Atomic Layer Deposition (ALD) process, or a Physical Vapor Deposition (PVD) process.

In exemplary embodiments of the inventive concept, the base layer BP may be formed by forming an amorphous silicon layer on the second lower insulating layer IL22 and changing the amorphous silicon layer into a single crystal silicon layer by performing a heat treatment on the amorphous silicon layer or irradiating a laser beam onto the amorphous silicon layer. Accordingly, the defect in the base layer BP can be removed. In exemplary embodiments of the inventive concept, the base layer BP may be formed through a wafer bonding process. In this case, the base layer BP may be formed on the second lower insulating layer IL22 by attaching a single crystal silicon wafer to the second lower insulating layer IL22 and partially removing or planarizing the top of the single crystal silicon wafer.

The first wordline drive signal line SI1 may be disposed on the base layer BP and may extend in the second horizontal direction HD 2. The first word line driving signal line SI1 may be electrically connected to the transistor TR included in the second semiconductor layer L2 through contacts CP11, CP21, and CP12 and metal patterns MP11 and MP 21. For example, the transistor TR formed in the second semiconductor layer L2 may configure a circuit corresponding to the driving signal line decoder 222a of fig. 5.

Fig. 8 illustrates a row decoder 220a 'and a pass transistor circuit 210a' according to an exemplary embodiment of the inventive concept.

Referring to fig. 8, the memory block BLKa' may correspond to one of the memory blocks BLK1 through BLKi of fig. 3. Compared to the memory block BLKa of fig. 5, the memory block BLKa' may further include first to fourth dummy word lines DWL1, DWL2, DWL3, and DWL 4. The first and second dummy word lines DWL1 and DWL2 may be disposed between the ground selection line GSL and the first word line WL1, and the third and fourth dummy word lines DWL3 and DWL4 may be disposed between the m-th word line WLm and the string selection line SSL. In some embodiments of the inventive concept, the memory block BLKa' may include at least one of the first to fourth dummy word lines DWL1 to DWL 4. According to an exemplary embodiment of the inventive concept, the number of dummy word lines included in the memory block BLKa' may vary.

The row decoder 220a 'may correspond to a variation of the row decoder 220a of fig. 5, and the pass transistor circuit 210a' may correspond to a variation of the pass transistor circuit 210 of fig. 5. Compared to the transfer transistor circuit 210 of fig. 5, the transfer transistor circuit 210a' may further include vertical transfer transistors TRd1, TRd2, TRd3, and TRd 4. The vertical transfer transistors TRd1 to TRd4 may connect the dummy word lines DWL1 to DWL4 to the corresponding dummy word line driving signal lines DSI1, DSI2, DSI3, and DSI4, respectively.

Fig. 9 is a cross-sectional view schematically illustrating a memory device 10a' including the pass transistor circuit of fig. 8, according to an exemplary embodiment of the inventive concepts.

Referring to fig. 9, the memory device 10a' may include: the memory cell array 100a', a plurality of vertical transfer transistors TR1 to TRm, TRs, and TRd1 to TRd4, word line driving signal lines SI1 to SIm, a string selection line driving signal line SS, and dummy word line driving signal lines DSI1 to DSI 4. The plurality of vertical transfer transistors TR1 to TRm, TRs, and TRd1 to TRd4 may be commonly connected to the same gate GT. The length in the vertical direction VD of the contacts CPd respectively disposed above the dummy word line driving signal lines DSI1 to DSI4 may be equal to the length in the vertical direction VD of the contacts CP1, CP2, and CPm respectively disposed above the word line driving signal lines SI1 to SIm. The memory device 10a' corresponds to a variant of the memory device 10a of fig. 6. The contents described above with reference to fig. 6 and 7 are applied to the current embodiment.

Fig. 10 is a top view illustrating a memory device 10c including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concepts. Fig. 11 is a sectional view taken along line XI-XI' of fig. 10 according to an exemplary embodiment of the inventive concept.

Referring to fig. 10 and 11, a plurality of driving signal lines SI1, SI2, SI3, and SI4 and SS1, SS2, SS3, and SS4 and a common source line CSL may be disposed at the same level. For example, the plurality of driving signal lines SI1 to SI4 and SS1 to SS4 and the common source line CSL may be formed through the same process. In an exemplary embodiment of the inventive concept, the plurality of driving signal lines SI1 to SI4 and SS1 to SS4 extend in the second horizontal direction HD2 and may be spaced apart from each other in the first horizontal direction HD 1. In an exemplary embodiment of the inventive concept, the common source line CSL extends in the second horizontal direction HD2, and may be implemented by a metal plate. The plurality of driving signal lines SI1 to SI4 and SS1 to SS4 may also be implemented by metal plates.

The first to fourth word lines WL1 to WL4 may be formed in a staircase shape in the staircase region SA. The first word line WL1 may be disposed above the gate GT in the vertical direction VD and may include a tungsten region W and a nitride region NT. Here, the tungsten region W may include, for example, a conductive material such as W without limitation thereto. Contact CP1 may pass through tungsten region W of first word line WL 1. In addition, the nitride region NT may include an insulating material such as nitride without being limited to nitride. The second to fourth word lines WL2 to WL4 may be sequentially stacked above the first word line WL1 in the vertical direction VD. The first word line WL1 may be connected to the vertical channel VC1 through a contact CP1, and the vertical channel VC1 may be connected to the first word line driving signal line SI 1. The third word line WL3 may be connected to the vertical channel VC2 through a contact CP3, and the vertical channel VC2 may be connected to a third word line driving signal line SI 3. The third word line WL3 may also include a tungsten region W through which the contact CP3 passes. The first to fourth word lines WL1 to WL4 may extend in the first horizontal direction HD1, and the word lines arranged at the same level may be divided by a word line cutting region WLC.

The first upper string selection line SSLu1, the second upper string selection line SSLu2, the third upper string selection line SSLu3, and the fourth upper string selection line SSLu4 may be arranged at the same level and may be separated by a string selection line cutting region SSLC. The first upper string selection line SSLu1 may be connected to the vertical channel VC3 through contacts CPs1, and the vertical channel VC3 may be connected to the string selection line driving signal line SS 1. The second upper string selection line SSLu2 may be connected to the vertical channel VC4 through contacts CPs2, and the vertical channel VC4 may be connected to the string selection line driving signal line SS 2. The first string select line SSLu1 and the second upper string select line SSLu2 may include tungsten W.

Fig. 12 is a cross-sectional view illustrating a memory device 10d including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concepts.

Referring to fig. 12, the memory device 10d may include a memory cell array 100a, a transfer transistor circuit 210a, and a block decoder 221a, and the block decoder 221a may be disposed below the transfer transistor circuit 210a in a vertical direction VD. The memory device 10d corresponds to a modification of the memory device 10c of fig. 11, and the description of the memory device 10c given previously is omitted.

The gate GT commonly connected to the vertical channel VC may be connected to the block decoder 221a through a wiring including contacts CP13, CP14, CP22, and CP23, and metal patterns MP12, MP21, and MP 22. In other words, the block selection signal BS output from the block decoder 221a may be supplied to the gate GT through a wiring including the contacts CP13, CP14, CP22, and CP23 and the metal patterns MP12, MP21, and MP 22. In this case, the block selection signal BS may turn on a transistor connected to the gate GT. The metal patterns MP21 and MP22, the contacts CP22 and CP23, and the block decoder 221a may be disposed in the second semiconductor layer L2 of fig. 2.

Fig. 13 is a cross-sectional view illustrating a memory device 10e including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concepts.

Referring to fig. 13, the memory device 10e may include a memory cell array 100a, a transfer transistor circuit 210a, a block decoder 221b, and a peripheral circuit 200a, and the peripheral circuit 200a may be disposed below the transfer transistor circuit 210a in a vertical direction VD. In this case, the block decoder 221b may be adjacent to the peripheral circuit 200a in the first horizontal direction HD 1. However, the inventive concept is not limited thereto. The block decoder 221b may be adjacent to the peripheral circuit 200a in the second horizontal direction HD 2. The memory device 10e corresponds to a modification of the memory device 10c of fig. 11, and the description of the memory device 10c given previously is omitted.

The gate GT commonly connected to the vertical channel VC may be connected to the block decoder 221b through a wiring including contacts CP13, CP14, CP22, and CP23, and metal patterns MP12, MP21, and MP 22. In other words, the block selection signal BS output from the block decoder 221b may be supplied to the gate GT through a wiring including the contacts CP13, CP14, CP22, and CP23 and the metal patterns MP12, MP21, and MP 22. For example, the metal patterns MP21 and MP22, the contacts CP22 and CP23, the block decoder 221b, and the peripheral circuit 200a may be disposed in the second semiconductor layer L2 of fig. 2.

Fig. 14 is a top view illustrating a memory device 10f including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concepts.

Referring to fig. 14, the plurality of driving signal lines SI1 to SI4 and SS1 to SS4 and the common source line CSL may be disposed at the same level. For example, the plurality of driving signal lines SI1 to SI4 and SS1 to SS4 extend in the second horizontal direction HD2, and may be spaced apart from each other by a certain distance in the first horizontal direction HD 1. The gate GT may be disposed above the plurality of driving signal lines SI1 to SI4 and SS1 to SS4 in the vertical direction VD, and may extend in the first horizontal direction HD 1. The first to fourth word lines WL1 to WL4 may be sequentially stacked above the gate GT in the vertical direction VD.

Fig. 15 is a cross-sectional view taken along line XV-XV' of fig. 14, according to an exemplary embodiment of the inventive concept.

Referring to fig. 15, contacts CP11 may be disposed on a plurality of driving signal lines SI1 to SI4 and SS1 to SS4, respectively, and a plurality of driving signal lines SI1 to SI4 and SS1 to SS4 may be electrically connected to the metal pattern MP11 through contacts CP11, respectively. In this case, the driving signal line decoder 222 may be disposed below the plurality of driving signal lines SI1 to SI4 and SS1 to SS4 in the vertical direction VD. The driving signal line decoder 222 may be disposed in the second semiconductor layer L2 of fig. 2.

Fig. 16 is a cross-sectional view taken along line XVI-XVI' of fig. 14, according to an exemplary embodiment of the inventive concept.

Referring to fig. 16, the word line driving signal line SI1 may be connected to the driving signal line decoder 222 through a wiring including contacts CP11, CP12', CP15, and CP16, and metal patterns MP11, MP13, and MP 14. In other words, the driving signal line decoder 222 may supply the word line driving signal to the first word line driving signal line SI1 through a wiring including the contacts CP11, CP12', CP15, and CP16, and the metal patterns MP11, MP13, and MP 14. For example, the word line driving signals may have the voltage levels shown in fig. 17.

Fig. 17 illustrates voltages applied to word line driving signal lines through a memory operation according to an exemplary embodiment of the inventive concepts.

Referring to fig. 17, a selected word line driving signal line SIa corresponds to a driving signal line connected to a selected word line WLsel, and an unselected word line driving signal line SIb may correspond to a driving signal line connected to an unselected word line WLunsel. During a program operation, a program voltage Vpgm (e.g., about 20V) may be applied to the selected word line driving signal line SIa, and a pass voltage Vpass (e.g., about 9V) may be applied to the unselected word line driving signal line SIb. In example embodiments of the inventive concepts, the program voltage Vpgm may be about 10V to about 25V, and the pass voltage Vpass may be about 5V to about 15V. During a read operation, a read voltage Vr (e.g., about 0V) may be applied to the selected word line driving signal line SIa, and a read pass voltage Vread (e.g., about 6V) may be applied to the unselected word line driving signal lines SIb. In an exemplary embodiment of the inventive concept, the read voltage Vr may be about-1V to about 10V, and the read pass voltage Vread may be about 4V to about 10V. During an erase operation, an erase voltage Ver (e.g., about 0V) is applied to both the selected wordline drive signal line SIa and the unselected wordline drive signal line SIb. In one exemplary embodiment of the inventive concept, the erase voltage Ver may be about-2V to about 3V.

Fig. 18 illustrates a row decoder 220b and a pass transistor circuit 210b according to an exemplary embodiment of the inventive concepts.

Referring to fig. 18, the memory block BLKb may correspond to one of the memory blocks BLK1 through BLKi of fig. 3, and "b" may be a positive integer. The row decoder 220b may correspond to a variation of the row decoder 220a of fig. 5, and the pass transistor circuit 210b may correspond to a variation of the pass transistor circuit 210a of fig. 5. Therefore, the description previously given with reference to fig. 1 to 8 may be applied to the current embodiment. The row decoder 220b may include a block decoder 221 and a driving signal line decoder 222 b. The transfer transistor circuit 210b may include a plurality of vertical transfer transistors TRs, TR1 to TRm, TRg, and TRgd.

The driving signal line decoder 222b may be connected to the transfer transistor circuit 210b through a string selection line driving signal line SS, word line driving signal lines SI1 to SIm, a ground selection line driving signal line GS, and a Gate Induced Drain Leakage (GIDL) gate driving signal line GDS. For example, the string selection line driving signal line SS, the word line driving signal lines SI1 to SIm, the ground selection line driving signal line GS, and the GIDL gate driving signal line GDS may be connected to the plurality of vertical transfer transistors TRs, TR1 to TRm, TRg, and TRgd, respectively.

The pass transistor circuit 210b may be connected to the memory block BLKb through a ground selection line GSL, a plurality of word lines WL1 to WLm, a string selection line SSL, and a GIDL gate line GIDL. The vertical transfer transistor TRgd may be connected to a GIDL gate driving signal line GDS corresponding to the GIDL gate line GIDL. For example, when the block selection signal is activated, the plurality of vertical transfer transistors TRs, TR1 to TRm, TRg, and TRgd may supply driving signals supplied through the string selection line driving signal line SS, the word line driving signal lines SI1 to SIm, the ground selection line driving signal line GS, and the GIDL gate driving signal line GDS to the string selection line SSL, the plurality of word lines WL1 to WLm, the ground selection line GSL, and the GIDL gate line GIDL, respectively.

In an exemplary embodiment of the inventive concept, the plurality of vertical transfer transistors TRs, TR1 to TRm, and TRg may be implemented by vertical transfer transistors. For example, a plurality of vertical transfer transistors TRs, TR1 to TRm, and TRg may be arranged in a staircase region (e.g., SA of fig. 6) of the word line. In exemplary embodiments of the inventive concept, the vertical transfer transistor TRgd may be implemented by a general transfer transistor. For example, the vertical transfer transistor TRgd may be disposed in a decoder area (e.g., DAa of fig. 23), which will be described in detail with reference to fig. 19.

Fig. 19 is a cross-sectional view illustrating a memory device 10g including the pass transistor circuit of fig. 18 according to an exemplary embodiment of the inventive concepts.

Referring to fig. 19, the memory device 10g may include: a memory cell array 100b, a plurality of vertical transfer transistors TR1 to TRm, TRs, and TRg, and a plurality of driving signal lines SI1 to SIm, SS, and GS. The memory device 10g corresponds to a modification of the memory device 10a of fig. 6, and the description of the memory device 10a given previously is omitted.

The memory cell array 100b may be arranged in the cell region CA, and may include a string selection line SSL, a plurality of word lines WL1 through WLm, a ground selection line GSL, a GIDL gate line GIDL, and a common source line CSL. The string selection line SSL, the plurality of word lines WL1 to WLm, the ground selection line GSL, and the GIDL gate line GIDL may be stacked in the vertical direction VD and may extend in the first horizontal direction HD 1. The string selection line SSL, the plurality of word lines WL1 to WLm, the ground selection line GSL, and the GIDL gate line GIDL may be electrically insulated by a plurality of insulating layers.

The plurality of vertical transfer transistors TR1 to TRm, TRs, and TRg may be arranged in the staircase region SA of the plurality of word lines WL1 to WLm. The vertical transfer transistor TRg may be connected between the ground selection line GSL and the ground selection line driving signal line GS. The vertical channels VC respectively included in the plurality of vertical transfer transistors TR1 to TRm, TRs, and TRg may be commonly connected to the gate GT. In the current embodiment, the gate GT commonly connected to the vertical channels VC respectively included in the plurality of vertical transfer transistors TR1 to TRm, TRs, and TRg may be disposed at the same level as that of the GIDL gate line GIDL.

The plurality of contacts CP1 to CPm, CPs, and CPg may be disposed on the plurality of vertical transfer transistors TR1 to TRm, TRs, and TRg, respectively. The plurality of vertical transfer transistors TR1 to TRm may be connected to the corresponding word lines WL1 to WLm through corresponding contacts CP1 to CPm, respectively, the vertical transfer transistors TRs may be connected to the string selection line SSL through contacts CPs, and the vertical transfer transistor TRg may be connected to the ground selection line GSL through a contact CPg. In an exemplary embodiment of the inventive concept, heights of the plurality of contacts CP1 to CPm, CPs, and CPg in the vertical direction VD may be equal to each other as a second height H2'.

In an exemplary embodiment of the inventive concept, the row decoder 220b may be adjacent to the plurality of vertical transfer transistors TR1 to TRm, TRs, and TRg in the first horizontal direction HD1 or the second horizontal direction HD 2. However, the inventive concept is not limited thereto. At least one of the block decoder 221 and the driving signal line decoder 222b of the row decoder 220b may be disposed below the plurality of vertical transfer transistors TR1 to TRm, TRs, and TRg in the vertical direction VD.

Fig. 20 is a perspective view illustrating a memory device 10h according to an exemplary embodiment of the inventive concept.

Referring to fig. 20, the memory device 10h may include a plurality of metal lines MT arranged parallel to each other in the first horizontal direction HD1 and extending in the second horizontal direction HD 2. The plurality of metal lines MT may include a common source line CSL and an m-th wordline driving signal line SIm arranged at the same level. For example, the common source line CSL may be formed of a metal plate, and the mth word line driving signal line SIm may be formed in a line shape.

The memory cell array (e.g., 100 of fig. 1) may be arranged above the common source line CSL. For example, the ground selection line GSL, the plurality of word lines WL1 to WLm, the lower string selection line SSLd, and the upper string selection line SSLu may be stacked above the common source line CSL in the vertical direction VD. The upper string selection lines SSLu may include first to fourth upper string selection lines (e.g., SSLu1 to SSLu4 of fig. 10) arranged at the same level. The plurality of vertical channel structures VP extend in the vertical direction VD and may pass through the ground selection line GSL, the plurality of word lines WL1 to WLm, the lower string selection line SSLd, and the upper string selection line SSLu.

Drain contacts DR are disposed on the plurality of vertical channel structures VP, respectively, and bit line contacts BLC may be disposed on the drain contacts DR, respectively. The drain contact DR may be implemented by a pillar (stud). Bit lines BL spaced apart from each other at a certain distance in the first horizontal direction HD1 and extending in the second horizontal direction HD2 are disposed on the bit line contacts BLC. In some embodiments of the inventive concept, the memory device 10h may not include the bit line contacts BLC, and the bit lines BL may be disposed above the drain contacts DR, respectively.

A pass transistor circuit (e.g., 210 of fig. 1) may be arranged above the mth word line driving signal line SIm. For example, the gate GTm may be disposed above the mth wordline driving signal line SIm, and a vertical channel VC extending in the vertical direction VD may pass through the gate GTm. The gate GTm and the vertical channel VC may configure a vertical transfer transistor TRm. A contact CPm extending in the vertical direction VD may be formed above the vertical channel VC, and the contact CPm may electrically connect the mth word line WLm to the vertical channel VC.

Further, contacts CP11 and CP11 'extending in the vertical direction VD may be disposed above the mth word line driving signal line SIm, and a metal pattern MP11 extending in the second horizontal direction HD2 may be disposed above the contact CP 11'. For example, contact CP11' may be disposed at the same level as the level of bit line contact BLC. For example, the metal pattern MP11 may be arranged at the same level as that of the bit line BL. In some embodiments of the inventive concept, the memory device 10d may not include the contact CP11', and the metal pattern MP11 may be disposed above the contact CP 11.

Fig. 21 is a perspective view illustrating a memory device 10i according to an exemplary embodiment of the inventive concept.

Referring to fig. 21, the memory device 10i may include a plurality of metal lines MT arranged parallel to each other in the first horizontal direction HD1 and extending in the second horizontal direction HD 2. The plurality of metal lines MT may include a common source line CSL and first to m-th wordline drive signal lines SI1 to SIm arranged at the same level. For example, the common source line CSL may be formed of a metal plate. Compared to the memory device 10h of FIG. 20, the memory device 10i according to the current embodiment may further include first to (m-1) th word line driving signal lines SI1 to SIm-1. Therefore, the description given previously with reference to fig. 20 may be applied to the current embodiment, and is omitted.

The plurality of vertical channels VC and the plurality of gates GT1 to GTm may be disposed above the first to mth wordline driving signal lines SI1 to SIm. The plurality of gates GT 1-GTm may extend along the first horizontal direction HD1 and may be spaced apart from each other by a distance along the second horizontal direction HD 2.

In exemplary embodiments of the inventive concept, lengths of the plurality of gates GT1 to GTm in the first horizontal direction HD1 may be different from each other. However, the inventive concept is not limited thereto. In some embodiments of the inventive concept, lengths of the plurality of gates GT1 to GTm in the first horizontal direction HD1 may be equal to each other. In an exemplary embodiment of the inventive concept, the plurality of gates GT1 to GTm may be arranged at the same level as that of the ground selection line GSL. However, the inventive concept is not limited thereto. In some embodiments of the inventive concept, the plurality of gates GT1 to GTm may be arranged at the same level as that of the GIDL gate line.

Further, a plurality of contacts CP1 to CPm extending in the vertical direction VD may be respectively arranged above the plurality of vertical channels VC, and the lengths of the plurality of contacts CP1 to CPm in the vertical direction VD may be equal to each other. For example, the vertical channel VC and the gate GT1 arranged above the first wordline drive signal line SI1 may configure the first vertical transfer transistor TR 1. A contact CP1 disposed above the first vertical transfer transistor TR1 may be electrically connected to the first word line WL 1. Further, the (m-1) th vertical transfer transistor TRm-1 may be configured by the vertical channel VC and the gate GTm-1 disposed above the (m-1) th word line driving signal line SIm-1. The contact CPm-1 disposed above the (m-1) th vertical transfer transistor TRm-1 may be electrically connected to the (m-1) th word line WLm-1.

On the other hand, the gate GT1 may be disposed above the first to mth wordline drive signal lines SI1 to SIm, only the contact CP1 among the contacts CP1 to CPm disposed above the vertical channel VC formed through the gate GT1 may be electrically connected to the first wordline WL1, and the other contacts CP2 to CPm may not be electrically connected to the first wordline WL 1. For example, the other contacts CP2 through CPm may be connected to a nitride region (e.g., NT of fig. 11) of the first word line WL1, thereby preventing the other contacts CP2 through CPm from being electrically connected to the first word line WL 1. Contact CP1 may be connected to the tungsten region (e.g., W of fig. 11) of first word line WL1, allowing contact CP1 to be electrically connected to first word line WL 1.

Further, the gate GTm-1 may be disposed above the (m-1) th and m-th word line driving signal lines SIm-1 and SIm, only a contact CPm-1 of contacts CPm-1 and CPm disposed above the vertical channel VC formed through the gate GTm-1 may be electrically connected to the (m-1) th word line WLm-1, and the other contact CPm may not be electrically connected to the (m-1) th word line WLm-1. For example, another contact CPm may be connected to a nitride region (e.g., NT of FIG. 11) of the (m-1) th word line WLm-1, thereby preventing the other contact CPm from being electrically connected to the (m-1) th word line WLm-1. The contact CPm-1 may be connected to a tungsten region (e.g., W of FIG. 11) of the (m-1) th word line WLm-1, thereby allowing the contact CPm-1 to be electrically connected to the (m-1) th word line WLm-1.

In addition, the plurality of metal lines MT may further include a metal line SI0, and the metal line SI0 may have the same structure as the first to mth word line driving signal lines SI1 to SIm. A contact CPb for receiving a block selection signal (e.g., BS of fig. 8) may be disposed on the gate GT 1. Contacts for receiving the block selection signal BS may also be arranged on the other gates GT2 to GTm.

Fig. 22 is a perspective view illustrating a memory device 10j according to an exemplary embodiment of the inventive concept.

Referring to fig. 22, a memory device 10j corresponds to a modification of the memory device 10i of fig. 21, and the memory device 10j may further include at least one common transfer transistor TRn arranged below the plurality of metal lines MT in the vertical direction VD, as compared to the memory device 10 i. For example, the plurality of metal lines MT, the vertical transfer transistors TR1 to TRm, the contacts CP1 to CPm, the contacts CP11, CP11' and CPb, the metal pattern MP11, the ground selection line GSL, the plurality of word lines WL1 to WLm, the lower string selection line SSLd, the upper string selection line SSLu, and the vertical channel structure VP may be disposed in the first semiconductor layer (e.g., L1 of fig. 2). The normal transfer transistor TRn may be disposed in the second semiconductor layer (e.g., L2 of fig. 2).

In an exemplary embodiment of the inventive concept, the memory device 10j may include the active region 101, the gate insulating layer 102, and the gate electrode layer GTp, and the active region 101, the gate insulating layer 102, and the gate electrode layer GTp may configure the common transfer transistor TRn. The gate electrode layer GTp may extend in the first horizontal direction HD 1. Contacts CP24 and CP25 extending in the vertical direction VD may be disposed on the active region 101. For example, contacts CP24 and CP25 may correspond to a source contact and a drain contact, respectively. The metal pattern MP24 extending in the second horizontal direction HD2 may be disposed on the contact CP24, and the metal pattern MP25 extending in the first horizontal direction HD1 may be disposed on the contact CP 25. For example, the metal pattern MP24 may be arranged above the metal pattern MP25 in the vertical direction VD. However, the inventive concept is not limited thereto.

According to the current embodiment, the memory device 10j may include a hybrid transfer transistor circuit including vertical transfer transistors TR1 to TRm and a normal transfer transistor TRn. For example, the common transfer transistor TRn may be connected to the ground selection line GSL. However, the inventive concept is not limited thereto.

Fig. 23 illustrates a top surface of the memory device 20 according to a comparative example and a top surface of the memory device 30 according to an exemplary embodiment of the inventive concepts. Fig. 24 is an enlarged view of the first region 21 and the second region 31 of fig. 23.

Referring to fig. 23 and 24, the memory device 20 may include first and second cell regions CAa and CAb, first and second transfer transistor circuit regions PAa and PAb, first and second decoder regions DAa 'and DAb', and a PAD region PAD. The memory device 20 may have a first chip size CS1 in the second horizontal direction HD 2.

The first memory cell array is disposed in the first cell area CAa, and the second memory cell array may be disposed in the second cell area CAb. In the first transfer transistor circuit area PAa, a plurality of transfer transistors connected to gate lines, in other words, a string selection line, a ground selection line, and a word line included in the first memory cell array may be arranged. In the second transfer transistor circuit area PAb, a plurality of transfer transistors connected to the gate lines, in other words, a string selection line, a ground selection line, and a word line included in the second memory cell array may be arranged. In the first decoder area DAa', a row decoder and a transfer transistor connected to the first memory cell array may be disposed. In the second decoder region DAb', a row decoder and a transfer transistor connected to the second memory cell array may be arranged.

For example, the first area 21 may include a portion of the first unit area CAa and a first decoder area DAa'. A portion of the first cell region CAa may include a cell region CA in which a vertical channel structure (e.g., VP of fig. 6) is disposed and a staircase region SA of a word line. The first decoder area DAa' may include an area in which the transfer transistor circuit is disposed and an area in which the row decoder is disposed. In this case, the transfer transistor circuit may include a normal transfer transistor (in other words, a planar transfer transistor). As described above, the ratio of the region in which the transfer transistor circuit is arranged to the first decoder region DAa' is very high. Thus, the first chip size CS1 of the memory device 20 may be large.

On the other hand, the memory device 30 according to an exemplary embodiment of the inventive concept may include first and second unit areas CAa and CAb, first and second decoder areas DAa and DAb, and a PAD area PAD. The memory device 30 may have a second chip size CS2 in the second horizontal direction HD 2. The first memory cell array may be disposed in the first cell area CAa, and the second memory cell array may be disposed in the second cell area CAb. Row decoders connected to the first memory cell array may be disposed in the first decoder area DAa, and row decoders connected to the second memory cell array may be disposed in the second decoder area DAb.

According to the current embodiment, the memory device 30 does not include the first pass transistor circuit region PAa and the second pass transistor circuit region PAb, as compared to the memory device 20. Further, the lengths of the first and second decoder regions DAa and DAb in the second horizontal direction HD2 may be smaller than the lengths of the first and second decoder regions DAa 'and DAb' in the second horizontal direction HD 2. Accordingly, the second chip size CS2 may be smaller than the first chip size CS 1.

For example, the second area 31 may include a portion of the first unit area CAa and the first decoder area DAa. A portion of the first cell region CAa may include a cell region CA in which a vertical channel structure (e.g., VP of fig. 6) is arranged and a staircase region SA of word lines. The first decoder area DAa may include an area in which a row decoder (e.g., 220 of fig. 1) is disposed. In one exemplary embodiment of the inventive concept, the transfer transistor may be implemented by a vertical transfer transistor, and the vertical transfer transistor may be disposed in the stepped region SA of the word line. Accordingly, a region in which the pass transistor circuit (e.g., 210 of fig. 1) is disposed may be included in the first cell region CAa. Accordingly, the length of the first decoder area DAa in the second horizontal direction HD2 may be smaller than the length of the first decoder area DAa' in the second horizontal direction.

Fig. 25 is a top view illustrating a first surface of a first semiconductor layer 300 included in a memory device according to an exemplary embodiment of the inventive concepts.

Referring to fig. 25, the first semiconductor layer 300 may include a plurality of driving signal lines SI1 to SI4 and SS1 to SS4 and a common source line CSL arranged at the same level. For example, the plurality of driving signal lines SI1 to SI4 and SS1 to SS4 extend in the second horizontal direction HD2, and may be spaced apart from each other by a certain distance in the first horizontal direction HD 1. The gate GT is arranged above the plurality of driving signal lines SI1 to SI4 and SS1 to SS4 in the vertical direction VD, and may extend in the first horizontal direction HD 1. The first to fourth word lines WL1 to WL4 may be sequentially stacked above the gate GT in the vertical direction VD. In exemplary embodiments of the inventive concept, in the first semiconductor layer 300, a substrate may be disposed on a second surface facing the first surface. Accordingly, the plurality of driving signal lines SI1 to SI4 and SS1 to SS4 and the common source line CSL may be disposed on the substrate.

Fig. 26 and 27 illustrate a memory device 40 according to an exemplary embodiment of the inventive concept. For example, the first semiconductor layer 300 of fig. 26 shows a cross section taken along the line XXVI-XXVI 'of fig. 25, and the first semiconductor layer 300 of fig. 27 shows a cross section taken along the line XXVII-XXVII' of fig. 25.

Referring to fig. 26 and 27, the first semiconductor layer 300 may be bonded to the second semiconductor layer 400 by, for example, Cu-to-Cu (C2C) wafer bonding. In this case, a plurality of bonding pads PD1a and PD1b may be formed on the first surface of the first semiconductor layer 300, and a plurality of bonding pads PD2a and PD2b may be formed on the first surface of the second semiconductor layer 400. Accordingly, the first semiconductor layer 300 of fig. 25 is turned over, and thus the first surface of the first semiconductor layer 300 may be bonded with the first surface of the second semiconductor layer 400. In one exemplary embodiment, an input/output (I/O) pad forming process and a back lap process may be sequentially performed on the second surface of the first semiconductor layer 300.

The gate GT may be connected to the transistor 440 through a wiring including the contact 310, the metal pattern 330, and the bonding pad PD1a included in the first semiconductor layer 300, and the bonding pad PD2a, the contacts 410 and 430, and the metal pattern 420 included in the second semiconductor layer 400. In addition, the word line driving signal line SI1 may be connected to the transistor 480 through a wiring including the contact 320 and the bonding pad PD1b included in the first semiconductor layer 300, and the bonding pad PD2b, the contacts 450 and 470, and the metal pattern 460 included in the second semiconductor layer 400.

Fig. 28 illustrates a structure of a memory device 50 according to an exemplary embodiment of the inventive concepts.

Referring to fig. 1 and 28, the memory device 50 may include a first semiconductor layer L1 'and a second semiconductor layer L2', and the second semiconductor layer L2 'may be stacked on the first semiconductor layer L1' in the vertical direction VD. For example, the first semiconductor layer L1 'and the second semiconductor layer L2' may be bonded by wafer bonding, and the second semiconductor layer L2 'may be disposed above the first semiconductor layer L1' in the vertical direction VD.

In exemplary embodiments of the inventive concept, the memory cell array 100, the transfer transistor circuit 210, and the row decoder 220 may be formed in the first semiconductor layer L1', and the control logic 230 and the page buffer 240 may be formed in the second semiconductor layer L2'. Accordingly, the memory device 50 may have a structure in which the memory cell array 100 is disposed under a portion of the peripheral circuit, in other words, a Peripheral Over Cell (POC) structure. In the POC structure, the horizontal direction area can be reduced, and the integration degree of the memory device 50 can be increased.

In exemplary embodiments of the inventive concept, each of the first and second semiconductor layers L1 'and L2' may include a substrate, and the first and second semiconductor layers L1 'and L2' may be bonded by C2C wafer bonding after the memory cell array 100, the pass transistor circuit 210, and the row decoder 220 are formed in the first semiconductor layer L1 'and the circuits including the control logic 230 and the page buffer 240 are formed in the second semiconductor layer L2'.

Fig. 29 is a cross-sectional view illustrating the memory device 50 of fig. 28 according to an exemplary embodiment of the inventive concepts.

Referring to fig. 29, the first semiconductor layer L1' may include a first substrate SUB1, a plurality of driving signal lines SI1 to SI4 and SS1 to SS4, a common source line CSL, a gate GT, a ground selection line GSL, word lines WL1 to WLm, a lower string selection line SSLd, and an upper string selection line SSLu. In addition, the first semiconductor layer L1' may further include a plurality of vertical channels 510, a plurality of contacts 520, and a plurality of bonding pads PD1 connected to the plurality of contacts 520, respectively. In addition, the first semiconductor layer L1' may further include a plurality of vertical channel structures 530. The second semiconductor layer L2' may include a second substrate SUB2, a transistor TR, metal layers 540 and 550, a contact 560, and a plurality of bond pads PD 2.

Fig. 30 is a block diagram illustrating an example in which a memory device according to an exemplary embodiment of the inventive concept is applied to a Solid State Drive (SSD) system.

Referring to fig. 30, an SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 transmits and receives the signal SIG to and from the host 1100 through the signal connector, and receives the power PWR through the power connector. SSD 1200 may include SSD controller 1210, auxiliary power supply 1220, and memory devices 1230, 1240, and 1250. Memory devices 1230, 1240, and 1250 can be implemented using the embodiments described above with reference to fig. 1-29. Memory devices 1230, 1240, and 1250 may be connected to SSD controller 1210 via channels Ch2, Ch2, … …, Chn.

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims (20)

1. A memory device, the memory device comprising:

a memory cell array disposed in the first semiconductor layer, the memory cell array including a plurality of word lines extending in a first direction and stacked in a second direction perpendicular to the first direction; and

a plurality of transfer transistors disposed in the first semiconductor layer, wherein a first transfer transistor of the plurality of transfer transistors is disposed between a first signal line of a plurality of signal lines and a first word line of the plurality of word lines,

wherein the plurality of signal lines are arranged at the same level as the common source line, and

wherein the memory device is a non-volatile memory device.

2. The memory device of claim 1, wherein the first pass transistor is a vertical pass transistor, and

wherein each of the plurality of pass transistors includes a vertical channel, wherein a top of the vertical channel is below the first word line.

3. The memory device of claim 2, further comprising a gate extending in a first direction between the plurality of signal lines and the plurality of word lines, wherein the first pass transistor comprises a channel extending from the first signal line through the gate in a second direction.

4. The memory device of claim 3, wherein a width of a channel between the gate and the first word line is greater than a width of a channel under the gate,

wherein the memory cell array further comprises a plurality of channel structures extending from the common source line through the ground select line in the second direction, and

wherein a first channel structure of the plurality of channel structures has a first width in a region between the ground select line and the first word line, and a channel of the first transfer transistor has a second width in a region between the gate and the first word line, the second width being greater than the first width.

5. The memory device of claim 4, wherein tops of the plurality of vertical channels are at the same level as each other, and

wherein the second width is at least twice the first width.

6. The memory device according to claim 1, wherein the plurality of transfer transistors are formed in a region where the plurality of word lines form a staircase shape.

7. The memory device according to claim 1, further comprising a second semiconductor layer, wherein the first semiconductor layer is stacked on the second semiconductor layer in the second direction, the second semiconductor layer comprises a second transistor electrically connected to the first transfer transistor, and

wherein the second transistor is included in the row decoder.

8. The memory device of claim 1, further comprising a gate connected to at least one of the plurality of pass transistors, wherein the gate is disposed at the same level as a ground select line.

9. The memory device according to claim 1, wherein the plurality of transfer transistors are connected in common to a gate line, and

wherein the plurality of transfer transistors are supplied with the same block selection signal.

10. A memory device, the memory device comprising:

a memory cell array including a plurality of word lines stacked in a vertical direction; and

a plurality of vertical transfer transistors, wherein a first vertical transfer transistor of the plurality of vertical transfer transistors includes a first vertical channel extending in a vertical direction between a first drive signal line and a first word line of the plurality of word lines, wherein the first vertical channel is disposed near an end of the first word line, and

wherein the first driving signal line and the common source line are arranged in the same layer.

11. The memory device according to claim 10, wherein a first driving signal line is provided on the base layer of the first semiconductor layer and extends horizontally, the first driving signal line is connected to a transistor included in the second semiconductor layer, and

wherein the first driving signal line is connected to the transistor in the second semiconductor layer through the contact and the metal pattern in the first semiconductor layer.

12. The memory device of claim 10, wherein the plurality of vertical pass transistors includes a second vertical pass transistor including a second vertical channel extending in a vertical direction between the second drive signal line and a second word line of the plurality of word lines, the second vertical channel disposed near an end of the second word line.

13. The memory device according to claim 12, wherein the end of the second word line is closer to a cell area of the memory cell array than the end of the first word line,

wherein the first vertical channel and the second vertical channel have the same height as each other in a vertical direction, and

wherein a top surface of the first vertical channel and a top surface of the second vertical channel are located below a bottom surface of the first word line.

14. The memory device of claim 10, wherein the first word line comprises a tungsten region and a nitride region, and

wherein the tungsten region is connected to a contact, and the contact is connected to the first word line through the tungsten region.

15. The memory device of claim 10, the memory device further comprising:

a gate electrode disposed between the first driving signal line and the first word line; and

a ground selection line disposed between the common source line and the first word line, wherein the gate and the ground selection line are disposed at the same level as each other, and

wherein the memory cell array and the plurality of transfer transistors are disposed in a first semiconductor layer, and at least a portion of the row decoder is disposed in a second semiconductor layer below the first semiconductor layer.

16. The memory device according to claim 10, wherein a first word line connected to the first drive signal line is supplied with a program voltage, and a second word line connected to the second drive signal line is supplied with a pass voltage, and

wherein the programming voltage is 10V to 25V, and the pass voltage is 5V to 15V.

17. The memory device according to claim 10, wherein a first word line connected to the first drive signal line is supplied with a read voltage, and a second word line connected to the second drive signal line is supplied with a read pass voltage, and

wherein the read voltage is-1V to 10V, and the read pass voltage is 4V to 10V.

18. The memory device according to claim 10, wherein the first word line connected to the first drive signal line is supplied with an erase voltage, and

wherein the erasing voltage is-2V to 3V.

19. A memory device, the memory device comprising:

a first semiconductor layer comprising: a memory cell array including a plurality of word lines stacked in a vertical direction; a plurality of transfer transistors, a first transfer transistor of the plurality of transfer transistors being connected to a driving signal line; and a gate electrode disposed on the same layer as the ground selection line; and

a second semiconductor layer including a first transistor connected to a contact, the contact being connected to a second bonding pad, the second bonding pad being connected to the first bonding pad,

wherein the first transfer transistor is connected to the gate, the gate is connected to the contact, the contact is connected to the first bonding pad, and

the plurality of word lines have a staircase shape in a region where the first transfer transistor is disposed.

20. The memory device of claim 19, wherein the second semiconductor layer is bonded to the first semiconductor layer, and

wherein the second semiconductor layer includes a transistor connected to the gate electrode in the first semiconductor layer.

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