EP3740967A1 - Method for contacting and packetising a semiconductor chip - Google Patents

Method for contacting and packetising a semiconductor chip

Info

Publication number
EP3740967A1
EP3740967A1 EP19712123.9A EP19712123A EP3740967A1 EP 3740967 A1 EP3740967 A1 EP 3740967A1 EP 19712123 A EP19712123 A EP 19712123A EP 3740967 A1 EP3740967 A1 EP 3740967A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor chip
contacting surface
contacting
insulating layer
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19712123.9A
Other languages
German (de)
French (fr)
Inventor
Johannes Rudolph
Fabian LORENZ
Ralf Werner
Peter Seidel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Technische Universitaet Chemnitz
Original Assignee
Technische Universitaet Chemnitz
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Technische Universitaet Chemnitz filed Critical Technische Universitaet Chemnitz
Publication of EP3740967A1 publication Critical patent/EP3740967A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82104—Forming a build-up interconnect by additive methods, e.g. direct writing using screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/828—Bonding techniques
    • H01L2224/8284—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the invention relates to a method for contacting and packaging a
  • Semiconductor chips and is used in particular for the contacting and packaging of semiconductors using the 3D multi-material printing.
  • the upper side is contacted by means of bonding wires.
  • the electrical and thermal connection is less pronounced compared to the bottom, resulting in quality losses.
  • the document WO 2009/034557 A2 discloses a method for the production of structures with integrated electrical elements such as semiconductor chips.
  • the method relates to the implementation of arbitrary structures for providing electrical connection and mechanical attachment for integrated circuits.
  • According to the document structures are using three-dimensional
  • the structure is produced in a single process step, wherein the mechanical, electrical and thermal properties in the
  • the structure may include dielectric and metallic materials.
  • the structures may be made directly in connection with the integrated circuits or separately for subsequent mounting to the integrated circuits.
  • a method for producing a functional unit and a functional unit is known.
  • the method provides that a functional unit is produced by layer-wise orders of a first and second material.
  • the first material and the second material have different properties, wherein an encapsulation of the first material and a conductor track structure of the second material are generated.
  • one or more functional units are incorporated into the
  • a laminate package consisting of a chip and a carrier in a cavity is disclosed in the publication DE 10 2016 107 031 A1.
  • a laminate package having a chip carrier of a first material and a body of a second material, wherein the first material is different from the second material.
  • the first and second materials are arranged on the chip carrier such that they form a cavity.
  • At least a part of the semiconductor chip is arranged in the cavity.
  • the laminate encapsulates at least part of the
  • Chip carrier at least part of the body and at least part of the
  • the cavity can be manufactured by means of additive processes to reduce costs.
  • the object of the invention is to develop a method for contacting and packaging a semiconductor chip, which ensures a simple structural design and a good quality of the electrical and thermal connection of the semiconductor chip.
  • the invention relates to a method for contacting a semiconductor chip of a power electronic component, wherein the power electronic component has a first lower contacting surface and a semiconductor chip positioned thereon on the lower contacting surface a ceramic insulating layer surrounding the semiconductor chip along its circumference is printed.
  • Insulating layer is formed so as to extend over the surface of the first lower contacting surface not covered by the semiconductor chip.
  • a second upper contacting surface is printed on the ceramic insulating layer and the semiconductor chip, which covers the semiconductor chip and in their
  • External dimensions corresponds to the dimensions of the first contacting surface and the insulating layer.
  • the method according to the invention comprises to achieve the best possible
  • Results preferably five process steps.
  • a first process step the production of a first, lower
  • the semiconductor chip is aligned and positioned on the first lower contacting surface by means of a "pick and place” method.
  • the third process step comprises the application of a ceramic insulation layer by means of the 3D multi-material printing process.
  • the ceramic insulation layer is applied or printed in a plane surrounding the semiconductor chip on its circumference on the first lower contacting surface.
  • the second contacting surface is printed in a fourth method step.
  • the packaging thus produced which as described above contains the semiconductor chip, is sintered in a fifth method step by means of heat treatment.
  • the first and the second contacting surface and the ceramic insulating layer are produced in a printing process by means of a 3D multi-material printer.
  • the height of the ceramic insulating layer substantially corresponds to the height of the semiconductor chip, whereby a flat surface of the
  • Top of the semiconductor chip and the ceramic insulation layer is formed as a support for the second upper contact pad
  • terminals may be generated in the form of gate contacts in the manufacture of a field effect transistor.
  • MOSFET metal oxide semiconductor field effect transistor
  • a terminal as an additional contact is isolated from the second contacting area in such a way that the terminal is surrounded on the circumference by the ceramic insulating layer such that the ceramic insulating layer is in the area of the
  • Peripheral insulation of the terminal and the additional connection can be generated in the same process step with the printing of the upper second contacting surface by means of the multi-material pressure.
  • the recess in the form of recess contains electrically conductive printed structures formed by suitable ceramic structures electrically insulated against the surrounding second contacting surface by means of the ceramic.
  • the first contacting surface and the second contacting surface are made of a conductive material, wherein the first contacting surface is made of copper in particular.
  • a housing for the semiconductor chip is produced by means of the printing process in a further method step.
  • the housing may be designed such that it has cooling functionalities that are introduced when the housing is produced.
  • a power electronic component produced by the method according to the invention has a semiconductor chip, wherein the semiconductor chip is positioned on a first lower contacting surface.
  • a ceramic insulating layer enclosing the semiconductor chip, which substantially corresponds to the height of the semiconductor chip and has a second contacting area arranged on the semiconductor chip and the ceramic insulating layer, wherein the layers can be produced within a printing process.
  • the power electronic component preferably has at least one
  • the terminal in the upper contacting surface, the terminal being insulated from the second upper contacting surface by means of a ceramic insulating layer surrounding the terminal at its periphery.
  • Insulation layer is formed in one piece.
  • Figure 1 is a schematic representation of the layered structure of the power electronic component.
  • the power electronic component H according to the method of the invention is shown in FIG.
  • the power electronic component has a first lower contacting surface 1 and a semiconductor chip 2 arranged thereon, preferably by means of a "pick and place” method.
  • the lower contacting surface 1 is made of copper in particular by means of a 3D multi-material pressure.
  • Printing method applied ceramic insulation layer 3, which surrounds the semiconductor chip 2 along its circumference and embeds in the insulating layer 3.
  • Insulation layer 3 extends on the surface of the contacting surface 1 not covered by the semiconductor chip 2.
  • the ceramic insulation layer 3 has substantially a height corresponding to the height of the semiconductor chip 2, whereby a flat surface is formed.
  • a second upper contacting surface 4 is arranged by means of the 3D multi-material printing process.
  • the second contacting surface 4 has a recess 5, which is designed in the form of an additional connection 6 or contact.
  • the recess 5 is insulated from the upper second contacting surface 4 by means of the circumferentially enclosing ceramic insulation layer 3.
  • the ceramic insulation layer 3 extends around the connection 5 in a covering manner up to the level of the upper side of the upper contacting surface 4. It is possible to provide both one and a plurality of recesses 5 in the upper contacting surface 4.
  • the recess 5 and the ceramic insulation layer 3 can in one
  • Process step with the second contact surface 4 are applied together.
  • An additional connection 6 produced in this way is important for power electronic components.
  • one or more terminals 6 can be generated in the form of gate contacts when producing a field effect transistor. LIST OF REFERENCES

Abstract

The invention relates to a method for contacting a semiconductor chip of a power-electronic component. The power-electronic component has a first lower contact face (1) and a semiconductor chip (2) positioned thereon, wherein a ceramic insulation layer (3), which extends over the first contact face not covered by the semiconductor chip and which surrounds the semiconductor along its circumference, is pressed onto the lower contact face, and a second upper contact face (4) is pressed onto the semiconductor chip.

Description

Verfahren zum Kontaktieren und Paketieren eines Halbleiterchips  Method for contacting and packaging a semiconductor chip
Die Erfindung betrifft ein Verfahren zum Kontaktieren und Paketieren eines The invention relates to a method for contacting and packaging a
Halbleiterchips und findet insbesondere für die Kontaktierung und Paketierung von Halbleitern mit Hilfe des 3D Multimaterialdrucks Anwendung. Semiconductor chips and is used in particular for the contacting and packaging of semiconductors using the 3D multi-material printing.
Gemäß dem Stand der Technik sind Verfahren zum Kontaktieren von Halbleitern bekannt, wobei die Unterseite des Halbleiters durch Auflegen eines Chips auf eine metallische Fläche und anschließendes Versintern unter zusätzlichem mechanischem Druck kontaktiert wird. Die derart geschaffene Kontaktierung bietet eine gute Qualität der thermischen und elektrischen Verbindung. According to the prior art, methods for contacting semiconductors are known, wherein the underside of the semiconductor is contacted by laying a chip on a metallic surface and then sintering under additional mechanical pressure. The contacting thus created provides a good quality of the thermal and electrical connection.
Die Oberseite wird hingegen mittels Bonddrähten kontaktiert. Die elektrische und thermische Verbindung ist jedoch im Vergleich zu der Unterseite schlechter ausgeprägt, wodurch qualitative Einbußen vorliegen.  The upper side, however, is contacted by means of bonding wires. However, the electrical and thermal connection is less pronounced compared to the bottom, resulting in quality losses.
In der Druckschrift WO 2009/034557 A2 wird ein Verfahren zur Herstellung von Strukturen mit integrierten elektrischen Elementen wie Halbleiterchips offenbart. Das Verfahren betrifft die Implementierung beliebiger Strukturen zum Bereitstellen einer elektrischen Verbindung und einer mechanischen Befestigung für integrierte Schaltungen. Gemäß der Druckschrift werden Strukturen unter Verwendung von dreidimensionalen The document WO 2009/034557 A2 discloses a method for the production of structures with integrated electrical elements such as semiconductor chips. The method relates to the implementation of arbitrary structures for providing electrical connection and mechanical attachment for integrated circuits. According to the document structures are using three-dimensional
Herstellungsprozessen hergestellt, die nur additive Schritte für alle Materialien innerhalb der Struktur verwenden. Die Struktur wird in einem einzigen Verfahrensschritt erzeugt, wobei die mechanischen, elektrischen und thermischen Eigenschaften in dem Manufactured manufacturing processes that use only additive steps for all materials within the structure. The structure is produced in a single process step, wherein the mechanical, electrical and thermal properties in the
Verfahrensschritt eingebracht werden, wie sie für das Design erforderlich sind. Die Struktur kann dielektrische und metallische Materialien aufweisen. Die Strukturen können direkt in Verbindung mit den integrierten Schaltungen oder getrennt für die nachfolgende Montage an die integrierten Schaltungen hergestellt werden. Process step are introduced, as required for the design. The structure may include dielectric and metallic materials. The structures may be made directly in connection with the integrated circuits or separately for subsequent mounting to the integrated circuits.
Aus der Druckschrift DE 10 2006 008 332 A1 ist ein Verfahren zur Herstellung einer funktionellen Baueinheit sowie eine funktionelle Baueinheit bekannt. Das Verfahren sieht vor, dass durch schichtweises Aufträgen von einem ersten und zweiten Material eine funktionelle Baueinheit hergestellt wird. Das erste Material und das zweite Material weisen unterschiedliche Eigenschaften auf, wobei aus dem ersten Material eine Verkapselung und aus dem zweiten Material eine Leiterbahnstruktur erzeugt werden. Während des Auftragens der Materialien werden eine oder mehrere funktionelle Einheiten in die From the document DE 10 2006 008 332 A1 a method for producing a functional unit and a functional unit is known. The method provides that a functional unit is produced by layer-wise orders of a first and second material. The first material and the second material have different properties, wherein an encapsulation of the first material and a conductor track structure of the second material are generated. During the application of the materials, one or more functional units are incorporated into the
Schichtstruktur eingebettet und mit der Leiterbahnstruktur kontaktiert. Eine Laminatpackung bestehend aus einem Chip und einem Träger in einer Kavität wird in der Druckschrift DE 10 2016 107 031 A1 offenbart. Gemäß dem Ausführungsbeispiel wird eine Laminatpackung bereitgestellt, die einen Chipträger aus einem ersten Material und einen Körper aus einem zweiten Material aufweist, wobei sich das erste Material von dem zweiten Material unterscheidet. Das erste und zweite Material sind derart auf dem Chipträger angeordnet, dass sie eine Kavität bilden. In der Kavität ist zumindest ein Teil des Halbleiterchips angeordnet. Das Laminat kapselt mindestens einen Teil des Embedded layer structure and contacted with the conductor track structure. A laminate package consisting of a chip and a carrier in a cavity is disclosed in the publication DE 10 2016 107 031 A1. According to the embodiment, there is provided a laminate package having a chip carrier of a first material and a body of a second material, wherein the first material is different from the second material. The first and second materials are arranged on the chip carrier such that they form a cavity. At least a part of the semiconductor chip is arranged in the cavity. The laminate encapsulates at least part of the
Chipträgers, mindestens einem Teil des Körpers und mindestens einen Teil des Chip carrier, at least part of the body and at least part of the
Halbleiterchips ein. Die Kavität kann zur Kostenreduzierung mittels additiver Verfahren hergestellt werden. Semiconductor chips on. The cavity can be manufactured by means of additive processes to reduce costs.
Aufgabe der Erfindung ist es, ein Verfahren zum Kontaktieren und Paketieren eines Halbleiterchips zu entwickeln, welches einen einfachen konstruktiven Aufbau und eine gute Qualität der elektrischen und thermischen Verbindung des Halbleiterchips gewährleistet. The object of the invention is to develop a method for contacting and packaging a semiconductor chip, which ensures a simple structural design and a good quality of the electrical and thermal connection of the semiconductor chip.
Diese Aufgabe wird mit den kennzeichnenden Merkmalen des ersten und zehnten Patentanspruchs gelöst. This object is achieved with the characterizing features of the first and tenth patent claim.
Vorteilhafte Ausgestaltungen ergeben sich aus den Unteransprüchen. Advantageous embodiments emerge from the subclaims.
Die Erfindung betrifft ein Verfahren zum Kontaktieren eines Halbleiterchips eines leistungselektronischen Bauelements, wobei das leistungselektronische Bauelement eine erste untere Kontaktierungsfläche und einen darauf positionierten Halbleiterchip aufweist auf die untere Kontaktierungsfläche eine, den Halbleiterchip entlang seines Umfangs umschließende keramische Isolationsschicht gedruckt wird. Die keramische The invention relates to a method for contacting a semiconductor chip of a power electronic component, wherein the power electronic component has a first lower contacting surface and a semiconductor chip positioned thereon on the lower contacting surface a ceramic insulating layer surrounding the semiconductor chip along its circumference is printed. The ceramic
Isolationsschicht ist derart ausgebildet, dass sie sich über die nicht von dem Halbleiterchip bedeckte Fläche der ersten unteren Kontaktierungsfläche erstreckt. In einem folgenden Schritt wird auf die keramische Isolationsschicht und den Halbleiterchip eine zweite obere Kontaktierungsfläche aufgedruckt, die den Halbleiterchip bedeckt und in ihren Insulating layer is formed so as to extend over the surface of the first lower contacting surface not covered by the semiconductor chip. In a following step, a second upper contacting surface is printed on the ceramic insulating layer and the semiconductor chip, which covers the semiconductor chip and in their
Außenabmessungen den Abmessungen der ersten Kontaktierungsfläche und der Isolationsschicht entspricht. Das erfindungsgemäße Verfahren umfasst zum Erreichen eines bestmöglichen External dimensions corresponds to the dimensions of the first contacting surface and the insulating layer. The method according to the invention comprises to achieve the best possible
Ergebnisses vorzugsweise fünf Verfahrensschritte. In einem ersten Verfahrensschritt erfolgt die Herstellung einer ersten, unteren Results preferably five process steps. In a first process step, the production of a first, lower
Kontaktierungsfläche mittels eines 3D-Multimaterialdruckverfahrens. Contact surface by means of a 3D multi-material printing process.
Folgend wird mittels einer„pick and place“ Methode der Halbleiterchip auf der ersten unteren Kontaktierungsfläche ausgerichtet und positioniert.  Subsequently, the semiconductor chip is aligned and positioned on the first lower contacting surface by means of a "pick and place" method.
Der dritte Verfahrensschritt umfasst das Aufträgen einer keramischen Isolationsschicht mittels des 3D-Multimaterialdruckverfahrens. Die keramische Isolationsschicht wird dabei in einer Ebene den Halbleiterchip an seinem Umfang umschließend auf der ersten unteren Kontaktierungsfläche aufgetragen beziehungsweise aufgedruckt.  The third process step comprises the application of a ceramic insulation layer by means of the 3D multi-material printing process. The ceramic insulation layer is applied or printed in a plane surrounding the semiconductor chip on its circumference on the first lower contacting surface.
Auf die aus der keramischen Isolationsschicht und der Oberseite des Halbleiterchips gebildete Fläche wird in einem vierten Verfahrensschritt die zweite Kontaktierungsfläche aufgedruckt.  On the surface formed from the ceramic insulation layer and the upper side of the semiconductor chip, the second contacting surface is printed in a fourth method step.
Abschließend wird die derart erzeugte Paketierung, die wie vorgenannt beschrieben, den Halbleiterchip enthält, in einem fünften Verfahrensschritt mittels Wärmebehandlung gesintert.  Finally, the packaging thus produced, which as described above contains the semiconductor chip, is sintered in a fifth method step by means of heat treatment.
In einer vorteilhaften Ausgestaltung werden die erste und die zweite Kontaktierungsfläche sowie die keramische Isolationsschicht in einem Druckprozess mittels eines 3D- Multimaterialdruckers erzeugt. Die Höhe der keramischen Isolationsschicht entspricht im Wesentlichen der Höhe des Halbleiterchips, wodurch eine ebene Fläche aus der In an advantageous embodiment, the first and the second contacting surface and the ceramic insulating layer are produced in a printing process by means of a 3D multi-material printer. The height of the ceramic insulating layer substantially corresponds to the height of the semiconductor chip, whereby a flat surface of the
Oberseite des Halbleiterchips und der keramischen Isolationsschicht als Auflage für die zweite obere Kontaktierungsfläche gebildet wird Top of the semiconductor chip and the ceramic insulation layer is formed as a support for the second upper contact pad
Vorzugsweise sind in die zweite Kontaktierungsfläche ein oder mehrere Aussparungen für zusätzliche Anschlüsse eingebracht. Dies ist beispielsweise für leistungselektronische Bauelemente von Bedeutung. So können Anschlüsse in Form von Gate-Kontakten bei Herstellung eines Feldeffekttransistors erzeugt werden. Hier seien insbesondere Metall- Oxid-Halbleiter-Feldeffekttransistor (MosFet) genannt. Preferably, one or more recesses for additional connections are introduced into the second contacting surface. This is important, for example, for power electronic components. Thus, terminals may be generated in the form of gate contacts in the manufacture of a field effect transistor. Here, in particular metal oxide semiconductor field effect transistor (MOSFET) may be mentioned.
Ein Anschluss als zusätzliche Kontaktierung wird von der zweiten Kontaktierungsfläche derart isoliert, dass der Anschluss umfangseitig von der keramischen Isolationsschicht umschlossen wird derart, dass die keramische Isolationsschicht im Bereich des A terminal as an additional contact is isolated from the second contacting area in such a way that the terminal is surrounded on the circumference by the ceramic insulating layer such that the ceramic insulating layer is in the area of the
Anschlusses bis an die Oberseite der zweiten Kontaktierungsfläche reicht. Die Connection to the top of the second contacting area is sufficient. The
umfangsseitige Isolation des Anschlusses sowie der zusätzliche Anschluss lassen sich im gleichen Verfahrensschritt mit dem Drucken der oberen zweiten Kontaktierungsfläche mittels des Multimaterialdrucks erzeugen. Der Anschluss in Form der Aussparung enthält elektrisch leitende gedruckte Strukturen die durch geeignete keramische Strukturen elektrisch gegen die sie umschließende zweite Kontaktierungsfläche mittels der Keramik isoliert sind. Peripheral insulation of the terminal and the additional connection can be generated in the same process step with the printing of the upper second contacting surface by means of the multi-material pressure. The recess in the form of recess contains electrically conductive printed structures formed by suitable ceramic structures electrically insulated against the surrounding second contacting surface by means of the ceramic.
Die erste Kontaktierungsfläche und die zweite Kontaktierungsfläche sind aus einem leitenden Material hergestellt, wobei die erste Kontaktierungsfläche insbesondere aus Kupfer hergestellt wird. The first contacting surface and the second contacting surface are made of a conductive material, wherein the first contacting surface is made of copper in particular.
In einer vorteilhaften Ausgestaltung wird in einem weiteren Verfahrensschritt ein Gehäuse für den Halbleiterchip mittels des Druckverfahrens erzeugt. Das Gehäuse kann derart ausgebildet sein, dass es Kühlfunktionalitäten aufweist, die bei Erzeugen des Gehäuses eingebracht werden. In an advantageous embodiment, a housing for the semiconductor chip is produced by means of the printing process in a further method step. The housing may be designed such that it has cooling functionalities that are introduced when the housing is produced.
Durch die gute thermische Anbindung des Halbleiterchips an die erste und zweite  Due to the good thermal connection of the semiconductor chip to the first and second
Kontaktierungsfläche lassen sich auftretende elektrische Verlustleistungen besser nach Außen abtransportieren. Der Einsatz von keramischen Isolationsmaterialien erhöht diesen Effekt deutlich, da diese im Vergleich zu Kunststoffpaketierungen über deutlich höhere Wärmeleitfähigkeiten verfügen. Contact surface can better dissipate occurring electrical power losses to the outside. The use of ceramic insulation materials significantly increases this effect, since they have significantly higher thermal conductivities compared to plastic packages.
Ein nach dem erfindungsgemäßen Verfahren hergestelltes leistungselektronisches Bauelement weist einen Halbleiterchip auf, wobei der Halbleiterchip auf einer ersten unteren Kontaktierungsfläche positioniert ist. Auf der unteren Kontaktierungsfläche ist eine den Halbleiterchip umschließende keramische Isolationsschicht angeordnet, die im Wesentlichen der Höhe des Halbleiterchips entspricht und eine auf dem Halbleiterchip und der keramischen Isolationsschicht angeordnete zweite Kontaktierungsfläche aufweist, wobei die Schichten innerhalb eines Druckverfahrens herstellbar sind. A power electronic component produced by the method according to the invention has a semiconductor chip, wherein the semiconductor chip is positioned on a first lower contacting surface. Arranged on the lower contacting surface is a ceramic insulating layer enclosing the semiconductor chip, which substantially corresponds to the height of the semiconductor chip and has a second contacting area arranged on the semiconductor chip and the ceramic insulating layer, wherein the layers can be produced within a printing process.
Das leistungselektronische Bauelement weist vorzugsweise wenigstens einen The power electronic component preferably has at least one
zusätzlichen Anschluss in der oberen Kontaktierungsfläche auf, wobei der Anschluss von der zweiten oberen Kontaktierungsfläche mittels einer den Anschluss an seinem Umfang umschließenden keramischen Isolationsschicht isoliert ist. Die keramische additional terminal in the upper contacting surface, the terminal being insulated from the second upper contacting surface by means of a ceramic insulating layer surrounding the terminal at its periphery. The ceramic
Isolationsschicht ist einteilig ausgebildet. Insulation layer is formed in one piece.
Die Erfindung wird nachfolgend an einem Ausführungsbeispiel und zugehörigen The invention is described below with reference to an embodiment and associated
Zeichnungen näher erläutert. Drawings explained in more detail.
Es zeigen: Figur 1 eine schematische Darstellung des schichtweisen Aufbaus des leistungselektronischen Bauelements. Show it: Figure 1 is a schematic representation of the layered structure of the power electronic component.
Das leistungselektronische Bauelement H nach dem erfindungsgemäßen Verfahren ist in Figur 1 dargestellt. Das leistungselektronische Bauelement weist eine erste untere Kontaktierungsfläche 1 und einen darauf, vorzugsweise mittels einer„pick and place“ Methode angeordneten Halbleiterchip 2 auf. Die untere Kontaktierungsfläche 1 ist insbesondere mittels eines 3D-Multimaterialdrucks aus Kupfer hergestellt. The power electronic component H according to the method of the invention is shown in FIG. The power electronic component has a first lower contacting surface 1 and a semiconductor chip 2 arranged thereon, preferably by means of a "pick and place" method. The lower contacting surface 1 is made of copper in particular by means of a 3D multi-material pressure.
Auf der ersten unteren Kontaktierungsfläche 1 erstreckt sich eine mittels des  On the first lower contacting surface 1 extends one by means of
Druckverfahrens aufgebrachte keramische Isolationsschicht 3, die den Halbleiterchip 2 entlang seines Umfangs umschließt und in der Isolationsschicht 3 einbettet. Die Printing method applied ceramic insulation layer 3, which surrounds the semiconductor chip 2 along its circumference and embeds in the insulating layer 3. The
Isolationsschicht 3 erstreckt sich auf der Fläche der nicht von dem Halbleiterchip 2 bedeckten Kontaktierungsfläche 1. Insulation layer 3 extends on the surface of the contacting surface 1 not covered by the semiconductor chip 2.
Die keramische Isolationsschicht 3 weist im Wesentlichen eine Höhe entsprechend der Höhe des Halbleiterchips 2 auf, wodurch eine plane Fläche entsteht. Auf die keramische Isolationsschicht 3 ist mittels des 3D-Multimaterialdruckverfahrens eine zweite obere Kontaktierungsfläche 4 angeordnet.  The ceramic insulation layer 3 has substantially a height corresponding to the height of the semiconductor chip 2, whereby a flat surface is formed. On the ceramic insulation layer 3, a second upper contacting surface 4 is arranged by means of the 3D multi-material printing process.
Gemäß der Figur 1 weist die zweite Kontaktierungsfläche 4 eine Aussparung 5 auf, die in Form eines zusätzlichen Anschlusses 6 oder Kontaktes ausgebildet ist. Die Aussparung 5 wird mittels der umfangsseitig umschließenden keramischen Isolationsschicht 3 von der oberen zweiten Kontaktierungsfläche 4 isoliert. Die keramische Isolationsschicht 3 erstreckt sich um den Anschluss 5 bereichsweise diesen ummantelnd bis auf die Höhe der Oberseite der oberen Kontaktierungsfläche 4. Es kann sowohl ein, als auch mehrere Aussparungen 5 in der oberen Kontaktierungsfläche 4 vorgesehen sein. According to FIG. 1, the second contacting surface 4 has a recess 5, which is designed in the form of an additional connection 6 or contact. The recess 5 is insulated from the upper second contacting surface 4 by means of the circumferentially enclosing ceramic insulation layer 3. The ceramic insulation layer 3 extends around the connection 5 in a covering manner up to the level of the upper side of the upper contacting surface 4. It is possible to provide both one and a plurality of recesses 5 in the upper contacting surface 4.
Die Aussparung 5 sowie die keramische Isolationsschicht 3 können in einem The recess 5 and the ceramic insulation layer 3 can in one
Verfahrensschritt mit der zweiten Kontaktierungsfläche 4 gemeinsam aufgebracht werden. Ein derart erzeugter zusätzlicher Anschluss 6 ist für leistungselektronische Bauelemente von Bedeutung. So können ein oder mehrere Anschlüsse 6 in Form von Gate- Kontakten bei Herstellung eines Feldeffekttransistors erzeugt werden. Bezuqszeichenliste Process step with the second contact surface 4 are applied together. An additional connection 6 produced in this way is important for power electronic components. Thus, one or more terminals 6 can be generated in the form of gate contacts when producing a field effect transistor. LIST OF REFERENCES
1 Erste untere Kontaktierungsfläche 1 first lower contact surface
2 Halbleiterchip  2 semiconductor chip
3 Keramische Isolationsschicht  3 Ceramic insulation layer
4 Zweite obere Kontaktierungsfläche  4 Second upper contact surface
5 Aussparung  5 recess
6 zusätzlicher Anschluss  6 additional connection
H Leistungselektronische Bauelement  H power electronic component

Claims

Patentansprüche claims
1. Verfahren zum Kontaktieren und Paketieren eines Halbleiterchips (2) eines 1. A method for contacting and packaging a semiconductor chip (2) of a
leistungselektronischen Bauelements, wobei das leistungselektronische  power electronic component, wherein the power electronic
Bauelement eine erste untere Kontaktierungsfläche (1) und einen darauf positionierten Halbleiterchip (2) aufweist, dadurch gekennzeichnet, dass auf die untere Kontaktierungsfläche (1) eine, den Halbleiterchip (2) entlang seines Umfangs umschließende und sich auf der nicht von dem Halbleiterchip (2) bedeckten ersten Kontaktierungsfläche (1) erstreckende, keramische  Device has a first lower contacting surface (1) and a semiconductor chip (2) positioned thereon, characterized in that on the lower contacting surface (1) one, the semiconductor chip (2) enclosing along its circumference and on the not of the semiconductor chip (2 ) covered first contacting surface (1) extending, ceramic
Isolationsschicht (3) gedruckt wird und dass auf die keramische Isolationsschicht (3) und den Halbleiterchip (2) eine zweite obere Kontaktierungsfläche (4) aufgedruckt wird, wobei die erste und zweite Kontaktierungsfläche (1 , 4) und die keramische Isolationsschicht (3) in einem Druckprozess mittels eines 3D- Multimaterialdruckers erzeugt werden derart,  Insulating layer (3) is printed and that on the ceramic insulating layer (3) and the semiconductor chip (2) a second upper contact surface (4) is printed, wherein the first and second contacting surface (1, 4) and the ceramic insulating layer (3) in a printing process by means of a 3D multi-material printer are generated such
dass  that
in einem ersten Verfahrensschritt die erste Kontaktierungsfläche (1) mittels des Multimaterialdruckverfahrens hergestellt wird,  in a first method step, the first contacting surface (1) is produced by means of the multi-material printing method,
in einem zweiten Verfahrensschritt der Halbleiterchip (2) auf der ersten unteren Kontaktierungsfläche (1) platziert wird,  in a second method step, the semiconductor chip (2) is placed on the first lower contacting surface (1),
in einem dritten Verfahrensschritt auf die erste Kontaktierungsfläche (1) eine den Halbleiterchip (2) an seinem Umfang umschließende keramische Isolationsschicht (3) aufgedruckt wird,  a ceramic insulating layer (3) enclosing the semiconductor chip (2) at its circumference is printed on the first contacting area (1) in a third method step,
in einem vierten Verfahrensschritt die zweite Kontaktierungsfläche (4) auf die keramische Isolationsschicht (3) und den Halbleiterchip (2) aufgedruckt wird, in einem fünften Verfahrensschritt das leistungselektronische Bauelement mittels Wärmebehandlung gesintert wird.  In a fourth method step, the second contacting surface (4) is printed on the ceramic insulation layer (3) and the semiconductor chip (2), in a fifth method step, the power electronic component is sintered by means of heat treatment.
2. Verfahren nach einem der Anspruch 1 , dadurch gekennzeichnet, dass die Höhe der keramischen Isolationsschicht (3) im Wesentlichen der Höhe des 2. The method according to any one of claim 1, characterized in that the height of the ceramic insulation layer (3) is substantially equal to the height of
Halbleiterchips (2) entspricht.  Semiconductor chips (2) corresponds.
3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass in die zweite Kontaktierungsfläche (4) eine Aussparung (5) für einen zusätzlichen Anschluss (6) eingebracht wird. 3. The method according to claim 1 or 2, characterized in that in the second contacting surface (4) has a recess (5) for an additional connection (6) is introduced.
4. Verfahren nach Anspruch 3, dadurch gekennzeichnet, dass der Anschluss (6) von der keramischen Isolationsschicht (3) randseitig umschlossen und von der zweiten Kontaktierungsfläche (4) isoliert ist. 4. The method according to claim 3, characterized in that the connection (6) of the ceramic insulating layer (3) peripherally enclosed and isolated from the second contacting surface (4).
5. Verfahren nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass die erste Kontaktierungsfläche (1) und oder zweite Kontaktierungsfläche (4) aus einem leitenden Material hergestellt wird. 5. The method according to any one of claims 1 to 4, characterized in that the first contacting surface (1) and or second contacting surface (4) is made of a conductive material.
6. Verfahren nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, dass in einem weiteren Verfahrensschritt ein Gehäuse für den Halbleiterchip (2) mittels des Druckverfahrens erzeugt wird, wobei in das Gehäuse Kühlfunktionalitäten eingebracht werden. 6. The method according to any one of claims 1 to 5, characterized in that in a further method step, a housing for the semiconductor chip (2) is produced by means of the printing process, wherein cooling functionalities are introduced into the housing.
EP19712123.9A 2018-02-23 2019-01-29 Method for contacting and packetising a semiconductor chip Pending EP3740967A1 (en)

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DE102018104144.6A DE102018104144B4 (en) 2018-02-23 2018-02-23 Process for contacting and packaging a semiconductor chip
PCT/DE2019/100092 WO2019161833A1 (en) 2018-02-23 2019-01-29 Method for contacting and packetising a semiconductor chip

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DE102006008332B4 (en) 2005-07-11 2009-06-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Process for the production of a functional structural unit and functional structural unit
WO2009034557A2 (en) 2007-09-14 2009-03-19 Nxp B.V. Method and apparatus for forming arbitrary structures for integrated circuit devices
US7727813B2 (en) 2007-11-26 2010-06-01 Infineon Technologies Ag Method for making a device including placing a semiconductor chip on a substrate
US7767495B2 (en) * 2008-08-25 2010-08-03 Infineon Technologies Ag Method for the fabrication of semiconductor devices including attaching chips to each other with a dielectric material
US8138587B2 (en) 2008-09-30 2012-03-20 Infineon Technologies Ag Device including two mounting surfaces
US20120222736A1 (en) * 2011-03-04 2012-09-06 Applied Materials, Inc. Front contact solar cell manufacture using metal paste metallization
US9129959B2 (en) * 2012-08-21 2015-09-08 Infineon Technologies Ag Method for manufacturing an electronic module and an electronic module
US9478484B2 (en) * 2012-10-19 2016-10-25 Infineon Technologies Austria Ag Semiconductor packages and methods of formation thereof
US9156680B2 (en) 2012-10-26 2015-10-13 Analog Devices, Inc. Packages and methods for packaging
DE102016107031B4 (en) 2016-04-15 2019-06-13 Infineon Technologies Ag Laminated package of chip on carrier and in cavity, arrangement comprising these and method of manufacture

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DE102018104144A1 (en) 2019-08-29
WO2019161833A1 (en) 2019-08-29
US20220181291A1 (en) 2022-06-09
US11749638B2 (en) 2023-09-05

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