EP3719851A2 - Semiconductor structure and process thereof - Google Patents
Semiconductor structure and process thereof Download PDFInfo
- Publication number
- EP3719851A2 EP3719851A2 EP20162773.4A EP20162773A EP3719851A2 EP 3719851 A2 EP3719851 A2 EP 3719851A2 EP 20162773 A EP20162773 A EP 20162773A EP 3719851 A2 EP3719851 A2 EP 3719851A2
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- Prior art keywords
- fin
- layer
- stacked
- layers
- gate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 231
- 239000000463 material Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 6
- 229910001928 zirconium oxide Inorganic materials 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 4
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- OQPDWFJSZHWILH-UHFFFAOYSA-N [Al].[Al].[Al].[Ti] Chemical compound [Al].[Al].[Al].[Ti] OQPDWFJSZHWILH-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- 229910021324 titanium aluminide Inorganic materials 0.000 description 3
- 229910015846 BaxSr1-xTiO3 Inorganic materials 0.000 description 2
- 229910020696 PbZrxTi1−xO3 Inorganic materials 0.000 description 2
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 2
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 2
- VNSWULZVUKFJHK-UHFFFAOYSA-N [Sr].[Bi] Chemical compound [Sr].[Bi] VNSWULZVUKFJHK-UHFFFAOYSA-N 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- JPNWDVUTVSTKMV-UHFFFAOYSA-N cobalt tungsten Chemical compound [Co].[W] JPNWDVUTVSTKMV-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
Definitions
- the present invention relates generally to a semiconductor structure and process thereof, and more specifically to a semiconductor structure including a stacked fin structure and process thereof.
- the multi-gate MOSFET is advantageous for the following reasons.
- manufacturing processes of multi-gate MOSFET devices can be integrated into traditional logic device processes, and thus are more compatible.
- the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect.
- DIBL drain-induced barrier lowering
- the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased.
- the present invention provides a semiconductor structure and process thereof, which forms a stacked fin structure to improve the controlling of a gate.
- the present invention provides a semiconductor structure including at least one stacked fin structure, a gate and a source/drain.
- the stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer, a second fin layer, and a fin dielectric layer sandwiched by the first fin layer and the second fin layer.
- the gate is disposed over the stacked fin structure.
- the source/drain is disposed directly on the substrate and on sidewalls of the whole stacked fin structure.
- the present invention provides a semiconductor process including the following steps .
- a stacked layer is formed on a substrate, wherein the stacked layer includes a first layer, a dielectric layer and a second layer stacked from bottom to top.
- the stacked layer is patterned to form at least one stacked fin structure on the substrate, wherein the stacked fin structure includes a first fin layer, a second fin layer, and a fin dielectric layer sandwiched by the first fin layer and the second fin layer.
- a gate is disposed over the stacked fin structure.
- the stacked fin structure beside the gate is etched to form recesses in the stacked fin structure and expose the substrate.
- a source/drain is formed in the recesses and directly on the substrate.
- the present invention provides a semiconductor structure and process thereof, which forms a stacked fin structure on a substrate, wherein the stacked fin structure includes a plurality of fin layers and a plurality of fin dielectric layers, and each of the fin layers is sandwiched by the fin dielectric layers, to electrically isolate the fin layers and the substrate from each other.
- the controlling of the gate can be improved.
- FIGs.1-7 schematically depict three-dimensional diagrams of a semiconductor process according to an embodiment of the present invention.
- a stacked layer 120' is formed on a substrate 110.
- the substrate 110 may be a semiconductor substrate such as a silicon substrate, a silicon containing substrate, a III-V group-on-silicon (such as GaN-on-silicon) substrate, a graphene-on-silicon substrate or a silicon-on-insulator (SOI) substrate.
- the substrate 110 may be a bulk substrate, and the stacked layer 120' stacked on the substrate 110 is used for forming a stacked fin structure.
- the stacked layer 120' includes a first layer 122', a dielectric layer 123', a second layer 124', a dielectric layer 125', a third layer 126' and a dielectric layer 127'.
- the dielectric layer 127', the third layer 126', the dielectric layer 125', the second layer 124', the dielectric layer 123' and the first layer 122' are stacked from bottom to top.
- the first layer 122', the second layer 124' and the third layer 126' may be silicon containing layers such as silicon layers or silicon germanium layers serving as gate channels.
- the first layer 122', the second layer 124' and the third layer 126' are electrically isolated from each other by the dielectric layer 123', the dielectric layer 125' and the dielectric layer 127'.
- Each of the dielectric layer 123', the dielectric layer 125' and the dielectric layer 127' may include a high-K dielectric layer.
- each of the dielectric layer 123', the dielectric layer 125' and the dielectric layer 127' may include a high-K dielectric layer sandwiched by buffer layers.
- the buffer layers are used for buffering the high-K dielectric layer and the silicon containing layers (meaning the first layer 122', the second layer 124', the third layer 126', or the substrate 110) .
- the dielectric layer 123' includes a high-K dielectric layer 123a' sandwiched by two buffer layers 123b'/123c'; the dielectric layer 125' includes a high-K dielectric layer 125a' sandwiched by two buffer layers 125b'/125c'; the dielectric layer 127' includes a high-K dielectric layer 127a' sandwiched by two buffer layers 127b'/127c', but it is not limited thereto.
- the buffer layers 123b'/123c'/125b'/125c'/127b'/127c' may be oxide layers, such as silicon oxide (SiO 2 ); the high-K dielectric layers 123a' /125a' /127a' may be the group selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalite (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (
- the stacked fin structure 120 is formed on a substrate 110a. Only one stacked fin structure 120 is depicted in this embodiment, but the present invention is not restricted thereto.
- the stacked layer 120' of FIG.1 is patterned to form the stacked fin structure 120 on the substrate 110a, wherein the stacked fin structure 120 may include a first fin layer 122, a fin dielectric layer 123, a second fin layer 124, a fin dielectric layer 125, a third fin layer 126 and a fin dielectric layer 127.
- the fin dielectric layer 127, the third fin layer 126, the fin dielectric layer 125, the second fin layer 124, the fin dielectric layer 123 and the first fin layer 122 are stacked from bottom to top.
- the first fin layer 122, the second fin layer 124 and the third fin layer 126 may be silicon containing layers such as silicon layers or silicon germanium layers serving as gate channels, and the first fin layer 122, the second fin layer 124, the third fin layer 126 and the substrate 110a are electrically isolated from each other by the fin dielectric layer 123, the fin dielectric layer 125 and the fin dielectric layer 127.
- Each of the fin dielectric layer 123, the fin dielectric layer 125 and the fin dielectric layer 127 may include a high-K dielectric layer. This means the fin dielectric layer 123 includes a high-K dielectric layer 123a, the fin dielectric layer 125 includes a high-K dielectric layer 125a, and the fin dielectric layer 127 includes a high-K dielectric layer 127a.
- the fin dielectric layer 123 may include the high-K dielectric layer 123a sandwiched by two buffer layers 123b/123c; the fin dielectric layer 125 may include the high-K dielectric layer 125a sandwiched by two buffer layers 125b/125c; the fin dielectric layer 127 may include the high-K dielectric layer 127a sandwiched by two buffer layers 127b/127c, but it is not limited thereto.
- the first fin layer 122 may include a silicon fin layer
- the second fin layer 124 may include a silicon germanium fin layer
- the third fin layer 126 may include a silicon fin layer; perhaps, the first fin layer 122, the second fin layer 124 and the third fin layer 126 all include silicon fin layers, depending upon practical requirements.
- a part of the substrate 110 is patterned while the stacked layer 120' of FIG.1 is patterned, to form the substrate 110a, wherein the substrate 110a may include a fin part 112 on a bulk bottom part 114.
- the stacked fin structure 120 is directly formed on the fin part 112 of the substrate 110a. Sidewalls S1 of the stacked fin structure 120 are trimmed with sidewalls S2 of the fin part 112.
- only one stacked fin structure 120 and the fin part 112 are depicted, but a plurality of stacked fin structures 120 and the fin parts 112 can be applied in the present invention.
- the fin dielectric layer 127 is sandwiched by the third fin layer 126 and the substrate 110a, the fin dielectric layer 125 is sandwiched by the third fin layer 126 and the second fin layer 124, and the fin dielectric layer 123 is sandwiched by the second fin layer 124 and the first fin layer 122, the first fin layer 122, the second fin layer 124 and the third fin layer 126 can serve as gate channels respectively. Thicknesses and materials of the first fin layer 122, the second fin layer 124 and the third fin layer 126 may be different to have different channel properties, depending upon practical requirements.
- the fin dielectric layer 127 is located at the bottom of the stacked fin structure 120 and directly contacts the substrate 110a to prevent circuit leakage flowing from the stacked fin structure 120 to the substrate 110a.
- a plurality of fin layers are sandwiched by a plurality of fin dielectric layers, to form a plurality of gate channels in one same gate transistor, thereby the controlling of the gate can being improved.
- the first fin layer, the second fin layer and the third fin layer are just terms representing each fin layers, and the structure of the present invention may be described as a first fin layer, a plurality of fin dielectric layers and a plurality of second fin layers, the first fin layer, the fin dielectric layers and the second fin layers are stacked arranged, wherein the fin dielectric layers are sandwiched by the first fin layer and each of the second fin layers to electrically isolate the first fin layer and each of the second fin layers from each other.
- the isolation structure 10 is formed on the bulk bottom part 114 beside the stacked fin structure 120 and the fin part 112.
- the isolation structure 10 may be a shallow trench isolation (STI) structure, which may be formed by a shallow trench isolation process, but it is not limited thereto.
- STI shallow trench isolation
- a top surface S3 of the isolation structure 10 is trimmed with a top surface S4 of the fin part 112, therefore the whole stacked fin structure 120 protruding from and above the isolation structure 10.
- the fin dielectric layer 127 is at the bottom of the stacked fin structure 120, thereby preventing currents in a later formed gate disposed over the stacked fin structure 120 from flowing into the substrate 110a.
- a gate 130 is formed across the stacked fin structure 120.
- the gate 130 may include a buffer layer (not shown), a gate dielectric layer 132, a gate conductive layer 134 and a cap layer 136. More precisely, a buffer layer (not shown), a dielectric layer (not shown), a gate layer (not shown) and a cap layer (not shown) may be sequentially and blanketly deposited and then patterned to form the buffer layer (not shown), the gate dielectric layer 132, the gate conductive layer 134 and the cap layer 136. By doing this, the gate 130 is disposed over the stacked fin structure 120.
- the first fin layer 122 is at the top of the stacked fin structure 120, and the gate 130 contacts a top surface T1 and two sidewalls T2 of the first fin layer 122.
- the second fin layer 124 is at the middle of the stacked fin structure 120, and the gate 130 contacts two sidewalls T3 of the second fin layer 124.
- the buffer layer (not shown) is optionally formed to buffer the gate dielectric layer 132 and the stacked fin structure 120.
- the buffer layer (not shown) may be an oxide layer, but it is not limited thereto.
- the gate dielectric layer 132 is a high-K dielectric layer, which may be a metallic containing dielectric layer such as a hafnium oxide layer or a zirconium oxide layer, but it is not limited thereto.
- the gate dielectric layer 132 may be the group selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalite (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT) and barium strontium titanate (Ba x Sr 1-x TiO 3 , BST) .
- the gate dielectric layer 132 may thus be an oxide layer, which may be replaced by a high-K dielectric layer in later processes.
- the gate conductive layer 134 may be a polysilicon sacrificial gate layer, and may be replaced by a metal gate in later processes, but it is not limited thereto.
- the cap layer 136 may be one single layer or a multilayer, which may be constituted by a nitride layer, an oxide layer or/and etc, to serve as a hard mask in etching processes.
- the gate 130 may further include a barrier layer (not shown) between the gate dielectric layer 132 and the gate conductive layer 134, and the barrier layer (not shown) may include one single layer or a multilayer composed of materials such as titanium nitride or tantalum nitride etc.
- a spacer 140 may be formed on the stacked fin structure 120 and the substrate 110a beside the gate 130. More precisely, a spacer material (not shown) may be formed blanketly to cover the stacked fin structure 120, the isolation structure 10 and the substrate 110a. Then, the spacer material (not shown) is etched back to form the spacer 140.
- the spacer 140 may include one single layer or a multilayer composed of materials such as silicon nitride or/and silicon oxide etc.
- the stacked fin structure 120 beside the gate 130 is etched to form recesses R1 in the stacked fin structure 120 and expose the substrate 110a, as shown in FIG.4 .
- a source/drain 150 is formed in the recesses R1 and directly contacts the substrate 110a.
- the source/drain 150 contacts the whole sidewalls of the stacked fin structure 120 to contact each gate channels.
- the source/drain 150 may be formed by an epitaxial process, which may be grown from the fin part 112, but it is not limited thereto.
- FIG. 8 schematically depicting a partial cross-sectional view of FIG. 7 along line BB' is also presented.
- an inter-dielectric layer 160 may blanketly cover the source/drain 150 and the isolation structure 10 beside the gate 130 and expose the gate 130.
- the gate 130 is removed to form a recess R2 and expose the stacked fin structure 120.
- the metal gate 170 is formed in the recess R2.
- the metal gate 170 may include a gate dielectric layer 172, a work function metal layer 174 and a low resistivity material 176.
- the gate dielectric layer 172, the work function metal layer 174 and the low resistivity material 176 have U-shaped cross-sectional profiles.
- the gate dielectric layer 172 may be a metallic containing dielectric layer having a high dielectric constant, which may include hafnium oxide or zirconium oxide;
- the work function metal layer 174 may be a single layer or a multilayer structure, composed of titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminide (TiAl) or aluminum titanium nitride (TiAIN);
- the low resistivity material 176 may be composed of aluminum, tungsten, titanium aluminum (TiAl) alloy, cobalt tungsten phosphide (CoWP), but it is not limited thereto.
- Barrier layers may be selectively formed between the gate dielectric layer 172, the work function metal layer 174 and the low resistivity material 176, and the barrier layers may include one single layer or a multilayer composed of materials such as titanium nitride or/and tantalum nitride etc.
- the present invention provides a semiconductor structure and process thereof, which forms a stacked fin structure on a substrate, wherein the stacked fin structure includes a plurality of fin layers and a plurality of fin dielectric layers, and each of the fin layers is sandwiched by the fin dielectric layers, to electrically isolate the fin layers and the substrate from each other.
- the controlling of the gate can be improved.
- a source/drain is directly disposed on the substrate and contact the whole sidewalls of the stacked fin structure for connecting the whole gate channels.
- One of the fin dielectric layers is at the bottom of the stacked fin structure and contacts the substrate to prevent circuit leakage in the stacked fin structure from flowing to the substrate.
- Each of the fin dielectric layers may include a high-K dielectric layer, and the high-K dielectric layer is preferably sandwiched by two buffer layers to buffer the high-K dielectric layer and the fin layers.
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Abstract
Description
- The present invention relates generally to a semiconductor structure and process thereof, and more specifically to a semiconductor structure including a stacked fin structure and process thereof.
- With increasing miniaturization of semiconductor devices, various multi-gate MOSFET devices have been developed. The multi-gate MOSFET is advantageous for the following reasons. First, manufacturing processes of multi-gate MOSFET devices can be integrated into traditional logic device processes, and thus are more compatible. In addition, since the three-dimensional structure of the multi-gate MOSFET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased.
- The present invention provides a semiconductor structure and process thereof, which forms a stacked fin structure to improve the controlling of a gate.
- The present invention provides a semiconductor structure including at least one stacked fin structure, a gate and a source/drain. The stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer, a second fin layer, and a fin dielectric layer sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and on sidewalls of the whole stacked fin structure.
- The present invention provides a semiconductor process including the following steps . A stacked layer is formed on a substrate, wherein the stacked layer includes a first layer, a dielectric layer and a second layer stacked from bottom to top. The stacked layer is patterned to form at least one stacked fin structure on the substrate, wherein the stacked fin structure includes a first fin layer, a second fin layer, and a fin dielectric layer sandwiched by the first fin layer and the second fin layer. A gate is disposed over the stacked fin structure. The stacked fin structure beside the gate is etched to form recesses in the stacked fin structure and expose the substrate. A source/drain is formed in the recesses and directly on the substrate.
- According to the above, the present invention provides a semiconductor structure and process thereof, which forms a stacked fin structure on a substrate, wherein the stacked fin structure includes a plurality of fin layers and a plurality of fin dielectric layers, and each of the fin layers is sandwiched by the fin dielectric layers, to electrically isolate the fin layers and the substrate from each other. Thus, as a gate is disposed over the stacked fin structure, the controlling of the gate can be improved.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
-
FIG.1 schematically depicts a three-dimensional diagram of a semiconductor process according to an embodiment of the present invention. -
FIG.2 schematically depicts a three-dimensional diagram of a semiconductor process according to an embodiment of the present invention. -
FIG.3 schematically depicts a three-dimensional diagram of a semiconductor process according to an embodiment of the present invention. -
FIG.4 schematically depicts a three-dimensional diagram of a semiconductor process according to an embodiment of the present invention. -
FIG.5 schematically depicts a three-dimensional diagram of a semiconductor process according to an embodiment of the present invention. -
FIG.6 schematically depicts a three-dimensional diagram of a semiconductor process according to an embodiment of the present invention. -
FIG.7 schematically depicts a three-dimensional diagram of a semiconductor process according to an embodiment of the present invention. -
FIG.8 schematically depicts a partial cross-sectional view ofFIG.7 along line BB'. -
FIGs.1-7 schematically depict three-dimensional diagrams of a semiconductor process according to an embodiment of the present invention. As shown inFIG.1 , a stacked layer 120' is formed on asubstrate 110. Thesubstrate 110 may be a semiconductor substrate such as a silicon substrate, a silicon containing substrate, a III-V group-on-silicon (such as GaN-on-silicon) substrate, a graphene-on-silicon substrate or a silicon-on-insulator (SOI) substrate. In this embodiment, thesubstrate 110 may be a bulk substrate, and the stacked layer 120' stacked on thesubstrate 110 is used for forming a stacked fin structure. In this case, the stacked layer 120' includes a first layer 122', a dielectric layer 123', a second layer 124', a dielectric layer 125', a third layer 126' and a dielectric layer 127'. The dielectric layer 127', the third layer 126', the dielectric layer 125', the second layer 124', the dielectric layer 123' and the first layer 122' are stacked from bottom to top. The first layer 122', the second layer 124' and the third layer 126' may be silicon containing layers such as silicon layers or silicon germanium layers serving as gate channels. The first layer 122', the second layer 124' and the third layer 126' are electrically isolated from each other by the dielectric layer 123', the dielectric layer 125' and the dielectric layer 127'. - Each of the dielectric layer 123', the dielectric layer 125' and the dielectric layer 127' may include a high-K dielectric layer. Preferably, each of the dielectric layer 123', the dielectric layer 125' and the dielectric layer 127' may include a high-K dielectric layer sandwiched by buffer layers. The buffer layers are used for buffering the high-K dielectric layer and the silicon containing layers (meaning the first layer 122', the second layer 124', the third layer 126', or the substrate 110) . In this case, the dielectric layer 123' includes a high-K
dielectric layer 123a' sandwiched by twobuffer layers 123b'/123c'; the dielectric layer 125' includes a high-Kdielectric layer 125a' sandwiched by twobuffer layers 125b'/125c'; the dielectric layer 127' includes a high-Kdielectric layer 127a' sandwiched by twobuffer layers 127b'/127c', but it is not limited thereto. Thebuffer layers 123b'/123c'/125b'/125c'/127b'/127c' may be oxide layers, such as silicon oxide (SiO2); the high-Kdielectric layers 123a' /125a' /127a' may be the group selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalite (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT) and barium strontium titanate (BaxSr1-xTiO3, BST), but it is not limited thereto. In this case, the high-Kdielectric layers 123a'/125a'/127a' are hafnium oxide layers. - As shown in
FIG.2 , at least one stackedfin structure 120 is formed on asubstrate 110a. Only one stackedfin structure 120 is depicted in this embodiment, but the present invention is not restricted thereto. In this embodiment, the stacked layer 120' ofFIG.1 is patterned to form thestacked fin structure 120 on thesubstrate 110a, wherein thestacked fin structure 120 may include afirst fin layer 122, a findielectric layer 123, asecond fin layer 124, a findielectric layer 125, athird fin layer 126 and a findielectric layer 127. The findielectric layer 127, thethird fin layer 126, the findielectric layer 125, thesecond fin layer 124, the findielectric layer 123 and thefirst fin layer 122 are stacked from bottom to top. Thefirst fin layer 122, thesecond fin layer 124 and thethird fin layer 126 may be silicon containing layers such as silicon layers or silicon germanium layers serving as gate channels, and thefirst fin layer 122, thesecond fin layer 124, thethird fin layer 126 and thesubstrate 110a are electrically isolated from each other by the findielectric layer 123, the findielectric layer 125 and the findielectric layer 127. - Each of the fin
dielectric layer 123, the findielectric layer 125 and the findielectric layer 127 may include a high-K dielectric layer. This means the findielectric layer 123 includes a high-Kdielectric layer 123a, the findielectric layer 125 includes a high-Kdielectric layer 125a, and the findielectric layer 127 includes a high-Kdielectric layer 127a. Moreover, the findielectric layer 123 may include the high-Kdielectric layer 123a sandwiched by twobuffer layers 123b/123c; the findielectric layer 125 may include the high-Kdielectric layer 125a sandwiched by twobuffer layers 125b/125c; the findielectric layer 127 may include the high-Kdielectric layer 127a sandwiched by twobuffer layers 127b/127c, but it is not limited thereto. Thefirst fin layer 122 may include a silicon fin layer, thesecond fin layer 124 may include a silicon germanium fin layer, and thethird fin layer 126 may include a silicon fin layer; perhaps, thefirst fin layer 122, thesecond fin layer 124 and thethird fin layer 126 all include silicon fin layers, depending upon practical requirements. - In this embodiment, a part of the
substrate 110 is patterned while the stacked layer 120' ofFIG.1 is patterned, to form thesubstrate 110a, wherein thesubstrate 110a may include afin part 112 on abulk bottom part 114. The stackedfin structure 120 is directly formed on thefin part 112 of thesubstrate 110a. Sidewalls S1 of the stackedfin structure 120 are trimmed with sidewalls S2 of thefin part 112. For clarifying the present invention, only one stackedfin structure 120 and thefin part 112 are depicted, but a plurality ofstacked fin structures 120 and thefin parts 112 can be applied in the present invention. - Since the fin
dielectric layer 127 is sandwiched by thethird fin layer 126 and thesubstrate 110a, the findielectric layer 125 is sandwiched by thethird fin layer 126 and thesecond fin layer 124, and the findielectric layer 123 is sandwiched by thesecond fin layer 124 and thefirst fin layer 122, thefirst fin layer 122, thesecond fin layer 124 and thethird fin layer 126 can serve as gate channels respectively. Thicknesses and materials of thefirst fin layer 122, thesecond fin layer 124 and thethird fin layer 126 may be different to have different channel properties, depending upon practical requirements. Preferably, thefin dielectric layer 127 is located at the bottom of the stackedfin structure 120 and directly contacts thesubstrate 110a to prevent circuit leakage flowing from the stackedfin structure 120 to thesubstrate 110a. There are three fin layers respectively sandwiched by the fin dielectric layers in this embodiment, but the number of the fin layers and the fin dielectric layers are not restricted thereto. In the present invention, a plurality of fin layers are sandwiched by a plurality of fin dielectric layers, to form a plurality of gate channels in one same gate transistor, thereby the controlling of the gate can being improved. The first fin layer, the second fin layer and the third fin layer are just terms representing each fin layers, and the structure of the present invention may be described as a first fin layer, a plurality of fin dielectric layers and a plurality of second fin layers, the first fin layer, the fin dielectric layers and the second fin layers are stacked arranged, wherein the fin dielectric layers are sandwiched by the first fin layer and each of the second fin layers to electrically isolate the first fin layer and each of the second fin layers from each other. - An
isolation structure 10 is formed on the bulkbottom part 114 beside the stackedfin structure 120 and thefin part 112. Theisolation structure 10 may be a shallow trench isolation (STI) structure, which may be formed by a shallow trench isolation process, but it is not limited thereto. In this case, a top surface S3 of theisolation structure 10 is trimmed with a top surface S4 of thefin part 112, therefore the wholestacked fin structure 120 protruding from and above theisolation structure 10. Besides, thefin dielectric layer 127 is at the bottom of the stackedfin structure 120, thereby preventing currents in a later formed gate disposed over the stackedfin structure 120 from flowing into thesubstrate 110a. - As shown in
FIG.3 , a gate 130 is formed across the stackedfin structure 120. The gate 130 may include a buffer layer (not shown), agate dielectric layer 132, a gate conductive layer 134 and acap layer 136. More precisely, a buffer layer (not shown), a dielectric layer (not shown), a gate layer (not shown) and a cap layer (not shown) may be sequentially and blanketly deposited and then patterned to form the buffer layer (not shown), thegate dielectric layer 132, the gate conductive layer 134 and thecap layer 136. By doing this, the gate 130 is disposed over the stackedfin structure 120. Thefirst fin layer 122 is at the top of the stackedfin structure 120, and the gate 130 contacts a top surface T1 and two sidewalls T2 of thefirst fin layer 122. Thesecond fin layer 124 is at the middle of the stackedfin structure 120, and the gate 130 contacts two sidewalls T3 of thesecond fin layer 124. - The buffer layer (not shown) is optionally formed to buffer the
gate dielectric layer 132 and thestacked fin structure 120. The buffer layer (not shown) may be an oxide layer, but it is not limited thereto. As a gate-last for high-K first process or a gate first process is applied, thegate dielectric layer 132 is a high-K dielectric layer, which may be a metallic containing dielectric layer such as a hafnium oxide layer or a zirconium oxide layer, but it is not limited thereto. Thegate dielectric layer 132 may be the group selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalite (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT) and barium strontium titanate (BaxSr1-xTiO3, BST) . In this case, a gate-last for high-K last process is applied, thegate dielectric layer 132 may thus be an oxide layer, which may be replaced by a high-K dielectric layer in later processes. The gate conductive layer 134 may be a polysilicon sacrificial gate layer, and may be replaced by a metal gate in later processes, but it is not limited thereto. Thecap layer 136 may be one single layer or a multilayer, which may be constituted by a nitride layer, an oxide layer or/and etc, to serve as a hard mask in etching processes. The gate 130 may further include a barrier layer (not shown) between thegate dielectric layer 132 and the gate conductive layer 134, and the barrier layer (not shown) may include one single layer or a multilayer composed of materials such as titanium nitride or tantalum nitride etc. - A
spacer 140 may be formed on the stackedfin structure 120 and thesubstrate 110a beside the gate 130. More precisely, a spacer material (not shown) may be formed blanketly to cover the stackedfin structure 120, theisolation structure 10 and thesubstrate 110a. Then, the spacer material (not shown) is etched back to form thespacer 140. Thespacer 140 may include one single layer or a multilayer composed of materials such as silicon nitride or/and silicon oxide etc. - The stacked
fin structure 120 beside the gate 130 is etched to form recesses R1 in the stackedfin structure 120 and expose thesubstrate 110a, as shown inFIG.4 . As shown inFIG.5 , a source/drain 150 is formed in the recesses R1 and directly contacts thesubstrate 110a. Preferably, the source/drain 150 contacts the whole sidewalls of the stackedfin structure 120 to contact each gate channels. The source/drain 150 may be formed by an epitaxial process, which may be grown from thefin part 112, but it is not limited thereto. - Please refer to
FIGs. 6-7 , after the source/drain 150 is formed, a metal gate replacement process is performed to replace the gate 130 by ametal gate 170. For clarifying the present invention,FIG. 8 schematically depicting a partial cross-sectional view ofFIG. 7 along line BB' is also presented. As shown inFIG.6 , aninter-dielectric layer 160 may blanketly cover the source/drain 150 and theisolation structure 10 beside the gate 130 and expose the gate 130. Then, the gate 130 is removed to form a recess R2 and expose the stackedfin structure 120. Thereafter, as shown inFIGs.7-8 , themetal gate 170 is formed in the recess R2. Themetal gate 170 may include agate dielectric layer 172, a workfunction metal layer 174 and alow resistivity material 176. Thegate dielectric layer 172, the workfunction metal layer 174 and thelow resistivity material 176 have U-shaped cross-sectional profiles. Thegate dielectric layer 172 may be a metallic containing dielectric layer having a high dielectric constant, which may include hafnium oxide or zirconium oxide; the workfunction metal layer 174 may be a single layer or a multilayer structure, composed of titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminide (TiAl) or aluminum titanium nitride (TiAIN); thelow resistivity material 176 may be composed of aluminum, tungsten, titanium aluminum (TiAl) alloy, cobalt tungsten phosphide (CoWP), but it is not limited thereto. Barrier layers may be selectively formed between thegate dielectric layer 172, the workfunction metal layer 174 and thelow resistivity material 176, and the barrier layers may include one single layer or a multilayer composed of materials such as titanium nitride or/and tantalum nitride etc. - To summarize, the present invention provides a semiconductor structure and process thereof, which forms a stacked fin structure on a substrate, wherein the stacked fin structure includes a plurality of fin layers and a plurality of fin dielectric layers, and each of the fin layers is sandwiched by the fin dielectric layers, to electrically isolate the fin layers and the substrate from each other. Thus, as a gate is disposed over the stacked fin structure, the controlling of the gate can be improved.
- Preferably, a source/drain is directly disposed on the substrate and contact the whole sidewalls of the stacked fin structure for connecting the whole gate channels. One of the fin dielectric layers is at the bottom of the stacked fin structure and contacts the substrate to prevent circuit leakage in the stacked fin structure from flowing to the substrate. Each of the fin dielectric layers may include a high-K dielectric layer, and the high-K dielectric layer is preferably sandwiched by two buffer layers to buffer the high-K dielectric layer and the fin layers.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (15)
- A semiconductor structure, comprising:at least one stacked fin structure located on a substrate, wherein the stacked fin structure comprises a first fin layer and a second fin layer, and a fin dielectric layer sandwiched by the first fin layer and the second fin layer;a gate disposed over the stacked fin structure; anda source/drain disposed directly on the substrate and on sidewalls of the whole stacked fin structure.
- The semiconductor structure according to claim 1, wherein the stacked fin structure comprises the first fin layer, the plurality of fin dielectric layers and the plurality of second fin layers, the first fin layer, the fin dielectric layers and the second fin layers are stacked arranged, wherein the fin dielectric layers are sandwiched by the first fin layer and each of the second fin layers to electrically isolate the first fin layer and each of the second fin layers from each other.
- The semiconductor structure according to claim 2, wherein one of the fin dielectric layers is at the bottom of the stacked fin structure and contacts the substrate.
- The semiconductor structure according to claim 1, 2 or 3, wherein the first fin layer is at the top of the stacked fin structure and contacts the gate with a top surface and two sidewalls, and the second fin layer is at the middle of the stacked fin structure and contacts the gate with two sidewalls.
- The semiconductor structure according to one of the preceding claims, wherein the first fin layer and the second fin layer comprise silicon fin layers.
- The semiconductor structure according to one of the preceding claims, wherein the first fin layer comprises a silicon fin layer and the second fin layer comprises a silicon germanium fin layer.
- The semiconductor structure according to one of the preceding claims, wherein the fin dielectric layer comprises a high-K dielectric layer.
- The semiconductor structure according to claim 7, wherein the high-K dielectric layer comprises a hafnium oxide layer.
- The semiconductor structure according to claim 7, wherein the fin dielectric layer comprises the high-K dielectric layer sandwiched by two buffer layers.
- The semiconductor structure according to claim 9, wherein the buffer layers comprise oxide layers.
- The semiconductor structure according to one of the preceding claims, wherein a thickness of the first fin layer is different from a thickness of the second fin.
- A semiconductor process, comprising:forming a stacked layer on a substrate, wherein the stacked layer comprises a first layer, a dielectric layer and a second layer stacked from bottom to top;patterning the stacked layer to form at least one stacked fin structure on the substrate, wherein the stacked fin structure comprises a first fin layer and a second fin layer, and a fin dielectric layer sandwiched by the first fin layer and the second fin layer;forming a gate disposed over the stacked fin structure;etching the stacked fin structure beside the gate to form recesses in the stacked fin structure and expose the substrate; andforming a source/drain in the recesses and directly on the substrate.
- The semiconductor process according to claim 12, wherein the stacked fin structure comprises the first fin layer, the plurality of fin dielectric layers and the plurality of second fin layers, the first fin layer, the fin dielectric layers and the second fin layers are stacked arranged, wherein the fin dielectric layers are sandwiched by the first fin layer and each of the second fin layers to electrically isolate the first fin layer and each of the second fin layers from each other.
- The semiconductor process according to claim 12 or 13, wherein one of the fin dielectric layers is at the bottom of the stacked fin structure and contacts the substrate.
- The semiconductor process according to claim 12, 13 or 14, wherein the first fin layer is at the top of the stacked fin structure and contacts the gate with a top surface and two sidewalls, and the second fin layer is at the middle of the stacked fin structure and contacts the gate with two sidewalls.
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US8487378B2 (en) * | 2011-01-21 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-uniform channel junction-less transistor |
US8426277B2 (en) * | 2011-09-23 | 2013-04-23 | United Microelectronics Corp. | Semiconductor process |
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US9356027B1 (en) | 2015-05-11 | 2016-05-31 | International Business Machines Corporation | Dual work function integration for stacked FinFET |
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US9728621B1 (en) * | 2016-09-28 | 2017-08-08 | International Business Machines Corporation | iFinFET |
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