CN103325683A - Fin field effect transistor and technology thereof - Google Patents

Fin field effect transistor and technology thereof Download PDF

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Publication number
CN103325683A
CN103325683A CN2012100808993A CN201210080899A CN103325683A CN 103325683 A CN103325683 A CN 103325683A CN 2012100808993 A CN2012100808993 A CN 2012100808993A CN 201210080899 A CN201210080899 A CN 201210080899A CN 103325683 A CN103325683 A CN 103325683A
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effect transistor
fin
shaped field
layer
field
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CN2012100808993A
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林建廷
江文泰
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联华电子股份有限公司
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Abstract

The invention discloses a fin field effect transistor and the technology of the fin field effect transistor. The technology of the fin field effect transistor comprises the following steps that a substrate is provided; a first fin field effect transistor and a second field effect transistor are formed on the substrate, wherein the first fin field effect transistor comprises a first metal layer, and the second fin field effect transistor comprises a second metal layer; the processing technology is conducted on the first metal layer to change the threshold voltage of the first fin field effect transistor.

Description

Fin-shaped field-effect transistor and technique thereof

Technical field

The present invention relates to a kind of fin-shaped field-effect transistor (FinFET) and technique thereof, and be particularly related to a kind of fin-shaped field-effect transistor (FinFET) and technique thereof, it changes physical characteristic or the chemical characteristic of the metal level in the field-effect transistor by carrying out treatment process.

Background technology

In the known semiconductor industry, polysilicon is widely used in semiconductor element such as metal-oxide semiconductor (MOS) (metal-oxide-semiconductor, the MOS) transistor, selects as the grid packing material of standard.Yet, along with MOS transistor size micro constantly, the tradition polysilicon gate reduces because boron penetration (boron penetration) effect causes element efficiency, and the problem such as the depletion effect that is difficult to avoid (depletion effect), so that the gate dielectric layer thickness of equivalence increases, the grid capacitance value descends, and then cause the predicaments such as decline of element drives ability.Therefore, the semiconductor industry is more attempted with new grid packing material, for example utilize work function (work function) metal to replace traditional polysilicon gate, and form metal gates, in order to the control electrode as coupling high-k (High-K) gate dielectric.

Yet along with the development of semiconductor element, the requirement of its specification and performance is also day by day harsh.Under the size restrictions of various process technology limit, the restriction of each material behavior and semiconductor element, how to promote again metal gates electrically, such as the limit voltage of metal gates etc., to reach the specification of desired semiconductor element, be a current difficult problem that faces.

Summary of the invention

The present invention proposes a kind of fin-shaped field-effect transistor (FinFET) and technique thereof, it is by carrying out treatment process, change physical characteristic or the chemical characteristic of the metal level in the field-effect transistor, with promote such as the field-effect transistors such as limit voltage of metal level electrically.

The invention provides a kind of fin-shaped field-effect transistor (FinFET) technique, comprise the steps.At first, provide substrate.Then, form the first fin-shaped field-effect transistor and the second fin-shaped field-effect transistor in substrate, wherein the first fin-shaped field-effect transistor comprises the first metal layer, and the second fin-shaped field-effect transistor comprises the second metal level.Then, carry out treatment process in the first metal layer, to change the limit voltage of the first fin-shaped field-effect transistor.

The invention provides a kind of field-effect transistor, comprise that the first fin-shaped field-effect transistor and the second fin-shaped field-effect transistor with same conductivity are positioned in the substrate, wherein the first fin-shaped field-effect transistor comprises the first metal layer, the second fin-shaped field-effect transistor comprises the second metal level, and the first metal layer and the second metal level are identical material but different thickness.

The invention provides a kind of field-effect transistor, comprise that the first fin-shaped field-effect transistor and the second fin-shaped field-effect transistor with same conductivity are positioned in the substrate, wherein the first fin-shaped field-effect transistor comprises the first metal layer, the second fin-shaped field-effect transistor comprises the second metal level, and the first metal layer and the second metal level are different materials.

Based on above-mentioned, the invention provides a kind of fin-shaped field-effect transistor and technique thereof, it carries out at least the one for the treatment of process in the fin-shaped field-effect transistor more than two or two, with physical characteristic or the chemical characteristic of the metal level in each fin-shaped field-effect transistor of indivedual changes, and then the whole electrical parameters such as limit voltage of change fin-shaped field-effect transistor.

Description of drawings

Fig. 1-2 illustrates the stereogram of the fin-shaped field-effect transistor technique of the embodiment of the invention.

Fig. 3-10 illustrates the generalized section of the fin-shaped field-effect transistor technique of looking along the AA ' hatching of Fig. 2 and BB ' hatching.

Description of reference numerals

110: substrate 112: insulation system

120,124: the first fin structures of the 120 ': the first fin-shaped field-effect transistor

130,134: the second fin structures of the 130 ': the second fin-shaped field-effect transistor

142: dielectric layer 144: electrode layer

146: cap rock 148: clearance wall

149: source/drain region 150: interlayer dielectric layer

162: resilient coating 164: dielectric layer

172: 174: the first work function layers of end barrier layer

176: the second work function layers 178: top barrier layer

180: low resistivity material C, D: zone

P: mask layer P1, P2, P3: treatment process

R: groove

Embodiment

Fig. 1-2 illustrates the stereogram of the fin-shaped field-effect transistor technique of the embodiment of the invention.As shown in Figure 1, at first, provide substrate 110.Then, form the first fin-shaped field-effect transistor 120 ' and the second fin-shaped field-effect transistor 130 ' in substrate 110.

Specifically, the method that forms the first fin-shaped field-effect transistor 120 ' and the second fin-shaped field-effect transistor 130 ' can comprise: block ground (not illustrating) is provided, form hard mask layer (not illustrating) thereon, and with its patterning with the second fin structure 134 of defining in the block ground under it the first fin structure 124 of wanting corresponding the first fin-shaped field-effect transistor 120 ' that forms and the second fin-shaped field-effect transistor 130 ' in the position of substrate 110.Then, carry out etch process, in block ground (not illustrating), form simultaneously the first fin structure 124 and the second fin structure 134 in substrate 110.So, finish the first fin structure 124 and the second making of fin structure 134 in substrate 110.

Afterwards, between the first fin structure 124 and the second fin structure 134, form insulation system 112 in substrate 110 again, wherein insulation system 112 can be shallow groove insulation configuration, but the present invention is not as limit.In an embodiment, namely remove hard mask layer (not illustrating) after forming the first fin structure 124 and the second fin structure 134, can in subsequent technique, form three gate field effect transistors (tri-gate MOSFET).Thus, owing to having three direct contact surfaces (comprising that two contacts the side and contact end face) between the dielectric layer of the first fin structure 124 and the second fin structure 134 and follow-up formation, so being known as three gate field effect transistors (tri-gate MOSFET).Compared to the flat field effect transistor, three gate field effect transistors can be by the raceway groove that above-mentioned three direct contact surfaces are circulated as charge carrier, and under same grid length, have wider carrier channels width, so that the drain drives electric current that under identical driving voltage, can obtain to double.And in another embodiment, also can keep hard mask layer (not illustrating), have the multiple-grid utmost point field-effect transistor (multi-gate MOSFET) of fin structure and in subsequent technique, form another.Owing to having kept hard mask layer (not illustrating), the first fin structure 124 and the second fin structure 134 will only have two to contact the side between the dielectric layer that form with follow-up.

In addition, as previously mentioned, the present invention also can be applicable to the semiconductor base of other kinds, for example in another exemplifying embodiment, silicon-coated insulated substrate (not illustrating) is provided, and cover the monocrystalline silicon layer on the dielectric base (not illustrating) and stop at oxide layer with the method etching silicon of etching and photoetching, can finish fin structure in silicon-coated insulated suprabasil making.

In addition, be the clear announcement the present invention of energy, the present embodiment only illustrates the first fin structure 124 and the second fin structure 134, but in the first fin-shaped field-effect transistor 120 ' and the second fin-shaped field-effect transistor 130 ', and the applicable fin structure of the present invention also can be one or above two.

Then, after forming the first fin structure 124 and the second fin structure 134, sequentially form dielectric layer (not illustrating), electrode layer (not illustrating) and cap rock (not illustrating) and be located on the first fin structure 124 and the second fin structure 134, again three's patterning is formed dielectric layer 142, electrode layer 144 and cap rock 146 afterwards.Then, form clearance wall 148 in the side of dielectric layer 142, electrode layer 144 and cap rock 146.Dielectric layer 142 can comprise oxide layer; Electrode layer 144 can be polysilicon layer; 146 on cap rock can be nitration case, but the present invention is not as limit.Then, utilize the techniques such as angled ion injection to form respectively source/drain region 149 in the first fin structure 124 and second fin structure 134 of each clearance wall 148 side.So, finish the making of the first fin-shaped field-effect transistor 120 ' and the second fin-shaped field-effect transistor 130 '.Certain the first fin-shaped field-effect transistor 120 ' and the second fin-shaped field-effect transistor have polysilicon electrode 130 ' this moment, and so it will be replaced into metal electrode in subsequent technique.In addition, the present invention also can be integrated in preferential (gate-first) technique of grid, and directly selects suitable metal material layer and polysilicon layer to come together to form electrode layer 144.

As shown in Figure 2, cover interlayer dielectric layer (not illustrating) on substrate 110, the first fin structure 124, the second fin structure 134, clearance wall 148 and cap rock 146, again its planarization is formed interlayer dielectric layer 150.Wherein, the process of planarization can comprise the techniques such as chemico-mechanical polishing or etching, and removes in the lump cap rock 146, exposes electrode layer 144.Afterwards, remove electrode layer 144 and form recess R.In follow-up technique, can insert in the recess R of each metal material on the first fin structure 124 and the second fin structure 134, to form respectively the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130, the two can comprise similar and different metal level.For knowing the structure that discloses the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130, below in Fig. 3-10, illustrate the first fin-shaped field-effect transistor 120 of looking along AA ' hatching and the BB ' hatching of Fig. 2 and the generalized section of the second fin-shaped field-effect transistor 130.

The generalized section of looking along AA ' hatching and BB ' hatching for Fig. 2 as shown in Figure 3.Clearance wall 148 and interlayer dielectric layer 150 are located at respectively on the first fin structure 124 and the second fin structure 134.Source/drain region 149 is arranged in the first fin structure 124 and second fin structure 134 of clearance wall 148 sides.Clearance wall 148 exposes the first fin structure 124 and second fin structure 134 of part around recess R.Specifically, shown in the AA ' hatching of Fig. 2, can form the first fin-shaped field-effect transistor 120 on the first fin structure 124, in Fig. 3, form the zone of the first fin-shaped field-effect transistor 120 with the corresponding wish in C zone; And along shown in Fig. 2 BB ' hatching, can form the second fin-shaped field-effect transistor 130 on the second fin structure 134, then form the zone of the second fin-shaped field-effect transistor 130 with the corresponding wish in D zone.

As shown in Figure 4, on the first fin structure 124 and the second fin structure 134, sequentially form resilient coating 162 and dielectric layer 164 simultaneously.Resilient coating 162 is oxide layer for example, and dielectric layer 164 is generally dielectric layer with high dielectric constant.Dielectric layer with high dielectric constant optional autoxidation hafnium (hafnium oxide, HfO 2), hafnium silicate oxygen compound (hafnium silicon oxide, HfSiO 4), hafnium silicate oxynitrides (hafnium silicon oxynitride, HfSiON), aluminium oxide (aluminum oxide, Al 2O 3), lanthana (lanthanum oxide, La 2O 3), tantalum oxide (tantalum oxide, Ta 2O 5), yittrium oxide (yttriumoxide, Y 2O 3), zirconia (zirconium oxide, ZrO 2), strontium titanates (strontium titanate oxide, SrTiO 3), zirconium silicate oxygen compound (zirconium silicon oxide, ZrSiO 4), zirconic acid hafnium (hafniumzirconium oxide, HfZrO 4), strontium bismuth tantalum pentoxide (strontium bismuth tantalate, SrBi 2Ta 2O 9, SBT), lead zirconate titanate (lead zirconate titanate, PbZr xTi 1-xO 3, PZT) with barium strontium (barium strontium titanate, Ba xSr 1-xTiO 3, the group that BST) forms.

As shown in Figure 5, form simultaneously end barrier layer 172 on dielectric layer 164, wherein end barrier layer 172 can for example be titanium nitride layer, but the present invention is not as limit.Then, in the present embodiment, optionally carry out treatment process P1 in the end in D zone barrier layer 172, with the physical property of the end barrier layer 172 that changes the D zone or chemical property etc., with the work function of formed transistorized gate electrode in the change D zone, and then change formed transistorized limit voltage in the D zone.Certainly, in another embodiment, also can only carry out treatment process P1 in the end in C zone barrier layer 172, to change formed transistorized limit voltage in the C zone.Perhaps, carry out respectively different treatment process in the end barrier layer 172 in the end in C zone barrier layer 172 and D zone, to adjust respectively in the C zone formed transistorized limit voltage in formed transistorized limit voltage and the D zone.As shown in Figure 5, only treatment process P1 is illustrated in the D zone, only acts on the end barrier layer 172 in D zone for representing this treatment process P1.Yet, in practical operation, can be for example hide the C zone and expose the D zone with the mask (not illustrating) of patterning, and then carry out treatment process P1 comprehensively, only so can reach the purpose to end barrier layer 172 effects in D zone, anti-, as the same to the processing in C zone, do not add to give unnecessary details at this.

After formation end barrier layer 172 is on dielectric layer 164, can optionally form again etching stopping layer (not illustrating) on end barrier layer 172, wherein etching stopping layer (not illustrating) can comprise tantalum nitride layer, but the present invention is not as limit.

It should be noted that treatment process P1 can comprise etch process, doping process, oxidation technology, nitriding process or flaorination process etc., but the present invention is not as limit.The physical property and/or the chemical property that act as change end barrier layer 172 for the treatment of process P1, wherein physical property can comprise thickness, hardness, density or the reflectivity etc. of end barrier layer 172, and chemical property can comprise combination, reactivity or the rate of etch etc. of end barrier layer 172.Thus, the present invention can change physical property or the chemical property of end barrier layer 172 by carrying out at least one treatment process, and then adjusts the electrical parameter such as formed transistorized limit voltage, with the demand of equivalence element.In addition, treatment process P1 of the present invention can carry out after forming end barrier layer 172, perhaps can carry out afterwards in forming etching stopping layer (not illustrating), also or can all carry out afterwards respectively at forming the two.Certainly, the practice of the present invention also can be applicable in other metal levels of follow-up formation.

As shown in Figure 6, form the first work function layer 174 on end barrier layer 172, wherein the first work function layer 174 comprises titanium nitride layer or aluminium titanium layer, but the present invention electrically decides on transistorized not as limit.Afterwards, optionally carry out treatment process P2 in the first work function layer 174 in D zone, with the work function of formed transistorized gate electrode in the change D zone, and then change formed transistorized limit voltage in the D zone.Similar ground as shown in Figure 6, only is illustrated in treatment process P2 in the D zone, only acts on the first work function layer 174 in D zone for representing this treatment process P2.Yet, in practical operation, can be for example hide the C zone and expose the D zone with the mask (not illustrating) of patterning, and then carry out treatment process P2 comprehensively, only so can reach the purpose to the first work function layer 174 effect in D zone.Anti-, as the same to the processing in C zone, also do not add to give unnecessary details at this.

Similarly, treatment process P2 can comprise etch process, doping process, oxidation technology, nitriding process or flaorination process, but the present invention is not as limit.The effect for the treatment of process P2 can change physical property and/or the chemical property of the first work function layer 174, wherein physical property can comprise thickness, hardness, density or the reflectivity etc. of the first work function layer 174, and chemical property can comprise combination, reactivity or the rate of etch etc. of the first work function layer 174.Thus, the present invention can change physical property or the chemical property of the first work function layer 174 by carrying out at least treatment process, and then adjusts the electrical parameters such as formed transistorized limit voltage, with the demand of equivalence element.

In addition, in another exemplifying embodiment of the present invention, the metal level of work function layer of the first fin-shaped field-effect transistor and the second fin-shaped field-effect transistor etc. can also be different materials or stacked structure layer, such as Fig. 7-8.As shown in Figure 7, coverage mask layer P is in the D zone, to remove the first work function layer 174 in C zone.As shown in Figure 8, form the second work function layer 176 on the end in C zone barrier layer 172.In the present embodiment, the second work function layer 176 comprises titanium nitride layer or aluminium titanium layer, but the present invention electrically decides on transistorized not as limit.Then, optionally carry out treatment process P3 on the second work function layer 176.Because mask layer P has hidden the D zone, therefore treatment process P3 only acts on the second work function layer 176.Treatment process P3 and treatment process P1 and P2 are similar, therefore repeat no more.

Perhaps, after removing the first work function layer 174 in C zone, remove mask layer P as shown in Figure 7, form simultaneously again the second work function layer 176 on the end in the C zone barrier layer 172 and on the first work function layer 174 in D zone.Then, optionally carry out treatment process P3 on the second work function layer 176 in C zone and/or D zone, with the work function of formed transistorized gate electrode in change C zone and/or the D zone, and then change formed transistorized limit voltage in C zone and/or the D zone.Treatment process P3 and treatment process P1 and P2 are similar, therefore repeat no more.

As shown in Figure 9, form simultaneously top barrier layer 178 on the first work function floor 174 in the second work function floor 176 in C district and D district.Top barrier layer 178 is such as being titanium nitride layer etc.As shown in figure 10, form low resistivity material 180 on top barrier layer 178.Low resistivity material 180 can be such as being comprised of materials such as aluminium or copper.After forming top barrier layer 178, perhaps after forming low resistivity material 180, all optionally carry out treatment process (as treatment process P1, P2 and P3), to adjust C district or the top barrier layer 178 in D district or physical property and/or the chemical property of low resistivity material 180.At last, each metal level of planarization is to exposing interlayer dielectric layer again, and carries out various follow-up transistor technologies.

In general, the first fin-shaped field-effect transistor 120 can comprise the first metal layer, and it comprises the stacking metal levels such as at least one barrier layer (such as end barrier layer 172 and top barrier layer 178), the first work function layer 174 and low resistivity material 180; The second fin-shaped field-effect transistor 130 can comprise the second metal level, and it comprises the stacking metal levels such as at least one barrier layer (such as end barrier layer 172 and top barrier layer 178), the second work function layer 176 and low resistivity material 180.The present invention is then by carrying out at least one treatment process, with the one deck at least in the independent change the first metal layer or change separately physical property and/or the chemical property of the one deck at least in the second metal level, to reach the overall electrical purpose of modulation the first fin-shaped field-effect transistor 120 or the second fin-shaped field-effect transistor 130.For example, reach the limit voltage of modulation the first fin-shaped field-effect transistor 120 or the second fin-shaped field-effect transistor 130.Particularly, treatment process can comprise etch process, doping process, oxidation technology, nitriding process or flaorination process etc., and the material character that it can be adjusted can be such as being work function value, volume, grid leakage current, equivalent current density etc.

It should be noted that in the present invention, the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 all have same conductivity.Particularly, the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 can be all the N-type transistor and maybe can be all the P transistor npn npn.In other words, by adopting treatment process of the present invention, can change the electrical parameters such as limit voltage of identical electrical fin-shaped field-effect transistor 120.So, can reach the identical electrical transistorized function of indivedual fine settings, to meet the demand of each element.

For example, paint with Figure 10, the present invention can form a kind of field-effect transistor, and it can comprise that the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 with same conductivity are positioned in the substrate 110.For example the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 are all the N-type transistor.Perhaps for example, the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 are all the P transistor npn npn.The first fin-shaped field-effect transistor 120 comprises the first metal layer, and it can comprise at least one barrier layer (for example end barrier layer 172 and top barrier layer 178), the first work function layer 174 and low resistivity material 180; The second fin-shaped field-effect transistor 130 can comprise the second metal level, and it comprises at least one barrier layer (for example end barrier layer 172 and top barrier layer 178), the second work function layer 176 and low resistivity material 180.

Under exemplifying embodiment, can for example carry out etch process in one deck at least of the first metal layer or the second metal level changing its thickness, so that the first metal layer and the second metal level are identical material but different thickness.Perhaps, under another exemplifying embodiment, can for example carry out modified technique in one deck at least of the first metal layer or the second metal level, to change its chemical property, so that the first metal layer and the second metal level have different materials.

In addition, among other embodiment, the present invention also can be applicable to have the fin-shaped field-effect transistor of different conductivity types.For example, the first fin-shaped field-effect transistor 120 can be the P transistor npn npn, and the second fin-shaped field-effect transistor 130 is the N-type transistor.So, the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 can adopt the first work function layer 174 to be the aluminium titanium layer for titanium nitride layer the second work function layer 176, have different electrical the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistors 130 with coupling, but the present invention is not as limit.

In sum, the invention provides a kind of fin-shaped field-effect transistor and technique thereof, it carries out at least the one for the treatment of process in the fin-shaped field-effect transistor more than two or two, with physical characteristic and/or the chemical characteristic of the metal level in each fin-shaped field-effect transistor of indivedual changes, and then the whole electrical parameter of change fin-shaped field-effect transistor.Such as the limit voltage of fin-shaped field-effect transistor etc. electrically, to reach the demand of element.Particularly, treatment process can comprise etch process, doping process, oxidation technology, nitriding process or flaorination process etc.The physical characteristic of the metal level that treatment process can change can for example be thickness, hardness, density or the reflectivity of metal level, and the chemical characteristic of metal level can be such as combination, reactivity or the rate of etch etc. that are metal level.

The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.

Claims (21)

1. fin-shaped field-effect transistor technique comprises:
Substrate is provided;
Form the first fin-shaped field-effect transistor and the second fin-shaped field-effect transistor in this substrate, wherein this first fin-shaped field-effect transistor comprises the first metal layer, and this second fin-shaped field-effect transistor comprises the second metal level; And
Carry out treatment process in this first metal layer, to change the limit voltage of this first fin-shaped field-effect transistor.
2. fin-shaped field-effect transistor technique as claimed in claim 1, wherein this first fin-shaped field-effect transistor and this second fin-shaped field-effect transistor have same conductivity.
3. fin-shaped field-effect transistor technique as claimed in claim 2, wherein this first fin-shaped field-effect transistor and this second fin-shaped field-effect transistor are all the N-type transistor or are all the P transistor npn npn.
4. fin-shaped field-effect transistor technique as claimed in claim 1, wherein this treatment process comprises etch process, doping process, oxidation technology, nitriding process or flaorination process.
5. fin-shaped field-effect transistor technique as claimed in claim 1 is wherein carried out this treatment process and is comprised the physical property that changes this first metal layer in this first metal layer.
6. fin-shaped field-effect transistor technique as claimed in claim 5, wherein this physical property comprises thickness, hardness, density or the reflectivity of this first metal layer.
7. fin-shaped field-effect transistor technique as claimed in claim 1 is wherein carried out this treatment process and is comprised the chemical property that changes this first metal layer in this first metal layer.
8. fin-shaped field-effect transistor technique as claimed in claim 7, wherein this chemical property comprises combination, reactivity or the rate of etch of this first metal layer.
9. fin-shaped field-effect transistor technique as claimed in claim 1, wherein this first metal layer and this second metal level include barrier layer, workfunction layers, low resistivity material or three's combination.
10. fin-shaped field-effect transistor technique as claimed in claim 1 wherein forms this first fin-shaped field-effect transistor and this second fin-shaped field-effect transistor in this suprabasil step, comprising:
Form the first fin structure and the second fin structure in this substrate;
Form respectively dielectric layer on this first fin structure and this second fin structure;
Form respectively end barrier layer on each dielectric layer;
Form the first work function layer on this end barrier layer on this first fin structure;
Form the second work function layer on this end barrier layer on this second fin structure;
Form respectively the top barrier layer on this first work function layer and this second work function layer; And
Form respectively low resistivity material on each top barrier layer, wherein this first metal layer comprises this end barrier layer, this first work function layer, this top barrier layer and this low resistivity material that is positioned on this first fin structure, and this second metal level comprises this end barrier layer, this second work function layer, this top barrier layer and this low resistivity material that is positioned on this second fin structure.
11. fin-shaped field-effect transistor technique as claimed in claim 10 is wherein carried out this treatment process and is included in and carries out this treatment process after forming this end barrier layer, this first work function layer, this second work function layer, this top barrier layer or this low resistivity material.
12. a field-effect transistor comprises:
The first fin-shaped field-effect transistor and the second fin-shaped field-effect transistor with same conductivity are positioned in the substrate, wherein this first fin-shaped field-effect transistor comprises the first metal layer, this second fin-shaped field-effect transistor comprises the second metal level, and this first metal layer and this second metal level are identical material but different thickness.
13. field-effect transistor as claimed in claim 12, wherein this first metal layer and this second metal level include stacking metal level.
14. field-effect transistor as claimed in claim 13, wherein at least one of each stacking metal level of each stacking metal level of this first metal layer and this second metal level has different thickness.
15. field-effect transistor as claimed in claim 12, wherein this first metal layer and this second metal level include barrier layer, workfunction layers, low resistivity material or three's combination.
16. field-effect transistor as claimed in claim 12, wherein this first fin-shaped field-effect transistor and this second fin-shaped field-effect transistor have different limit voltages.
17. a field-effect transistor comprises:
The first fin-shaped field-effect transistor and the second fin-shaped field-effect transistor with same conductivity are positioned in the substrate, wherein this first fin-shaped field-effect transistor comprises the first metal layer, this second fin-shaped field-effect transistor comprises the second metal level, and this first metal layer and this second metal level are different materials.
18. field-effect transistor as claimed in claim 17, wherein this first metal layer and this second metal level all comprise stacking metal level in addition.
19. field-effect transistor as claimed in claim 18, wherein at least one of each stacking metal level of each stacking metal level of this first metal layer and this second metal level has different materials.
20. field-effect transistor as claimed in claim 17, wherein this first metal layer and this second metal level include barrier layer, workfunction layers, low resistivity material or three's combination.
21. field-effect transistor as claimed in claim 17, wherein this first fin-shaped field-effect transistor and this second fin-shaped field-effect transistor have different limit voltages.
CN2012100808993A 2012-03-23 2012-03-23 Fin field effect transistor and technology thereof CN103325683A (en)

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* Cited by examiner, † Cited by third party
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CN105723517A (en) * 2013-12-16 2016-06-29 英特尔公司 Multi-threshold voltage devices and associated techniques and configurations
US10573747B2 (en) 2013-12-16 2020-02-25 Intel Corporation Multi-threshold voltage devices and associated techniques and configurations
CN104867824A (en) * 2014-02-25 2015-08-26 格罗方德半导体公司 Integrated Circuits With Varying Gate Structures And Fabrication Methods

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Application publication date: 20130925