TWI573270B - Multigate field effect transistor and process thereof - Google Patents

Description

Multi-gate field effect transistor and its process

The present invention relates to a multi-gate field effect transistor and a process thereof, and more particularly to a multi-gate field effect transistor for forming a void in a dielectric layer between fin structures and a process therefor.

As the size of semiconductor components shrinks, maintaining the performance of small-sized semiconductor components is currently the main goal of the industry. In order to improve the performance of semiconductor components, various multi-gate MOSFETs have been developed. Multi-gate field effect transistor components include the following advantages. First, the process of the multi-gate field-effect transistor component can be integrated with the conventional logic component process, so it has considerable process compatibility. Secondly, since the three-dimensional structure increases the contact area between the gate and the substrate, the gate can be increased. Controlling the charge of the channel region, thereby reducing the Drain Induced Barrier Lowering (DIBL) effect and the short channel effect caused by the small-sized components; in addition, since the same length of the gate has The larger the channel width, the more the current between the source and the drain can be increased.

In detail, the multi-gate field effect transistor component has a fin structure on the substrate, and the gate structure and the source/drain electrodes are disposed on the fin structures to form a multi-gate channel. Gate field effect transistor. However, as the size of the multi-gate field effect transistor shrinks, a large parasitic capacitance is easily formed between the fin structures to reduce the multi-gate. Electrical performance of field effect transistors.

The invention provides a multi-gate field effect transistor and a process thereof, which form a pore in a dielectric layer between the fin structures, and reduce the parasitic capacitance of the multi-gate field effect transistor to solve the above problem.

The invention provides a multi-gate field effect transistor comprising a two fin structure and a dielectric layer. The second fin structure is located on a substrate. The dielectric layer covers the substrate and the second fin structure, and at least two pores are located in the dielectric layer between the two fin structures.

The invention provides a multi-gate field effect transistor process comprising the following steps. First, a two fin structure is formed on a substrate. Next, a dielectric layer is formed to cover the substrate and the second fin structure, wherein at least two of the pores are formed in the dielectric layer between the second fin structures.

Based on the above, the present invention provides a multi-gate field effect transistor and a process thereof, which are formed in a dielectric layer between the fin structures, and reduce the multi-gate field effect transistor, especially between the fin structures. Parasitic capacitance. Moreover, the present invention directly forms a dielectric layer between the fin structures, which can reduce the process cost more than the process of completely filling the dielectric layer.

1-7 are schematic cross-sectional views showing a process of a multi-gate field effect transistor according to a first embodiment of the present invention. First, a plurality of fin structures are formed on a substrate. As shown in FIG. 1, a second fin structure 112 is formed on a substrate 110. The substrate 110 is, for example, a substrate, a germanium-containing substrate, a tri-five-layer overlying substrate (eg, GaN-on-silicon), a graphene-on-silicon or a silicon-on-insulator (silicon- On-insulator, SOI) A semiconductor substrate such as a substrate. In detail, the method of forming the second fin structure 112 on the substrate 110 may include the following steps. First, a piece of substrate (not shown) is provided, a hard mask layer (not shown) is formed thereon, and patterned to form a patterned hard mask layer P to define the underlying layer. The position of the fin structure 112 to be formed correspondingly in the bulk substrate. Next, an etching process is performed to form the fin structure 112 in a bulk substrate (not shown). Thus, the fabrication of the fin structure 112 on the substrate 110 is completed.

As shown in FIG. 2, an insulating structure 10 is formed on the substrate 110 between the two fin structures 112. The insulating structure 10 is, for example, a shallow trench isolation (STI) structure, which is formed, for example, by a shallow trench isolation process. In this embodiment, an insulating layer (not shown) is integrally formed; then, a polishing process such as a chemical mechanical polishing process is performed, and the patterned hard mask layer P is used as a stop layer to polish the insulating layer ( It is not shown) until the patterned hard mask layer P is exposed, but the invention is not limited thereto.

Next, the patterned hard mask layer P is removed, and a three-gate tri-gate MOSFET is formed in a subsequent process. As a result, there are three direct contact faces (including two contact sides and one contact top) between the fin structure 112 and the subsequently formed dielectric layer. It is called a three-gate tri-gate MOSFET. Compared with the planar field effect transistor, the three-gate field effect transistor can have a wider carrier channel width under the same gate length by using the above three direct contact surfaces as a channel through which the carrier flows. Double the drain drive current at the same drive voltage. In other embodiments, a hard mask layer (not shown) may be left, and another multi-gate MOSFET-fin field effect having a fin structure is formed in a subsequent process. Fin field effect transistor (Fin FET). In a fin field effect transistor, since a hard mask layer (not shown) is left, there are only two contact sides between the fin structure 112 and a dielectric layer to be formed later.

In addition, as described above, the present invention can also be applied to other kinds of semiconductor substrates. For example, in another embodiment, an insulating substrate (not shown) is provided and etched by etching and lithography. The formation of the fin structure on the insulating substrate can be completed by covering the single crystal germanium layer on the insulating substrate (not shown) and stopping at the oxide layer.

In addition, in order to clearly disclose the present invention, only two fin structures 112 are shown in the present embodiment, but the fin structures 112 to which the present invention can be applied may also be a combination of three or more arrays.

Then, the insulating structure 10 is etched back, and as shown in Fig. 3, the insulating structure 10a is formed. In the present embodiment, the etched back insulating structure 10a has a bottom portion 12a and two side wall portions 12b, wherein the bottom portion 12a is located on the substrate 110 between the two fin structures 112, and the side wall portions 12b are respectively located in the second fin structure 112. The opposite sides. In this way, the insulating structure 10a of the embodiment can promote the subsequently formed epitaxial structure toward the fin structure 112. The top is grown instead of covering the side walls of each fin structure 112 downward. In other embodiments, the insulating structure 10 may not be etched back, depending on actual needs. In addition, in this embodiment, the patterned hard mask layer P is removed first, and the insulating structure 10 is etched back; however, in other embodiments, the insulating structure 10 may be etched back first, and then the patterned hard mask is removed. Cover layer P.

Of course, in other embodiments, the insulating structure 10 can be etched back, or as shown in FIG. 4, the insulating structure 10b can be formed only on the substrate 110 between the two fin structures 112 without being formed in the fin structure. A spacer (not shown) is formed on the sidewall of the 112, and then selectively formed on the sidewalls of each of the fin structures 112, depending on actual process and structural requirements. In addition, in an embodiment of the insulating substrate, after etching the single crystal germanium layer and stopping the oxide layer to form the fin structure, a spacer is selectively formed on the sidewalls of each fin structure. (not shown).

As shown in FIG. 5, a gate structure G is formed across the substrate 110 and each of the fin structures 112. The gate structure G includes a gate dielectric layer 122 and a selective barrier layer (not shown). A sacrificial electrode layer 124, a cap layer 126, and a spacer 128. In detail, the gate dielectric layer 122, the selective barrier layer (not shown), the sacrificial electrode layer 124, and the cap layer 126 form a stacked structure 120, and the spacers 128 are formed on the sidewalls of the stacked structure 120. On the substrate 110. Furthermore, the method of forming the gate structure G may include sequentially covering a dielectric layer (not shown), a selective barrier layer (not shown), a sacrificial electrode layer (not shown), and a cap layer (not shown). The substrate 110 and the fin structure 112 are patterned and patterned to form a stacked structure including a gate dielectric layer 122, a selective barrier layer (not shown), a sacrificial electrode layer 124, and a cap layer 126. 120. Then, all The spacers cover the spacer material (not shown) on the stacked structure 120, the fin structure 112 and the substrate 110, and then pattern the spacer material (not shown) to form the spacers 128 on the sidewalls of the stacked structure 120. /10b and the fin structure 112.

In this embodiment, a gate-to-high gate constant (Gate-Last for High-K Last) process is performed, so that the gate dielectric layer 122 is selectively removed completely or partially in a subsequent process, and Filling in the high dielectric constant gate dielectric layer, the gate dielectric layer 122 in this embodiment may be only a sacrificial material that is generally convenient for removal in subsequent processes, such as an oxide layer, but the present invention does not This is limited. The selective barrier layer (not shown) is, for example, a single layer structure or a composite layer structure of tantalum nitride (TaN), titanium nitride (TiN) or the like. The sacrificial electrode layer 124 may be formed, for example, of polysilicon, but the invention is not limited thereto. The cover layer 126 can be a single layer or a double layer structure composed of a nitride layer or an oxide layer, and is used as a patterned hard mask, but the invention is not limited thereto. The spacer 128 is, for example, a single layer or a multilayer composite structure composed of a material such as tantalum nitride or tantalum oxide.

In another embodiment, when applied to a Gate-Last for High-K First process, the gate dielectric 122 is a high dielectric constant gate dielectric. a layer selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), and aluminum oxide (aluminum oxide, Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO _{2 )} ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), strontium bismuth tantalate (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr _1-x TiO ₃ , BST The group consisting of, but the invention is not limited thereto. Moreover, before forming the gate dielectric layer 122, a buffer layer (not shown) may be selectively formed, which may be an oxide layer, and is formed, for example, by a thermal oxidation process or a chemical oxidation process, but the present invention does not This is limited. A buffer layer (not shown) is located between the gate dielectric layer 122 and the substrate 110 and serves as a buffer for the gate dielectric layer 122 and the substrate 110.

As shown in FIG. 6, an epitaxial structure 130 is selectively formed on each of the fin structures 112. The epitaxial structure 130 can be, for example, a germanium epitaxial structure for forming an epitaxial structure of a PMOS transistor, or a germanium carbon epitaxial structure/phosphorus-doped germanium epitaxial structure for forming an NMOS transistor. Epitaxial structure, but the invention is not limited thereto. In this embodiment, since the sidewall portion 12b of the insulating structure 10 covers the sidewall of the fin structure 112, the epitaxial structure 130 grown by the epitaxial technique can be an upwardly growing pentagon structure as shown, instead of The fin structure 112 is covered. Furthermore, the cross-sectional structure of the epitaxial structure 130 of the present embodiment has a laterally widest portion 132, so that each of the fin structures 112 can have a narrow opening between the middle width (as shown in FIG. 6). Greater than the opening width Degree b), in order to facilitate the subsequent comprehensive coverage of the dielectric layer, the pores may be formed between the fin structures 112 and the lateral widest portions 132 of the epitaxial structures 130, respectively, to achieve the object of the present invention, but the present invention Not limited to this. In other embodiments, the shape of the elongated epitaxial structure 130 can also be controlled by adjusting the depth and shape of the insulating structure 10 after etching back.

Subsequently, a source/drain (not shown) is formed in the epitaxial structure 130 or/and the fin structure 112 on the side of the gate structure G, respectively. In other embodiments, the source/drain (not shown) may also be formed prior to forming the epitaxial structure 130 or together with the epitaxial structure 130. In addition, it should be noted that, in various embodiments of the present invention, the present invention is formed by forming a spacer (not shown) on the sidewalls of each of the fin structures 112, respectively, in the foregoing steps. After forming the gate structure G and the epitaxial structure 130 on each fin structure 112, a step of etching a portion of the insulating structure 10 may be selectively performed to increase the aspect ratio of the gap between the fin structures 112. , depending on actual needs.

As shown in FIG. 7, a dielectric layer 140 is formed to cover the substrate 110 and the fin structure 112, wherein the dielectric layer 140 is formed between the fin structures 112 on both sides of the gate structure G. in. The dielectric layer 140 can be, for example, a chemical vapor deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or a high density plasma chemical vapor deposition (High). The process of forming a process is preferably performed by forming a dielectric layer 140 into the dielectric layer 140 when the dielectric layer 140 is formed. Furthermore, the invention can The position at which the pores V are formed is controlled by adjusting the depth d of the etch-back insulating structure 10a or the like, for example, an etching process after forming the insulating structure 10a or forming the gate structure G and the epitaxial structure 130, and adjusting the insulating structure 10a. The shape of the equals controls the size and shape of the formation of the pores V. In addition, the present invention can also adjust the position, size and shape of the pores V by forming the epitaxial structure 130 on the fin structure 112. Taking the embodiment as an example, since the cross-sectional structure of the epitaxial structure 130 has a laterally widest portion 132, the fin structures 112 may have a narrow opening between the middle and the width, so that the dielectric layer 140 is covered. When the fin structure 112 and the substrate 110 are on, the dielectric layer 140 is more difficult to fill between the fin structures 112, and the dielectric layer 140 between the fin structures 112 can form the pores V. Still further, the aperture V is located below the laterally widest portion 132. Of course, in other embodiments, the epitaxial structure 130 may not be formed, but the position, size, and shape of the aperture V may be controlled by adjusting the depth and shape of the insulating structure 10a, etc., wherein the aperture V is preferably located in the fin shape. Below the top T of the structure 112.

The step of forming the dielectric layer 140: firstly covering the dielectric layer (not shown) on the substrate 110, the fin structure 112, and the gate structure G, and then planarizing the dielectric layer (not shown) to expose the sacrifice Electrode layer 124 (as shown in Figure 7). Then, a metal gate replacement (RMG) process is performed to replace the sacrificial electrode layer 124 and the gate dielectric layer 122 with a metal gate M, as shown in FIG. Specifically, the sacrificial electrode layer 124 can be removed and the gate dielectric layer 122 can be selectively removed; then, a selective buffer layer (not shown) and a high dielectric constant layer are sequentially formed at the same position. Electrical layer (not shown), a selective bottom barrier layer (not shown), a work function metal layer (not shown), a selective top barrier layer (not shown), and a low A resistive material (not shown) is ground to the dielectric layer 140 to form a metal gate M, wherein the metal gate M includes a buffer layer 152, a high-k dielectric layer 154, and a selective bottom resistance. A barrier layer (not shown), a work function metal layer 156, a selective top barrier layer (not shown), and a low resistivity material 158. Therefore, the buffer layer 152 in the metal gate M, the high-k dielectric layer 154, the selective bottom barrier layer (not shown), the work function metal layer 156, and the selective top barrier layer (not All of them have a U-shaped cross-sectional structure. Subsequent semiconductor processes can then be continued to form the desired semiconductor structure. In another embodiment, the gate dielectric layer 122 may not be removed and extended as a buffer layer. In this case, after the sacrificial electrode layer 124 is removed, the buffer layer needs to be formed again, thus completing the structure. The middle buffer layer 152 will have a cross-sectional structure of a straight line.

In this embodiment, the insulating structure 10 is first formed on the substrate 110 between the fin structures 112, and etched back to form the insulating structure 10a; thereafter, the gate structure G is formed to span the fin structure 112 and the substrate 110. Then, an epitaxial structure 130 is formed on the fin structure 112 on the side of the gate structure G; the dielectric layer 140 is completely covered while the void V is formed in the dielectric layer 140 between the fin structures 112. However, the multi-gate field effect transistor process provided by the present invention can also be applied to various semiconductor processes without being limited to the embodiment. Another embodiment is further described below, in which the epitaxial structure 130 is formed first, and then the insulating structure 10 is etched back to form the gate structure G.

8-9 are schematic cross-sectional views showing a process of a multi-gate field effect transistor according to a second embodiment of the present invention. The previous stage process of this embodiment is the same as the previous embodiment (such as the first 1-2) As shown, a second fin structure 112 is formed on a substrate 110 (as shown in FIG. 1); an insulating structure 10 is formed on the substrate 110 between the second fin structures 112 (as shown in FIG. 2). Thereafter, the insulating structure 10 is not etched back, and as shown in FIG. 8, an epitaxial structure 130 is formed on each of the fin structures 112, respectively. Then, the insulating structure 10 is etched back, and as shown in Fig. 9, the insulating structure 10a is formed. It is noted that in the previous embodiment, the insulating structure 10a is formed having a bottom portion 12a and two side wall portions 12b, wherein the bottom portion 12a is located on the substrate 110 between the two fin structures 112, and the side wall portions 12b are respectively located at two The opposite sides of the fin structure 112 are formed by isolating the fin structure 112 to form an upwardly grown epitaxial structure 130, so that a desired void V can be formed when the dielectric layer is subsequently filled. In the present embodiment, since the epitaxial structure 130 is formed first without etching back the insulating structure 10, the insulating structure 10 has been isolated from the fin structure 112 so that the epitaxial structure 130 can be directly formed upward. Therefore, when the insulating structure 10 is etched back, the side wall portion 12b of the insulating structure 10a on the sidewall of the fin structure 112 may be selected to be formed, and the insulating structure 10b may be directly formed (as indicated by a broken line in FIG. 10), and may even be further An isotropic etching, such as wet etching, is used to completely hollow the insulating structure 10 between the fin structures 112. Here, for the convenience of the following description, the insulating structure 10a is taken as an example for illustration, which is consistent with the drawing of FIGS. 6-7.

Furthermore, the epitaxial structure 130 of the present embodiment is the same as the previous embodiment, preferably an upwardly growing pentagon structure without covering the fin structure 112, and the cross-sectional structure of the epitaxial structure 130 has a The lateral widest portion 132, such that each of the fin structures 112 may have a narrow opening above the middle width (as shown in FIG. 9 , the intermediate width a is greater than the opening width b), so that the subsequently fully covered dielectric layer can be Fin structure 112 and epitaxial An aperture is formed below the laterally widest portion 132 of the structure 130 for the purposes of the present invention. In addition, since the top surface of the entire fin structure 112 forms an epitaxial structure 130, the epitaxial structure 130 may be only germanium epitaxial, and a polyhedron may be formed due to a specific angle of epitaxial growth. In this way, the epitaxial structure 130 can enjoy a plurality of direct contact faces with the subsequently formed gate structure to form a multi-gate field effect transistor having a larger channel width. Of course, the epitaxial structure 130 can also be, for example, an epitaxial structure for forming an epitaxial structure of a PMOS transistor, or a carbon epitaxial structure for forming an epitaxial structure of an NMOS transistor. This is limited to this.

Then, as shown in FIG. 6, the gate structure G is formed across the epitaxial structure 130 and the substrate 110. The gate structure G includes a gate dielectric layer 122 and a selective barrier layer (not shown). A sacrificial electrode layer 124, a cap layer 126, and a spacer wall 128 are formed in the same manner as the previous embodiment, and thus will not be described again. Thereafter, a source/drain (not shown) is formed in the epitaxial structure 130 or/and the fin structure 112 on the side of the gate structure G, respectively. In other embodiments, the source/drain (not shown) may also be formed prior to forming the epitaxial structure 130 or together with the epitaxial structure 130. Subsequent semiconductor processes can then be continued to form the desired semiconductor structure.

Then, as shown in FIG. 7, a dielectric layer 140 is formed to cover the substrate 110 and the epitaxial structure 130, wherein the two holes V are respectively formed in the dielectric layer between the fin structures 112 on both sides of the gate structure G. 140. The dielectric layer 140 can be, for example, a chemical vapor deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or a high process. A high-density plasma chemical vapor deposition (HDPCVD) process is formed, wherein the process is preferably formed in the dielectric layer 140 when the dielectric layer 140 is formed. Furthermore, the present invention can control the size and shape of the formation of the pores V by adjusting the depth of the etch back insulating structure 10a to control the position at which the pores V are formed, and the shape of the insulating structure 10a. In addition, the present invention can also adjust the position, size and shape of the pores V by forming an epitaxial structure on the fin structure 112. Taking the embodiment as an example, since the cross-sectional structure of the epitaxial structure 130 has a laterally widest portion 132, the fin structures 112 may have a narrow opening between the middle and the width, so that the dielectric layer 140 is covered. When the fin structure 112 and the substrate 110 are on, the dielectric layer 140 is more difficult to fill between the fin structures 112, and the pores V may be formed in the dielectric layer 140 between the fin structures 112. Still further, the aperture V is located below the laterally widest portion 132. Of course, in other embodiments, the epitaxial structure 130 may not be formed, but the position, size, and shape of the aperture V may be controlled by adjusting the depth and shape of the insulating structure 10a, wherein the aperture V is preferably located in the fin structure. Below the top T of 112.

It should also be noted that, after forming the epitaxial structure 130 and/or the gate structure G on each of the fin structures 112, the present embodiment may selectively perform a step of etching a portion of the insulating structure 10a to increase each The aspect ratio of the gap between the fin structures 112 depends on actual needs.

The step of forming the dielectric layer 140: firstly covering the dielectric layer (not shown) on the substrate 110, the fin structure 112, and the gate structure G, and then planarizing the dielectric layer (not shown) The sacrificial electrode layer 124 is exposed (as shown in FIG. 7). Then, a metal gate replacement (RMG) process is performed to replace the sacrificial electrode layer 124 and the gate dielectric layer 122 with a metal gate M, as shown in FIG. Specifically, the sacrificial electrode layer 124 may be sequentially removed and the gate dielectric layer 122 may be selectively removed; then, a selective buffer layer (not shown) and a high dielectric are sequentially formed at the same position. a constant dielectric layer (not shown), a selective bottom barrier layer (not shown), a work function metal layer (not shown), a selective top barrier layer (not shown), and a low resistivity material (not shown) is ground to the dielectric layer 140 to form a metal gate M, wherein the metal gate M comprises a buffer layer 152, a high-k dielectric layer 154, and a selective A bottom barrier layer (not shown), a work function metal layer 156, a selective top barrier layer (not shown), and a low resistivity material 158. Therefore, the buffer layer 152 in the metal gate M, the high-k dielectric layer 154, the selective bottom barrier layer (not shown), the work function metal layer 156, and the selective top barrier layer (not All of them have a U-shaped cross-sectional structure. Subsequent semiconductor processes can then be continued to form the desired semiconductor structure. In another embodiment, the gate dielectric layer 122 may not be removed and extended as a buffer layer. In this case, after the sacrificial electrode layer 124 is removed, the buffer layer needs to be formed again, thus completing the structure. The middle buffer layer 152 will have a cross-sectional structure of a straight line.

The process of the multi-gate field effect transistor of the first embodiment is slightly different, and the structure of the multi-gate field effect transistor formed is substantially the same, except that the epitaxial structure 130 of the second embodiment is formed in the whole On the strip fin structure 112, there is more than the epitaxial structure 130 of the first embodiment located directly under the metal gate M. However, above these two embodiments The views are all the same. As shown in FIG. 10, a top view of a multi-gate field effect transistor according to an embodiment of the present invention is shown. A multi-gate field effect transistor 100 includes at least two fin structures 112 on a substrate 110. A metal gate M is spanned over the fin structure 112 and the substrate 110. An epitaxial structure 130 is selectively located on the fin structure 112 on the side of the metal gate M. A source/drain (not shown) is respectively located in the fin structure 112 or/and the epitaxial structure 130 on the side of the metal gate M, and the source/drain in each fin structure 112 (not shown) They are electrically connected to a source terminal S and a terminal D, respectively. The dielectric layer 140 covers the fin structure 112 and the substrate 110, and the dielectric layer 140 between the fin structures 112 has a void V therein. The configuration methods and functions of the above-mentioned components have been described in the foregoing two embodiments, and therefore will not be described again.

In summary, the present invention provides a multi-gate field effect transistor and a process thereof, which form a pore in a dielectric layer between the fin structures, and reduce a multi-gate field effect transistor, particularly a fin structure. Parasitic capacitance between. Preferably, the pores are located below the top end of the fin structure. More preferably, an epitaxial structure having a laterally widest portion can be formed on the fin structure to cause the pores to be located below the widest portion of the lateral direction, thereby making it easier and more accurate to control the position, size and shape of the pores. Furthermore, the present invention can control the position, size and shape of the apertures by adjusting the depth and shape of the insulating structures on the substrate between the fin structures. Moreover, the present invention directly forms a dielectric layer between the fin structures, which can reduce the process cost more than the process of completely filling the dielectric layer.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10, 10a, 10b‧‧‧ insulation structure

12a‧‧‧ bottom

12b‧‧‧ Sidewall

110‧‧‧Base

112‧‧‧Fin structure

120‧‧‧Stack structure

122‧‧‧ gate dielectric layer

124‧‧‧Sacrificial electrode layer

126‧‧‧ cover

128‧‧‧ spacer

130‧‧‧ epitaxial structure

132‧‧‧ horizontal widest part

140‧‧‧Dielectric layer

152‧‧‧buffer layer

154‧‧‧High dielectric constant dielectric layer

156‧‧‧Work function metal layer

158‧‧‧ Low resistivity material

A‧‧‧intermediate width

B‧‧‧ opening width

D‧‧‧depth

D‧‧‧汲 Extreme

G‧‧‧ gate structure

M‧‧‧Metal gate

P‧‧‧ patterned hard mask layer

S‧‧‧ source extreme

T‧‧‧ top

V‧‧‧ pores

1-7 are schematic cross-sectional views showing a process of a multi-gate field effect transistor according to a first embodiment of the present invention.

8-9 are schematic cross-sectional views showing a process of a multi-gate field effect transistor according to a second embodiment of the present invention.

Fig. 10 is a top view showing a multi-gate field effect transistor according to an embodiment of the present invention.

11 is a cross-sectional view showing a process of a multi-gate field effect transistor according to an embodiment of the present invention.

10a‧‧‧Insulation structure

12a‧‧‧ bottom

12b‧‧‧ Sidewall

110‧‧‧Base

112‧‧‧Fin structure

128‧‧‧ spacer

130‧‧‧ epitaxial structure

132‧‧‧ horizontal widest part

140‧‧‧Dielectric layer

152‧‧‧buffer layer

154‧‧‧High dielectric constant dielectric layer

156‧‧‧Work function metal layer

158‧‧‧ Low resistivity material

D‧‧‧depth

M‧‧‧Metal gate

T‧‧‧ top

V‧‧‧ pores

Claims (22)

A multi-gate field effect transistor comprising: a second fin structure on a substrate; and a dielectric layer covering the substrate and the second fin structure, and at least two pores between the two fin structures In the dielectric layer. The multi-gate field effect transistor according to claim 1, wherein each of the two fin structures is further provided with an epitaxial structure. The multi-gate field effect transistor according to claim 2, wherein the cross-sectional structure of each of the epitaxial structures has a lateral widest portion. The multi-gate field effect transistor of claim 3, wherein the two apertures are located below the lateral widest portion. The multi-gate field effect transistor of claim 1, wherein the two apertures are located below a top end of the second fin structure. The multi-gate field effect transistor according to claim 1, further comprising: an insulating structure on the substrate between the two fin structures. The multi-gate field effect transistor of claim 6, wherein the insulating structure has a bottom, the substrate between the two fin structures, and two sidewalls The portions are respectively located on opposite sides of the two fin structures. The multi-gate field effect transistor according to claim 1, further comprising: a gate structure disposed in the dielectric layer, spanning the substrate and the second fin structure, and located in the second aperture between. The multi-gate field effect transistor according to claim 8, further comprising: the two source/drain electrodes are respectively located in the two fin structures on the side of the gate structure. A multi-gate field-effect transistor process includes: forming a second fin structure on a substrate; and forming a dielectric layer covering the substrate and the second fin structure, wherein at least two pores are formed in the second fin The structure is between the dielectric layers. The multi-gate field-effect transistor process as described in claim 10, further comprising: forming an epitaxial structure on each of the two fin structures. The multi-gate field effect transistor process of claim 11, wherein the cross-sectional structure of each of the epitaxial structures has a laterally widest portion. The multi-gate field effect transistor process of claim 12, wherein the two apertures are formed below the lateral widest portion. The multi-gate field effect transistor process of claim 10, wherein the two pores are formed below the top end of the second fin structure. The multi-gate field effect transistor process of claim 10, wherein the dielectric layer comprises a chemical vapor deposition (CVD) process and plasma enhanced chemical vapor deposition (Plasma Enhance). Chemical Vapor Deposition (PECVD) process, or high-density plasma chemical vapor deposition (HDPCVD) process. The multi-gate field effect transistor process of claim 10, after forming the second fin structure, further comprises: forming an insulating structure on the substrate between the two fin structures. The multi-gate field-effect transistor process of claim 16, wherein after forming the insulating structure, the method further comprises: etching back the insulating structure. The multi-gate field effect transistor process of claim 17, wherein the etched back insulating structure has a bottom portion on the substrate between the two fin structures, and the two side wall portions are respectively located The opposite sides of the two fin structure. The multi-gate field-effect transistor process as described in claim 18 of the patent application, in eclipse After the insulating structure is engraved, the method further comprises: forming an epitaxial structure on the second fin structure respectively. The multi-gate field effect transistor process of claim 16, wherein after forming the insulating structure, further comprising: forming an epitaxial structure on the second fin structure respectively; and etching back the insulating structure. The multi-gate field effect transistor process of claim 10, after forming the second fin structure, further comprises: forming a gate structure spanning the substrate and the second fin structure. The multi-gate field-effect transistor process as described in claim 21, after forming the gate structure, further comprising: forming the two-fin structure of the two source/drain electrodes respectively on the side of the gate structure in.