EP3675187B1 - Optimised methods for manufacturing a structure to be assembled by hybridisation and a device including such a structure - Google Patents

Description

Technical area

The invention relates to the field of semiconductor devices and more particularly to optoelectronic devices.

The subject of the invention is thus more precisely a method of manufacturing a semiconductor structure intended to be assembled by hybridization to a support and a method of manufacturing a device comprising a structure and support to which said structure is assembled by hybridization.

State of the prior art

The manufacture of certain semiconductor devices may require a connection operation, for example by hybridization, of a semiconductor structure on a dedicated support. This is particularly the case for optoelectronic devices for which said structure can be made in one or more semiconductor materials called III-V and the support is made of silicon, the latter possibly including a control circuit for said structure based on C-MOS type technology.

To allow such a connection by hybridization, it is known, in particular documents WO 2006/054005 and WO 2009/115686 , to provide the structure with inserts and the support with pads of ductile conductive material, the connection being obtained by inserting the inserts into said pads of ductile conductive material.

• la gravure localisée d'au moins une couche active dans laquelle est aménagée la région active de chacune des structures, cette gravure permettant d'isoler les régions actives entre elles de manière à former lesdites structures indépendamment les unes des autres, et
• une séparation de ces dites structures du substrat.

The manufacture of a structure suitable for such a connection, that is to say comprising said inserts, is generally carried out in several collective steps, making it possible to manufacture a plurality of structures on the same support, and with individualization steps. including in particular:

• the localized etching of at least one active layer in which the active region of each of the structures is arranged, this etching making it possible to isolate the regions active between themselves so as to form said structures independently of each other, and
• a separation of these said structures from the substrate.

Now, when the at least one active layer of such a structure comprises a nitrided semiconductor material, such as gallium nitride, the step of localized etching of the at least one active layer must necessarily use a method of particularly abrasive physicochemical etching. It therefore results, in order to provide the location of this etching, that it is necessary to use a suitable mask, such as a hard mask made of silicon dioxide, or a resin mask, having a relatively large thickness, this mask itself being etched during etching of the active layer.

Thus, if such a manufacturing process allows perfect individualization of the structures, it nevertheless has the drawback of being relatively complex to implement, since it requires the use of a mask of relatively large thickness. In addition, with such a process for manufacturing structures, the steps for individualizing the structures are decorrelated from the positioning of the inserts, there is therefore a significant risk of an alignment problem between the delimitation of the structure and the inserts. To limit this latter risk, it is therefore necessary to oversize the semiconductor structure.

WO 2018/033689 A1 and US 2013/328013 A1 disclose methods of manufacturing semiconductor structures.

Disclosure of the invention

The invention aims to remedy these drawbacks and thus aims to provide a method of manufacturing a semiconductor structure intended to be connected by hybridization to a support substrate comprising at least one active layer in a nitrided semiconductor, said method being simplified by -to the methods of the prior art allowing the formation of such a semiconductor structure, and providing an alignment between the boundaries of the structure and the inserts.

• fourniture d'un premier support qui comporte un substrat et au moins une couche active, ladite couche active comprenant au moins un matériau semiconducteur nitruré, au moins une région active de ladite structure semiconductrice et au moins une première et une deuxième zone de connexion de ladite région active qui affleurent une surface du premier support étant aménagées dans la couche active,
• formation d'au moins un premier et un deuxième corps d'insert en contact électrique avec respectivement la première et la deuxième zone de connexion, ladite étape de formation comprenant la formation d'une couche de nickel recouvrant une portion de la surface du premier support, ladite couche de nickel étant disposée sur la surface du support au niveau de la région active en recouvrant au moins partiellement les première et deuxième zones de connexion,
• gravure physico-chimique localisée de la couche active, la localisation de la gravure étant fournie par une protection d'une partie de la couche active comprenant la région active par la couche de nickel,
• gravure physico-chimique de la couche de nickel, la gravure étant stoppée après libération d'au moins une partie de la surface du premier support de ladite couche de nickel, la partie de la surface du premier support comprenant la surface du premier support en dehors des première et deuxième zones de connexion, une portion restante de la couche de nickel et de chacun des premier et deuxième corps d'insert permettant la formation d'un premier et d'un deuxième insert,
• libération de la couche active du premier substrat, ladite libération permettant de former la structure semiconductrice.

To this end, the invention relates to a method of manufacturing a semiconductor structure intended to be connected by hybridization to a support substrate, said structure comprising the following steps:

• providing a first support which comprises a substrate and at least one active layer, said active layer comprising at least one nitrided semiconductor material, at least one active region of said semiconductor structure and at least a first and a second connection area of said active region which are flush with a surface of the first support being arranged in the active layer,
• forming at least a first and a second insert body in electrical contact with the first and the second connection zone, respectively, said forming step comprising forming a layer of nickel covering a portion of the surface of the first support , said layer of nickel being disposed on the surface of the support at the level of the active region, at least partially covering the first and second connection zones,
• localized physicochemical etching of the active layer, the location of the etching being provided by protection of a part of the active layer comprising the active region by the nickel layer,
• physico-chemical etching of the nickel layer, the etching being stopped after release of at least part of the surface of the first support from said layer of nickel, the part of the surface of the first support comprising the surface of the first support outside first and second connection zones, a remaining portion of the nickel layer and of each of the first and second insert bodies allowing the formation of a first and a second insert,
• release of the active layer from the first substrate, said release making it possible to form the semiconductor structure.

In this way, the localized etching allowing to individualize the structure makes it possible to provide a delimitation of the structure which is aligned with the inserts. It is in fact the layer of nickel, which is included in the inserts, which serves as a mask during this localized etching.

What is more, since nickel exhibits a relatively low, or even substantially zero, etching rate with respect to the physico-chemical etching processes used to etch nitrided semiconductor materials, it is not necessary for this layer to have a thickness important as is the case for the engraving mask used for the etching of the active layer in the prior art. This same layer of nickel participating in the formation of the insert, the removal of unnecessary portions of said layer produced by physicochemical etching allows the formation of the first and second inserts. Thus, unlike the prior art, the step of removing the mask used during the localized etching of the active layer is fully useful, since it participates in the formation of the inserts. It therefore follows that the manufacturing method according to the invention presents a simplification with respect to the methods of the prior art.

The terms "conductor" and "insulator", when used above and throughout the remainder of this document, should be understood as "electrical conductor" and "electrical insulator".

• formation d'au moins une première et une deuxième portion respective de couche métallique recouvrant respectivement la première et la deuxième zone de connexion,
• formation d'un premier et d'un deuxième corps d'insert en contact respectivement de la première et deuxième portions de couche métallique,
• dépôt de la couche de nickel en contact de la surface du support des première et deuxième portions de couche métallique et des premier et deuxième corps d'insert, la couche de nickel formant un revêtement des premier et deuxième corps d'insert.

The step of forming the first and second insert may include the following sub-steps:

• formation of at least a first and a second respective portion of metal layer covering respectively the first and the second connection zone,
• formation of a first and a second insert body in contact respectively with the first and second metal layer portions,
• depositing the nickel layer in contact with the surface of the support of the first and second metal layer portions and of the first and second insert bodies, the nickel layer forming a coating of the first and second insert bodies.

In this way, the nickel layer forms both a coating of the insert bodies, participating in the formation of said inserts, and an etching mask for the release of the active layer allowing the singularization of said semiconductor structure. Such a singularization is particularly advantageous in the context of parallel manufacturing of a structure according to the invention.

• formation d'au moins une première et une deuxième portion respective de couche métallique recouvrant respectivement la première et la deuxième zone de connexion,
• dépôt de la couche de nickel en recouvrant la surface du support libre de première et de deuxième portion de couche métallique et lesdites première et deuxième portions de couche métallique,
• formation d'un premier et d'un deuxième corps d'insert en contact avec la couche de nickel au niveau de, respectivement, la première et la deuxième portion de couche métallique.

The step of forming the first and second insert body may include the following sub-steps:

• formation of at least a first and a second respective portion of metal layer covering respectively the first and the second connection zone,
• deposition of the nickel layer by covering the surface of the free support with first and second metallic layer portions and said first and second metallic layer portions,
• forming a first and a second insert body in contact with the nickel layer at the level of, respectively, the first and the second metal layer portion.

In this way, the nickel layer participates in the formation of the base of each of the inserts.

The first and second insert bodies can include nickel.

In this way, and in a manner similar to the nickel layer, the first and second insert bodies are not or only slightly etched during the step of localized physicochemical etching of the active layer.

The first and the second insert body can include a carbide of silicon carbide and tungsten carbide.

Such materials are particularly suitable, because of their hardness, for connection by hybridization of the semiconductor structure to a second support.

The active layer can comprise a gallium nitride.

The method according to the invention is particularly suitable for such a material of the active layer.

The active part of the semiconductor structure can be a diode, the first and second connection zones corresponding respectively to the metal contacts of the anode and of the cathode of said diode.

• une première sous-couche active présentant un premier type de conductivité, la deuxième zone de connexion étant une zone de connexion de ladite première sous-couche active,
• une zone active adaptée pour émettre de la lumière, ladite zone active comprenant préférentiellement au moins un puits quantique,
• une deuxième sous-couche active présentant un deuxième type de conductivité opposé au premier type de conductivité, la première zone de connexion étant une zone de connexion de ladite deuxième sous-couche active.

The active layer can include:

• a first active sublayer having a first type of conductivity, the second connection zone being a connection zone of said first active sublayer,
• an active area suitable for emitting light, said active area preferably comprising at least one quantum well,
• a second active sub-layer having a second type of conductivity opposite to the first type of conductivity, the first connection area being a connection area of said second active sub-layer.

• formation d'une structure semiconductrice au moyen d'un procédé de fabrication selon l'invention,
• fourniture d'un deuxième support comprenant au moins une troisième et une quatrième zone de connexion en correspondance avec la première et la deuxième zone de connexion de la structure semiconductrice, et un premier et un deuxième plot en matériau conducteur ductile en contact électrique avec respectivement la troisième et la quatrième zone de connexion,
• connexion des première et deuxième zones de connexion avec respectivement les troisième et quatrième zones de connexion par insertion des premier et deuxième inserts dans respectivement le premier et le deuxième plot en matériau conducteur ductile.

The invention further relates to a method of manufacturing a device comprising a semiconductor structure, the method comprising the following steps:

• formation of a semiconductor structure by means of a manufacturing method according to the invention,
• provision of a second support comprising at least a third and a fourth connection zone in correspondence with the first and the second connection zone of the semiconductor structure, and a first and a second pad made of ductile conductive material in electrical contact respectively with the third and fourth connection area,
• connection of the first and second connection zones with respectively the third and fourth connection zones by inserting the first and second inserts in respectively the first and the second pad made of ductile conductive material.

Such a manufacturing process benefits from the benefits associated with a step of providing a semiconductor structure in accordance with the manufacturing process of the invention.

The semiconductor structure is a light emitting diode, the second support comprising a control circuit suitable for supplying and controlling said light emitting diode.

Brief description of the drawings

• la figure 1 est une vue en section d'un dispositif selon un premier mode de réalisation de l'invention, le dispositif comprenant une structure assemblée par hybridation sur un support de commande,
• la figure 2 est une vue en section d'une première étape d'un procédé de fabrication de la structure de la figure 1,
• la figure 3 est une vue en section d'une deuxième étape d'un procédé de fabrication de la structure de la figure 1,
• la figure 4 est une vue en section d'une troisième étape d'un procédé de fabrication de la structure de la figure 1,
• la figure 5 est une vue en section d'une quatrième étape d'un procédé de fabrication de la structure de la figure 1,
• la figure 6 est une vue en section d'une cinquième étape d'un procédé de fabrication de la structure de la figure 1,
• la figure 7 est une vue en section d'une sixième étape d'un procédé de fabrication de la structure de la figure 1,
• la figure 8 est une vue en section d'une septième étape d'un procédé de fabrication de la structure de la figure 1,
• la figure 9 est une vue en section d'une huitième étape d'un procédé de fabrication de la structure de la figure 1,
• la figure 10 est une vue en section d'une première étape d'un procédé de fabrication d'une structure selon un deuxième mode de réalisation de l'invention,
• la figure 11 est une vue en section d'une deuxième étape d'un procédé de fabrication d'une structure selon un deuxième mode de réalisation de l'invention,
• la figure 12 est une vue en section d'une troisième étape d'un procédé de fabrication d'une structure selon un deuxième mode de réalisation de l'invention.

The present invention will be better understood on reading the description of exemplary embodiments, given purely as an indication and in no way limiting, with reference to the appended drawings in which:

• the figure 1 is a sectional view of a device according to a first embodiment of the invention, the device comprising a structure assembled by hybridization on a control support,
• the figure 2 is a sectional view of a first step of a process for manufacturing the structure of the figure 1 ,
• the figure 3 is a sectional view of a second step of a process for manufacturing the structure of the figure 1 ,
• the figure 4 is a sectional view of a third step of a method of manufacturing the structure of the figure 1 ,
• the figure 5 is a sectional view of a fourth step of a method of manufacturing the structure of the figure 1 ,
• the figure 6 is a sectional view of a fifth step of a method of manufacturing the structure of the figure 1 ,
• the figure 7 is a sectional view of a sixth step of a method of manufacturing the structure of the figure 1 ,
• the figure 8 is a sectional view of a seventh step of a method of manufacturing the structure of the figure 1 ,
• the figure 9 is a sectional view of an eighth step of a method of manufacturing the structure of the figure 1 ,
• the figure 10 is a sectional view of a first step of a method for manufacturing a structure according to a second embodiment of the invention,
• the figure 11 is a sectional view of a second step of a method for manufacturing a structure according to a second embodiment of the invention,
• the figure 12 is a sectional view of a third step of a method for manufacturing a structure according to a second embodiment of the invention.

Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another.

The different parts shown in the figures are not necessarily on a uniform scale, to make the figures more readable.

The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with one another.

Detailed description of particular embodiments

The figure 1 illustrates, in a side sectional view, a semiconductor device 10, such as an optoelectronic device obtainable by means of a manufacturing method according to the invention, said device comprising a semiconductor structure 100, such as a optoelectronic structure, assembled by hybridization to a support 200, such as a control support, called second support 200.

In a usual application of the invention, the semiconductor structure 100 is an optoelectronic structure. More precisely, in the context of the first and second embodiments described below, corresponding to an example of application of the invention, the semiconductor structure 100 is a light-emitting diode. Of course, this example of application is in no way limiting, the invention covers any type of semiconductor structure such as, for example, semiconductor structures suitable for detecting electromagnetic radiation, in particular photodiodes.

Such a semiconductor device thus comprises the semiconductor structure 100 and the second support 200 assembled to said semiconductor structure 100.

• une couche d'adaptation 110, présentant une première et une deuxième face,
• une première sous-couche active 111 présentant une première et une deuxième face, la première sous-couche active recouvrant la deuxième face de la couche d'adaptation 110 en ayant sa première face en contact de la deuxième face de la couche d'adaptation 110,
• une zone active 112 comprenant au moins un puits quantique, la zone active 112 recouvrant la deuxième face de la première sous-couche active 111 en ayant sa première face en contact de la deuxième face de la première sous-couche active 111,
• une deuxième couche active 113 présentant une première et une deuxième face, la deuxième sous-active 113 recouvrant la deuxième face de la zone active 112 en ayant sa première face en contact de la deuxième face de la zone active 112,
• une première couche métallique 121 recouvrant une première portion de la deuxième sous-couche active 113, la première couche métallique 121 présentant une première et une deuxième face et recouvrant ladite première portion de la deuxième sous-couche active 113 en étant en contact avec la deuxième face de la deuxième sous-couche active 113,
• une couche isolante 131, 132 recouvrant la première couche métallique 121 et la partie de la deuxième sous-couche active 113 qui est libre de première couche métallique 121, la couche isolante 131, 132 présentant une première et une deuxième face et la couche isolante 131, 132 recouvrant la deuxième face de la première couche métallique 121 et la deuxième face de la deuxième sous-couche active 113 qui est libre de première couche métallique 121 en étant en contact avec lesdites deuxièmes faces par sa première face, la deuxième face de la couche isolante 131, 132 formant une surface de la structure semiconductrice 100,
• un premier et un deuxième via métallique 122A, 122B s'étendant à partir de la première couche métallique 121 au travers de la couche isolante 131, 132 en débouchant à la surface de la couche isolante 131, 132 pour former une première et une deuxième première zone de connexion,
• un troisième et un quatrième via métallique 123A, 123B, s'étendant à partir de la première couche active 111 au travers de la zone active 112, la deuxième couche active 113 et la couche isolante 132 en débouchant à la surface de ladite couche isolante 132 pour former une première et une deuxième deuxième zone de connexion de ladite structure semiconductrice 100, le troisième et le quatrième via métallique 123A, 123B présentant chacun un revêtement isolant 133 agencé pour les isoler électriquement d'au moins la deuxième sous-couche active 113,
• un premier et un deuxième premier insert 142A, 142B en contact avec respectivement la première et la deuxième première zone de connexion 122A, 122B,
• un premier et un deuxième deuxième insert 143A, 143B en contact avec respectivement la première et le deuxième deuxième zone de connexion 123A, 123B.

The semiconductor structure comprises, as illustrated in the figure 1 :

• an adaptation layer 110, having a first and a second face,
• a first active sublayer 111 having a first and a second face, the first active sublayer covering the second face of the adaptation layer 110 having its first face in contact with the second face of the adaptation layer 110 ,
• an active area 112 comprising at least one quantum well, the active area 112 covering the second face of the first active sublayer 111 having its first face in contact with the second face of the first active sublayer 111,
• a second active layer 113 having a first and a second face, the second sub-active 113 covering the second face of the active zone 112 having its first face in contact with the second face of the active zone 112,
• a first metallic layer 121 covering a first portion of the second active sublayer 113, the first metallic layer 121 having a first and a second face and covering said first portion of the second active sublayer 113 while being in contact with the second face of the second active sublayer 113,
• an insulating layer 131, 132 covering the first metallic layer 121 and the part of the second active sub-layer 113 which is free of the first metallic layer 121, the insulating layer 131, 132 having a first and a second face and the insulating layer 131 , 132 covering the second face of the first metallic layer 121 and the second face of the second active sub-layer 113 which is free of the first metallic layer 121 while being in contact with said second faces by its first face, the second face of the insulating layer 131, 132 forming a surface of the semiconductor structure 100,
• a first and a second metallic via 122A, 122B extending from the first metallic layer 121 through the insulating layer 131, 132 opening out at the surface of the insulating layer 131, 132 to form a first and a second first connection area,
• a third and a fourth metallic via 123A, 123B, extending from the first active layer 111 through the active zone 112, the second active layer 113 and the insulating layer 132 opening out to the surface of said insulating layer 132 to form a first and a second second connection zone of said semiconductor structure 100, the third and the fourth metal via 123A, 123B each having an insulating coating 133 arranged to electrically insulate them from at least the second active sub-layer 113,
• a first and a second first insert 142A, 142B in contact with the first and the second first connection zone 122A, 122B respectively,
• a first and a second second insert 143A, 143B in contact with the first and the second second connection zone 123A, 123B respectively.

In such a structure, the first active sub-layer, the active area and the third active sub-layer together form an active layer 111, 112, 113 of said semiconductor structure 100 comprising at least one nitrided semiconductor.

Such a nitrided semiconductor is a III-V semiconductor comprising nitrogen as an element. Thus such a nitrided semiconductor can be a binary alloy, such as an aluminum nitride AIN, a gallium nitride GaN or an indium nitride InN, or a ternary alloy, such as an arsenide-nitride of Gallium GaAsN, a gallium-alluminum nitride AIGaN or a gallium-indium nitride InGaN or else a quaternary alloy, such as gallium-aluminum arsenide-nitride AIGaAsN or a gallium-indium arsenide-nitride InGaAsN. In a preferred application of the invention, the nitrided semiconductor is a gallium nitride GaN, the first and second active sublayers 111, 113 being made of such a semiconductor and the active zone 113 then being chosen as a function of the range of emission wavelengths chosen for the semiconductor structure 100.

What is more, due to the mode of providing the active layer 111, 112, 113 according to this first embodiment of the invention, the composition of the adaptation layer 110 is chosen so as to allow adaptation of the crystal lattice. between the active layer 111, 112, 113, that is to say the first active sub-layer 111 and the first substrate 101, illustrated in particular on the figure 2 , on which it is formed. It will be noted that, according to the preferred application of the invention in which the first active sub-layer is produced in a GaN gallium nitride, said first substrate being a silicon Si substrate, the adaptation layer 110 can be a buffer layer nitride gallium GaN with a thickness between 1 nm and 500 nm, or even between 5 nm and 100 nm.

In order to form a light-emitting diode, the first active sub-layer 111 has a first type of conductivity, the second active sub-layer 113 having a second type of conductivity opposite to the first type of conductivity. Thus, for example, the first active sub-layer 111 can be N-doped, the second active sub-layer then being P-doped. In the preferred application of the invention, namely a first and a second layer of gallium nitride GaN . By way of example in the context of such a preferred application, the thickness of the first active sub-layer 111 is between 100 nm and 3 μm, for example of the order of 700 nm. According to this same example, the thickness of the second active sub-layer 113 is between 50 nm and 300 nm, for example of the order of 100 nm.

The active zone 112 is a zone substantially empty of carriers and comprising at least one quantum well, and preferably a plurality of quantum wells. The active zone is for example constituted by a stack of one or more emissive layers each forming a quantum well, for example based on at least one of gallium nitride GaN, indium nitride InN, nitrides gallium-indium InGaN, gallium-aluminum nitrides AIGaN, aluminum nitride AIN, gallium-indium-aluminum nitrides AlInGaN, gallium phosphorus GaP, gallium-aluminum phosphors AIGaP, gallium phosphors -indium aluminum AlInGaP, or a combination of one or more of these materials. As a variant, the active zone may be an intrinsic GaN gallium nitride layer, that is to say not intentionally doped, for example with a concentration of residual donors of between 10 ¹⁵ and 10 ¹⁸ atoms / cm ³ , for example. example of the order of 10 ¹⁷ atoms / cm ³ . Such quantum wells can for example be provided by a stack of layers of gallium-indium nitride In _X Ga _1-X N / gallium nitride GaN, X being selected in a range going from 0 to 1, 0 and 1 excludes and being chosen as a function of the range of wavelengths chosen, in accordance with the general knowledge of those skilled in the art. Likewise, the thicknesses of said layers of the stack are adapted, in accordance with general knowledge of those skilled in the art, depending on the range of wavelengths chosen.

It will be noted that, by way of example, the thickness of the active zone 112 may be between 10 nm and 200 nm, for example of the order of 100 nm.

It will be noted that according to the preferred application, as a variant, the active zone can also comprise quantum dots, the dimensions and composition of which are adapted as a function of the range of wavelengths chosen.

It will be noted that, in any event, and according to the principle of the invention, at least one of the first and the second active sub-layer 111, 113 and of the active zone 112 comprises at least one nitrided semiconductor. , such as gallium nitride GaN or one of gallium nitride GaN, indium nitride InN, gallium-indium nitride InGaN, gallium aluminum nitrides AIGaN, aluminum nitride AIN, gallium-indium-aluminum nitrides AlInGaN.

The first metal layer 121 is adapted to form an ohmic contact with the second active sublayer 113. Thus, according to the preferred application of the invention and in the case where the second sublayer has a P doping, the first layer metallic may be formed, for example by a stack comprising a first sub-layer of indium In and a second sub-layer of silver Ag or alternatively by a stack comprising a first sub-layer of indium-tin oxide, known by the acronym ITO and corresponding to a mixture of indium oxide In ₂ O ₃ and of tin oxide SnO ₂ , and a second sub-layer of silver Ag. The first metal layer may for example have a thickness between 1 nm and 5 µm, or even between 5 nm and 1 µm or even between 50 nm and 500 nm
The first metal layer is arranged to leave a part of the surface of the second sublayer 113 free, this so as to allow passage for the third and the fourth via 123A, 123B without risk of short-circuit.

The insulating layer 132, for its part, can be made of silicon dioxide SiO2 or of silicon nitride Si ₂ N ₃ .

The adaptation layer 110, the first active sub-layer 111, the active area 112, the second active sub-layer 113, the metal layer 121, the insulating layer 132 together form a first support 101, 110, 111, 112, 113, 121, 131.

The third and the fourth metal via 123A, 123B extend through the active layer 112, the second active sub-layer 113 and the insulating layer 132. The third and fourth metal via 123A, 123B are made of a material conductor adapted to form an ohmic contact with the material of the first active sublayer 111. Thus, according to the preferred application of the invention, in the case where the first active sub-layer 111 is N-doped, the third and the fourth metallic via 123A, 123B can comprise a tie layer in contact with the insulating layer titanium Ti / titanium nitride TiN and a copper core Cu.

Each of the third and fourth metallic via 123A, 123B is isolated from the active zone 112 and from the second active sub-layer 113 by the insulating coating 133 which is interposed between said via and said active zones 112 and second active sub-layer 113. The insulating coating 133 can be alumina Al ₂ O ₃ .

The first and the second metal via 122A, 122B extend through the insulating layer 131, 132 in contact with the first metal layer 121. According to this first embodiment, the first and second metal via 122A, 122B are produced. in the same metallic material as that of the third and fourth metallic via 123A, 123B. Thus, according to the preferred application of the invention, the first and the second first via 122A, 122B can comprise a bonding layer in contact with the insulating coating 133 titanium Ti / titanium nitride TiN and a copper core Cu

The first and second metal via 122A, 122B and the third and fourth metal via 123A, 123B are flush with the surface of the insulating layer 131 and therefore of the semiconductor structure 100. The first and second metal via 122A, 122B thus form the first connection zone and the third and fourth metallic via 123A, 123B form the second connection zone.

• une portion de deuxième couche métallique 148 recouvrant la zone de connexion correspondant,
• un corps d'insert 145A, 145B, 146A, 146B,
• une couche de nickel 147 recouvrant partiellement le corps d'insert 145A, 145B, 146A, 146B.

The first and second connection zones are in contact with the first and the second first insert 142A, 142B and the first and the first insert, respectively. second second insert 143A, 143B. Each of the first and second first inserts 142A, 142B and of the first and second second inserts 143A, 143B, comprises:

• a portion of a second metal layer 148 covering the corresponding connection zone,
• an insert body 145A, 145B, 146A, 146B,
• a nickel layer 147 partially covering the insert body 145A, 145B, 146A, 146B.

The portions of second metal layer 148 each extend beyond the connection zone by covering part of the surface of the insulating layer 131 and being spaced from each other. In the context of the preferred application of the invention, the second metallic layer 148 can be a layer of titanium nitride TiN.

The insert body 145A, 145B, 146A, 146B of each of the first and second first insert 142A, 142B and of each of the first and second second insert 143A, 143B, has a cylindrical shape of hollow revolution, the base opposite to the portion of the corresponding second metallic layer 148 being absent.

Of course, such a hollow cylindrical shape of the insert body 145A, 145B, 146A, 146B is provided only by way of example, the insert body 145A, 145B, 146A, 146B of each of the first and second first insert 142A, 142B and each of the first and second second insert 143A, 143B may be of another shape, such as that of a rod or a wall, without departing from the scope of the invention .

According to the preferred application of the invention, the insert body 145A, 145B, 146A, 146B of each of the first and second first insert 142A, 142B and of each of the first and of the second second insert 143A, 143B, may comprise a stack of layers comprising a first layer of titanium Ti, a second layer of titanium nitride TiN and a third layer of silicon carbide WSi, said layers succeeding each other from the outside of said cylindrical shape towards the inside of this same shape.

Alternatively, the insert body 145A, 145B, 146A, 146B of each of the first and second first insert 142A, 142B and of each of the first and second second insert 143A, 143B, may comprise a single material selected from the group comprising copper Cu, Titanium Ti, tungsten W, Chromium Cr, nickel Ni, platinum Pt, palladium Pd and their alloys, such as tungsten silicide WSi, tungsten nitride WN and nickel nitride TiN.

The insert body is covered by the layer of nickel 147 on these side walls, that is to say the walls substantially perpendicular to the surface of the first insulating layer 131, 132.

• un deuxième substrat 201 dans lequel est aménagé un circuit de commande 202 de la structure semiconductrice 100, le dit circuit de commande 202 présentant, d'une manière similaire à la structure semiconductrice 100, une première et une deuxième troisième zone de connexion 222A, 222B, en correspondance au première et deuxième première zone de connexion 122A, 122B de la structure semiconductrice 100, et une première et une deuxième quatrième zone de connexion 223A, 223B en correspondance avec la première et la deuxième deuxième zone de connexion 123A, 123B de la structure semiconductrice 100, lesdites première et deuxième troisièmes zones de connexion 222A, 222B et première et deuxième quatrièmes zones de connexion 223A, 223B affleurant la surface du deuxième support 200,
• un premier et un deuxième premier plot en matériau conducteur ductile 242A, 242B en contact avec respectivement la première et la deuxième troisième zone de connexion 222A, 222B,
• un premier et un deuxième deuxième plot en matériau conducteur ductile 243A, 243B en contact avec respectivement la première et la deuxième quatrième zone de connexion 223A, 223B.

The second support 200 for its part comprises, as illustrated on figure 1 :

• a second substrate 201 in which is arranged a control circuit 202 of the semiconductor structure 100, the said control circuit 202 having, in a manner similar to the semiconductor structure 100, a first and a second third connection area 222A, 222B , in correspondence with the first and second first connection zone 122A, 122B of the semiconductor structure 100, and a first and a second fourth connection zone 223A, 223B in correspondence with the first and the second second connection zone 123A, 123B of the semiconductor structure 100, said first and second third connection areas 222A, 222B and first and second fourth connection areas 223A, 223B flush with the surface of the second support 200,
• a first and a second first pad of ductile conductive material 242A, 242B in contact with the first and the second third connection zone 222A, 222B respectively,
• a first and a second second pad made of ductile conductive material 243A, 243B in contact with the first and the second fourth connection zone 223A, 223B respectively.

In a usual configuration of the invention, the second support 201 is made of a semiconductor material other than that of the active layer 111, 112, 113. The second support 201 is thus preferably suitable for forming a control circuit and can thus be produced in a semiconductor material among the silicon Si, germanium Ge and silicon carbide SiC. In the preferred application, the second support 201 is made of silicon Si.

The control circuit 202 is a conventional control circuit, such as a CMOS technology circuit. Since such control circuits 202 are known to those skilled in the art, it is not described more precisely in this document.

The control circuit 202 has the first and the second third connection area 222A, 222B and the first and second fourth connection area 223A, 223B.

The first and second first pads of ductile conductive material 242A, 242B, and the first and second second pads of ductile conductive material 243A, 243B may comprise one of indium In, tin Sn, aluminum Al and l. one of its alloys such as lead-tin SnPb alloys and copper-silver-tin SnAgCu or aluminum-copper AlCu alloys.

As shown on the figure 1 , the semiconductor structure 100 is assembled by hybridization to the second support 200 this with the first inserts 142A, 142B embedded in the first pads of ductile conductive material 242A, 242B corresponding and the second inserts 143A, 143B embedded in the second pads of ductile conductive material 243A, 243B.

Of course, this semiconductor structure 100 and this second support 100 are described in connection with the figure 1 which shows a side sectional view of said semiconductor structure 100 and of said second support 200. Thus, if this figure is not shown, and therefore described above, only a first and second first connection zone, which 'a first and second second connection area, that a first and second first insert 142A, 142B, that a first and second second insert 143A, 143B, a semiconductor structure 100 and a second support 200 according to the invention generally include them more. Indeed, in accordance with this first embodiment, the semiconductor structure 100 comprises, on a central part, four first connection zones and as many first inserts 142A, 142B and, on a peripheral part, twelve second connection zones and as many of second inserts 143A, 143B. Of course, in order to allow assembly between the semiconductor structure 100 and the second support 200, the second support 200 has a similar configuration with a corresponding number of third connection areas 222A, 222B and fourth connection areas 223A, 223B.

It will be noted that, of course, this first embodiment is only an exemplary embodiment of the invention, and that the semiconductor structure 100 can have any number of said first and second connection zones 122A, 122B, 123A, 123B, said first and second inserts 142A, 142B, 143A, 143B this without going beyond the scope of the invention.

• fourniture d'un premier support 101, 110, 111, 112, 113, 121, 131 comportant le substrat 101 et une couche active 111, 112, 113, la couche active comprenant un semiconducteur nitruré, la région active 115 de la structure semiconductrice 100 et au moins une première et une deuxième zone de connexion de ladite région active 115 qui affleure une surface du premier support 101, 110, 111, 112, 113, 121, 131 étant aménagés dans ladite couche active 111, 112, 113, les étapes de ladite fourniture étant illustrée sur les figures 2 à 5,
• formation des premiers et des deuxièmes corps d'insert 145A, 145B, 146A, 146B en contact électrique avec respectivement la première et la deuxième zone de connexion, ladite étape de formation comprenant la formation de la couche de nickel 147 recouvrant une portion de la surface du premier support 101, 110, 111, 112, 113, 121, 131, ladite couche de nickel 147 étant disposée sur la surface support 101, 110, 111, 112, 113, 121, 131 au niveau de la région active 115 en recouvrant au moins partiellement les zones de connexion, les étapes de ladite formation étant illustrées sur les figure 5 à 7,
• gravure physico-chimique localisée de la couche active 111, 112, 113, une partie de la couche active 111, 112, 113 comprenant la région active 115 étant protégée par la couche de nickel 147, telle qu'illustrée sur la figure 8,
• gravure physico-chimique de la couche de nickel 147, la gravure étant stoppée après libération d'au moins une partie de la surface du premier support 101, 110, 111, 112, 113, 121, 131 de ladite couche de nickel 147, la partie de la surface du premier support 101, 110, 111, 112, 113, 121, 131 comprenant la surface du premier support 101, 110, 111, 112, 113, 121, 131 en dehors des première et deuxième zones de connexion, une portion restante de la couche de nickel 147 et de chacun des premier et deuxième corps d'insert 145A, 145B, 146A, 146B permettant la formation des premiers et des deuxièmes inserts 142A, 142B, 143A, 143B, telle qu'illustrée sur la figure 9,
• libération de la couche active 111, 112, 113 du premier substrat 101, ladite libération permettant de former la structure semiconductrice 100, conformément à la structure semiconductrice 100 illustrée sur la figure 1.

The semiconductor structure 100 according to the invention can be formed by means of a manufacturing process illustrated in the figures 2 to 9 and comprising the following steps:

• provision of a first support 101, 110, 111, 112, 113, 121, 131 comprising the substrate 101 and an active layer 111, 112, 113, the active layer comprising a nitrided semiconductor, the active region 115 of the semiconductor structure 100 and at least a first and a second connection zone of said active region 115 which is flush with a surface of the first support 101, 110, 111, 112, 113, 121, 131 being arranged in said active layer 111, 112, 113, the steps of said supply being illustrated on the figures 2 to 5 ,
• forming the first and second insert bodies 145A, 145B, 146A, 146B in electrical contact with the first and second connection area, respectively, said forming step comprising forming the nickel layer 147 covering a portion of the surface of the first support 101, 110, 111, 112, 113, 121, 131, said nickel layer 147 being disposed on the support surface 101, 110, 111, 112, 113, 121, 131 at the level of the active region 115 by covering at least partially the connection areas, the stages of said training being illustrated on the figure 5 to 7 ,
• localized physicochemical etching of the active layer 111, 112, 113, part of the active layer 111, 112, 113 comprising the active region 115 being protected by the nickel layer 147, as illustrated on the figure figure 8 ,
• physico-chemical etching of the nickel layer 147, the etching being stopped after release of at least part of the surface of the first support 101, 110, 111, 112, 113, 121, 131 of said nickel layer 147, the part of the surface of the first support 101, 110, 111, 112, 113, 121, 131 comprising the surface of the first support 101, 110, 111, 112 , 113, 121, 131 outside the first and second connection zones, a remaining portion of the nickel layer 147 and of each of the first and second insert bodies 145A, 145B, 146A, 146B allowing the formation of the first and second inserts 142A, 142B, 143A, 143B, as shown on the figure 9 ,
• release of the active layer 111, 112, 113 from the first substrate 101, said release making it possible to form the semiconductor structure 100, in accordance with the semiconductor structure 100 illustrated on the figure figure 1 .

Thus, during the step of localized etching of the active layer 111, 112, 113 making it possible to single out the semiconductor structure 100, it is the nickel layer 147, participating in the formation of the inserts 142A, 142B, 143A, 143B, which is used as an engraving mask. This localized etching making it possible to single out the structure is therefore aligned with the elements forming the inserts 142A, 142B, 143A, 143B and therefore the inserts 142A, 142B, 143A, 143B themselves. It is therefore possible to reduce the size of the semiconductor structure to a minimum and to have good alignment between the structure 100 and its inserts 142A, 142B, 143A, 143B allowing it to be connected to the second support 200.

• fourniture du premier substrat 101, ce premier substrat 101 pouvant être, dans le cadre de l'application préférentielle, un premier substrat 101 en silicium Si,
• dépôt de la couche d'adaptation 110 en contact du premier substrat, la couche d'adaptation 110 étant, dans le cadre de l'application préférentielle, une couche de nitrure de gallium GaN,
• dépôt de la première sous-couche 111 en contact de la couche d'adaptation 110, la première sous-couche 111 étant, dans le cadre de l'application préférentielle, une couche de nitrure de gallium GaN du premier type de conductivité,
• formation de la zone active 112, en contact de la première sous-couche 111, ladite zone active 112 comprenant, dans le cadre de l'application préférentielle, au moins un puits quantique,
• dépôt de la deuxième sous-couche active 113, en contact de la zone active 112, la deuxième sous-couche 113 étant, dans le cadre de l'application préférentielle, une couche de nitrure de gallium GaN du deuxième type de conductivité,
• dépôt de la première couche métallique 121, en contact de la deuxième sous couche active 113, la première couche métallique 121 étant, dans le cadre de l'application préférentielle, une couche de nitrure de titane TiN,
• dépôt d'une couche isolante sacrificielle 131 en contact de la première couche métallique 121, la première couche métallique 121 étant, dans le cadre de l'application préférentielle, une couche de dioxyde de silicium SiPO₂ ou de nitrure de silicium Si₂N₃,
• gravure localisée de la couche isolante sacrificielle 131 et de la première couche métallique 121 de manière à libérer une deuxième portion de la deuxième sous-couche active 113, comme illustré sur la figure 2,
• retrait de la couche isolante sacrificielle 131,
• dépôt d'une première partie de la couche isolante 132, ledit dépôt étant suivi d'une étape de planarisation de la couche isolante 132,
• formation d'une première et d'une deuxième percée 310A, 310B au travers de la couche isolante 132, la deuxième sous-couche active 113, la zone active 112, et d'une partie de la première sous-couche active 111, lesdites première et deuxième percées 310A, 310B débouchant dans la première couche active,
• dépôt du revêtement isolant 133 en contact du premier support 101, 110, 111, 112, 113, 121, 131, le revêtement isolant 133 étant notamment déposé en contact des parois latérales des première et deuxième percées 310A, 310B, ledit revêtement isolant 133 étant, dans le cadre de l'application préférentielle, de l'alumine Al₂O₃,
• gravure isotrope du revêtement isolant 133 de manière à libérer la surface du premier support 101, 110, 111, 112, 113, 121, 131 et le fond des première et deuxième percées 310A, 310B, comme illustré sur la figure 3,
• formation d'une troisième et d'une quatrième percée au travers de la couche isolante 132, lesdites troisième et quatrième percées 310A, 310B débouchant dans la première couche métallique 121,
• dépôt d'un matériau métallique de manière à remplir les première, deuxième, troisième et quatrième percées 310A, 310B, le dépôt étant suivi d'une étape de planarisation de manière à libérer la couche isolante 132 de matériau métallique, ledit matériau métallique étant, dans le cadre de l'application préférentielle, une première couche d'accroche titane Ti/nitrure de titane TiN et un cœur en cuivre Cu, comme illustré sur la figure 4,
• dépôt d'une deuxième partie de la couche isolante 132 en contact de la première partie de la couche isolante 132,
• formation d'une cinquième, sixième, septième et huitième percée dans le prolongement de respectivement les première, deuxième, troisième et quatrième percées 310A, 310B et débouchant dans ladite percée 310A, 310B, ces percées étant de dimensions inférieurs à celles des première, deuxième, troisième et quatrième percées 310A, 310B,
• dépôt d'un matériau métallique de manière à remplir les cinquième, sixième, septième et huitième percées 310A, 310B, le dépôt étant suivi d'une étape de planarisation de manière à libérer la couche isolante 132 de matériau métallique, ledit matériau métallique étant, dans le cadre de l'application préférentielle, une première couche d'accroche titane Ti/nitrure de titane TiN et un cœur en cuivre Cu, le premier support 101, 110, 111, 112, 113, 121, 131 étant ainsi formé, comme illustré sur la figure 5.

The first step of providing the first support 101, 110, 111, 112, 113, 121, 131 may comprise the following substeps:

• provision of the first substrate 101, this first substrate 101 possibly being, in the context of the preferred application, a first substrate 101 made of silicon Si,
• deposition of the matching layer 110 in contact with the first substrate, the matching layer 110 being, in the context of the preferred application, a layer of gallium nitride GaN,
• deposition of the first sublayer 111 in contact with the adaptation layer 110, the first sublayer 111 being, in the context of the preferred application, a layer of gallium nitride GaN of the first type of conductivity,
• formation of the active zone 112, in contact with the first sublayer 111, said active zone 112 comprising, in the context of the preferred application, at least one quantum well,
• deposition of the second active sublayer 113, in contact with the active zone 112, the second sublayer 113 being, in the context of the preferred application, a layer of GaN gallium nitride of the second conductivity type,
• deposition of the first metal layer 121, in contact with the second active sub-layer 113, the first metal layer 121 being, in the context of the preferred application, a layer of titanium nitride TiN,
• deposition of a sacrificial insulating layer 131 in contact with the first metal layer 121, the first metal layer 121 being, in the context of the preferred application, a layer of silicon dioxide SiPO ₂ or of silicon nitride Si ₂ N ₃ ,
• localized etching of the sacrificial insulating layer 131 and of the first metal layer 121 so as to release a second portion of the second active sub-layer 113, as illustrated in figure figure 2 ,
• removal of the sacrificial insulating layer 131,
• deposition of a first part of the insulating layer 132, said deposition being followed by a step of planarization of the insulating layer 132,
• formation of a first and a second breakthrough 310A, 310B through the insulating layer 132, the second active sub-layer 113, the active area 112, and part of the first active sub-layer 111, said first and second openings 310A, 310B opening into the first active layer,
• deposition of the insulating coating 133 in contact with the first support 101, 110, 111, 112, 113, 121, 131, the insulating coating 133 being in particular deposited in contact with the side walls of the first and second openings 310A, 310B, said insulating coating 133 being , in the context of the preferential application, alumina Al ₂ O ₃ ,
• isotropic etching of the insulating coating 133 so as to free the surface of the first support 101, 110, 111, 112, 113, 121, 131 and the bottom of the first and second openings 310A, 310B, as illustrated in figure 3 ,
• formation of a third and a fourth hole through the insulating layer 132, said third and fourth holes 310A, 310B opening into the first metal layer 121,
• deposition of a metallic material so as to fill the first, second, third and fourth openings 310A, 310B, the deposition being followed by a planarization step so as to release the insulating layer 132 of metallic material, said metallic material being, in the context of the preferred application, a first titanium Ti / titanium nitride TiN bonding layer and a copper Cu core, as illustrated on figure 4 ,
• deposition of a second part of the insulating layer 132 in contact with the first part of the insulating layer 132,
• formation of a fifth, sixth, seventh and eighth opening in the extension of the first, second, third and fourth openings, 310A, 310B, respectively, and opening into said opening 310A, 310B, these openings being of smaller dimensions than those of the first, second , third and fourth openings 310A, 310B,
• deposition of a metallic material so as to fill the fifth, sixth, seventh and eighth openings 310A, 310B, the deposition being followed by a planarization step so as to release the insulating layer 132 of metallic material, said metallic material being, in the context of the preferred application, a first titanium Ti / titanium nitride TiN bond layer and a copper core Cu, the first support 101, 110, 111, 112, 113, 121, 131 being thus formed, as illustrated on the figure 5 .

• dépôt de la deuxième couche métallique 148 en contact avec la surface du premier support 101, 110, 111, 112, 113, 121, 131, ladite deuxième couche métallique 148 étant, dans le cadre de l'application préférentielle, une couche de nitrure de titane TiN,
• gravure localisé de la deuxième couche métallique 148 de manière à libérer une partie de la surface du premier support 101, 110, 111, 112, 113, 121, 131, et ainsi former une portion de couche métallique 148 en contact de chacune des première et deuxième première zone de connexion et des première et deuxième deuxième zone de connexion,
• formation d'un masque en résine photosensible 320 en contact de la deuxième couche de métallique 148 et de la partie de la surface du premier support 101, 110, 111, 112, 113, 121, 131 libre de couche métallique 148, ledit masque en résine étant muni d'une première et deuxième première percée 322A, 322B débouchant sur les portion de deuxième couche métallique 148 en contact avec les première et deuxième première zone de connexion et d'une première et deuxième deuxième percée 323A, 323B débouchant sur les portion de deuxième couche métallique 148 en contact avec les première et deuxième deuxième zone de connexion et étant, dans le cadre de l'application préférentielle une résine polymère telle qu'un polyamide,
• dépôt d'une couche du ou des matériaux destinés à former les corps d'insert 145A, 145B, 146A, 146B en contact de la surface du masque de résine, des parois des première et deuxième première percées 322A, 322A, des parois des première et deuxième deuxième percées 323A, 323B et des portions de deuxième couche métallique 148 libre de masque en résine photosensible 220, ce dépôt consistant, dans le cadre de l'application préférentielle, à un dépôt successif de titane Ti, de nitrure de titane TiN et de carbure de silicium WSi, le dépôt étant suivi d'une étape de planarisation de manière à libérer la surface du masque en résine de la couche du ou des matériaux destinés à former les corps d'insert 145A, 145B, 146A, 146B, les premier et deuxième premier corps d'insert 145A, 145B et les premier et deuxième deuxième corps d'insert 146A, 146B étant ainsi formés, comme illustré sur la figure 6,
• suppression du masque en résine photosensible 320,
• dépôt de nickel Ni de manière à former la couche de nickel 147 en contact avec les premier et deuxième premiers corps d'insert 145A, 145B, les premier et deuxième deuxièmes corps d'insert 146A, 146B, les portions de deuxième couche métallique 148 libre de corps d'insert 145A, 145B, 146A, 146B et les parties de la surface du premier support 101, 110, 111, 112, 113, 121, 131 libre de portions de deuxième couche métallique 148,
• gravure localisé de la couche de nickel 147 de manière à ce que la partie restante de la couche de nickel 147 recouvre une portion de la surface du premier support 101, 110, 111, 112, 113, 121, 131, ladite couche de nickel 147 étant disposée sur la surface support 101, 110, 111, 112, 113, 121, 131 au niveau de la région active 115 en recouvrant au moins partiellement les zones de connexion, ladite gravure étant une gravure physico chimique, tel qu'une gravure ionique, la localisation étant fournie par l'utilisation d'un masque adapté supprimé après gravure, comme illustré sur la figure 7.

The step of forming the first and second insert bodies 145A, 145B, 146A, 146B in electrical contact with the first and the second connection zone, respectively, can comprise the sub-steps:

• deposition of the second metal layer 148 in contact with the surface of the first support 101, 110, 111, 112, 113, 121, 131, said second metal layer 148 being, in the context of the preferred application, a layer of nitride of titanium TiN,
• localized etching of the second metal layer 148 so as to release part of the surface of the first support 101, 110, 111, 112, 113, 121, 131, and thus form a portion of metal layer 148 in contact with each of the first and second first connection area and first and second second connection area,
• formation of a photosensitive resin mask 320 in contact with the second metal layer 148 and the part of the surface of the first support 101, 110, 111, 112, 113, 121, 131 free of metal layer 148, said mask in resin being provided with a first and second first breakthrough 322A, 322B opening onto the portions of the second metal layer 148 in contact with the first and second first connection zones and with a first and second second breakthrough 323A, 323B opening onto the portions of second metal layer 148 in contact with the first and second second connection zone and being, in the context of the preferred application, a polymer resin such as a polyamide,
• deposition of a layer of the material (s) intended to form the insert bodies 145A, 145B, 146A, 146B in contact with the surface of the resin mask, the walls of the first and second first openings 322A, 322A, the walls of the first and second second breakthroughs 323A, 323B and portions of a second metal layer 148 free of photosensitive resin mask 220, this deposit consisting, in the context of the preferred application, in a successive deposit of titanium Ti, of titanium nitride TiN and of silicon carbide WSi, the deposition being followed by a planarization step so as to free the surface of the resin mask from the layer of the material or materials intended to form the insert bodies 145A, 145B, 146A, 146B, the first and second first insert bodies 145A, 145B and the first and second second insert bodies 146A, 146B being thus formed, as illustrated in figure 6 ,
• removal of the photosensitive resin mask 320,
• deposition of nickel Ni so as to form the layer of nickel 147 in contact with the first and second first insert bodies 145A, 145B, the first and second second insert bodies 146A, 146B, the portions of the second free metal layer 148 insert body 145A, 145B, 146A, 146B and parts of the surface of the first support 101, 110, 111, 112, 113, 121, 131 free of portions of second metal layer 148,
• localized etching of the nickel layer 147 so that the remaining part of the nickel layer 147 covers a portion of the surface of the first support 101, 110, 111, 112, 113, 121, 131, said nickel layer 147 being disposed on the support surface 101, 110, 111, 112, 113, 121, 131 at the level of the active region 115 by at least partially covering the connection zones, said etching being a physico-chemical etching, such as an ionic etching , the localization being provided by the use of a suitable mask removed after engraving, as illustrated on figure 7 .

During the localized physicochemical etching step of the active layer 111, 112, 113 and in the context of the preferred application, the physicochemical etching can be a chlorinated plasma etching, as illustrated on figure 8 .

During the step of etching the nickel layer 147 and in the context of the preferred application, the physicochemical etching can be ionic etching.

• connexion des première et deuxième zones de connexion avec respectivement les troisième et quatrième zones de connexion 222A, 222B, 223A, 223B par insertion des premier et deuxième inserts 142A, 142B, 143A, 143B dans respectivement le premier et le deuxième plot en matériau conducteur ductile 242A, 242B, 243A, 243B.

The semiconductor structure 100 thus formed is adapted to be connected to the second support 200 in order to form the semiconductor device 10 according to the invention. Such a connection can be made by means of a hybridization assembly process comprising the following step:

• connection of the first and second connection zones with respectively the third and fourth connection zones 222A, 222B, 223A, 223B by inserting the first and second inserts 142A, 142B, 143A, 143B in respectively the first and the second pad made of ductile conductive material 242A, 242B, 243A, 243B.

The figures 10 to 12 illustrate steps of a method of manufacturing a semiconductor structure according to a second embodiment. A manufacturing method according to this second embodiment differs from a method according to the first embodiment in that the step of depositing the nickel layer 147 is prior to the formation of a photosensitive resin mask 220.

• dépôt de nickel Ni de manière à former la couche de nickel 147 en contact avec les portions de deuxième couche métallique 148, et les parties de la surface du premier support 101, 110, 111, 112, 113, 121, 131 libres de portions de deuxième couche métallique 148,
• gravure localisée de la couche de nickel 147 de manière à ce que la partie restante de la couche de nickel 147 recouvre une portion de la surface du premier support 101, 110, 111, 112, 113, 121, 131, ladite couche de nickel 147 étant disposée sur la surface support 101, 110, 111, 112, 113, 121, 131 au niveau de la région active 115 en recouvrant au moins partiellement les zones de connexion, ladite gravure étant une gravure physico chimique, tel qu'une gravure ionique, la localisation étant fournie par l'utilisation d'un masque adapté supprimé après gravure, comme illustré sur la figure 10,
• formation d'un masque en résine photosensible 320 en contact de la couche de nickel 147 et de la partie de la surface du premier support 101, 110, 111, 112, 113, 121, 131 libre de couche de nickel 147, ledit masque en résine étant muni d'une première et deuxième première percée 322A, 322B débouchant sur la couche de nickel 147 au niveau des première et deuxième première zone de connexion et d'une première et deuxième percée 323A, 323B débouchant sur la couche de nickel 147 au niveau des première et deuxième deuxième zones de connexion et étant, dans le cadre de l'application préférentielle une résine polymère telle qu'un polyamide,
• dépôt d'une couche du ou des matériaux destinés à former les corps d'insert 145A, 145B, 146A, 146B en contact de la surface du masque de résine, des parois des première et deuxième première percées 322A, 322A, des parois des première et deuxième deuxième percées 323A, 323B et des portions de couche de nickel 147 libres de masque en résine photosensible 220, ce dépôt consistant, dans le cadre de l'application préférentielle, à un dépôt successif de titane Ti, de nitrure de titane TiN et du nickel Ni, le dépôt étant suivi d'une étape de planarisation de manière à libérer la surface de du masque de résine de la couche du ou des matériaux destinés à former les corps d'insert 145A, 145B, 146A, 146B, les premier et deuxième premier corps d'insert 145A, 145B et les premier et deuxième deuxième corps d'insert 145A, 145B étant ainsi formés, comme illustré sur la figure 11,
• suppression du masque en résine photosensible 320, comme illustré sur la figure 12.

Thus with a manufacturing method according to this second embodiment, the step of forming at least a first and a second insert body 145A, 145B, 146A, 146B in electrical contact with the first and the second zone respectively. connection can comprise, after the sub-step of localized etching of the second metal layer 148 so as to free part of the surface of the first support 101, 110, 111, 112, 113, 121, 131, the following sub-steps:

• deposition of nickel Ni so as to form the nickel layer 147 in contact with the portions of the second metal layer 148, and the parts of the surface of the first support 101, 110, 111, 112, 113, 121, 131 free of portions of second metallic layer 148,
• localized etching of the nickel layer 147 so that the remaining part of the nickel layer 147 covers a portion of the surface of the first support 101, 110, 111, 112, 113, 121, 131, said nickel layer 147 being disposed on the support surface 101, 110, 111, 112, 113, 121, 131 at the level of the active region 115 by at least partially covering the connection zones, said etching being a physico-chemical etching, such as an ionic etching , the localization being provided by the use of a suitable mask removed after engraving, as illustrated on figure 10 ,
• formation of a photosensitive resin mask 320 in contact with the nickel layer 147 and the part of the surface of the first support 101, 110, 111, 112, 113, 121, 131 free of nickel layer 147, said mask in resin being provided with a first and second first breakthrough 322A, 322B opening onto the nickel layer 147 at the level of the first and second first connection zones and with a first and second breakthrough 323A, 323B opening onto the nickel layer 147 at the level of the first and second second connection zones and being, in the context of the preferred application, a polymer resin such as a polyamide,
• deposition of a layer of the material (s) intended to form the insert bodies 145A, 145B, 146A, 146B in contact with the surface of the resin mask, the walls of the first and second first openings 322A, 322A, the walls of the first and second second breakthroughs 323A, 323B and portions of nickel layer 147 free of photosensitive resin mask 220, this deposit consisting, in the context of the preferred application, in a successive deposit of titanium Ti, of titanium nitride TiN and nickel Ni, the deposition being followed by a planarization step so as to free the surface of the resin mask from the layer of the material or materials intended to form the insert bodies 145A, 145B, 146A, 146B, the first and second first insert body 145A, 145B and the first and second second insert body 145A, 145B being so formed, as shown in FIG. figure 11 ,
• removal of the photosensitive resin mask 320, as shown in the figure 12 .

It will be noted that, in accordance with the preferred application described above, so as to limit the part of each of the insert bodies 145A, 145B, 146A, 146B etched during the localized physicochemical etching steps of the active layer 111 , 112, 113, and physico-chemical etching of the nickel layer 147, each of the insert bodies 145A, 145B, 146A, 146B preferably comprises nickel Ni.

Thus, the insert bodies 145A, 145B, 146A, 146B are little or not etched during the localized physicochemical etching step of the active layer 111, 112, 113 and exhibit anisotropic etching during the physical etching step. -chemical of the nickel layer 147. This anisotropic etching leads, as shown on the figure 12 , an etching of the part of the insert bodies 145A, 145B, 146A, 146B at the level of the base and the top of the cylindrical shape, the part of the nickel layer 147, protected by said base, then forming the base of the insert 142A, 142B, 143A, 143B formed after said etching.

• le corps d'insert 145A, 145B présente une forme de cylindre creux dépourvu de base,
• la couche de nickel 147 forme la base du corps d'insert 145A, 145B, 146A, 146B en contact avec la portion de deuxième couche métallique 148 correspondante, ladite couche de nickel ne revêtant pas les parois latérale du corps d'insert 145A, 145B, 146A, 146B.

In accordance with this possibility, it will be noted that a semiconductor structure 100 according to this second embodiment differs from a semiconductor structure according to the first in that for each of the first and second first insert 142A, 142B, 143A, 143B:

• the insert body 145A, 145B has the shape of a hollow cylinder without a base,
• the nickel layer 147 forms the base of the insert body 145A, 145B, 146A, 146B in contact with the portion of the second metal layer 148 corresponding, said layer of nickel not coating the side walls of the insert body 145A, 145B, 146A, 146B.

Claims (10)

1. Method for fabrication of a semiconducting structure (100) intended to be connected by hybridisation to a second support (200), the method for fabrication including the following steps:

   - supply a first support (101, 110, 111, 112, 113, 121, 131) that comprises a substrate (101) and at least one active layer (111, 112, 113), said active layer (111, 112, 113) comprising at least one nitrided semiconducting material, at least one active region (115) of said semiconducting structure (100) and at least one first and one second connection zone of said active region (115) flush with a surface of the first support (101, 110, 111, 112, 113, 121, 131) being arranged in said active layer (111, 112, 113),

   - formation of at least one first and one second insert body (145A, 145B, 146A, 146B) in electrical contact with the first and second connection zones respectively, said formation step comprising formation of a nickel layer (147) covering a portion of the surface of the first support (101, 110, 111, 112, 113, 121, 131), said nickel layer (147) being arranged on the support surface (101, 110, 111, 112, 113, 121, 131) at the active region (115), at least partially covering the first and second connection zones,

   - localised physico-chemical etching of the active layer (111, 112, 113), the localisation of the etching being provided by protecting part of the active layer (111, 112, 113) comprising the active region (115) by the nickel layer (147),

   - physico-chemical etching of the nickel layer (147), the etching being stopped after the release of at least part of the surface of the first support (101, 110, 111, 112, 113, 121, 131) of said nickel layer (147), the part of the surface of the first support (101, 110, 111, 112, 113, 121, 131) including the surface of the first support (101, 110, 111, 112, 113, 121, 131) outside the first and second connection zones, a remaining portion of the nickel layer (147) and each of the first and second insert bodies (145A, 145B, 146A, 146B) being used for formation of a first and a second insert (142A, 142B, 143A, 143B),

   - release of the active layer (111, 112, 113) from the first substrate (101), said release enabling formation of the semiconducting structure (100).
2. The method of fabrication according to claim 1, wherein the step for formation of the first and second inserts (142A, 142B, 143A, 143B) includes the following sub-steps:

   - formation of at least a first and a second portion of the metallic layer (148) covering the first and second connection zones respectively,

   - formation of a first and a second insert body (145A, 145B, 146A, 146B) in contact with the first and the second metallic layer portions (148), respectively,

   - deposition of the nickel layer (147) in contact with the support surface (101, 110, 111, 112, 113, 121, 131) of the first and second portions of metallic layer (148) and the first and second insert bodies (145A, 145B, 146A, 146B), the nickel layer (147) forming a coating of the first and second insert bodies (145A, 145B, 146A, 146B).
3. The method of fabrication according to claim 1, wherein the step for formation of the first and second insert bodies (145A, 145B, 146A, 146B) includes the following sub-steps:

   - formation of at least a first and a second portion of the metallic layer (148) covering the first and second connection zones respectively,

   - deposition of the nickel layer (147) covering the support surface (101, 110, 111, 112, 113, 121, 131) that is free of the first and second metallic layer portions (148) and said first and second metallic layer portions (148),

   - formation of a first and a second insert body (145A, 145B, 146A, 146B) in contact with the nickel layer (147) at the first and second metallic layer portions (148), respectively,
4. The method of fabrication according to claim 3, wherein the first and second insert bodies (145A, 145B, 146A, 146B) comprise nickel:
5. The method of fabrication according to any one of claims 1 to 4, wherein the first and second insert bodies (145A, 145B, 146A, 146B) include a carbide from among silicon carbide and tungsten carbide.
6. The method of fabrication according to any one of claims 1 to 5, wherein the active layer (111, 112, 113) comprises gallium nitride.
7. The method of fabrication according to any one of claims 1 to 6, wherein the active part (115) of the semiconducting structure (100) is a diode, the first and second connection zones corresponding to the metallic contacts (122A, 122B, 123A, 123B) of the anode and cathode of said diode, respectively.
8. The method of fabrication of a semiconducting structure (100) according to claim 7, wherein the active layer comprises:

   - a first active sub-layer (111) with a first type of conductivity, the second connection zone being a connection zone of said first active sub-layer (111),

   - an active zone (112) adapted to emit light, said active zone (112) preferably comprising at least one quantum well,

   - a second active sub-layer (113) with a second type of conductivity opposite the first type of conductivity, the first connection zone being a connection zone of said second active sub-layer (113),
9. Method of fabrication of a semiconducting device (10) comprising a semiconducting structure (100), the method including the following steps:

   - formation of a semiconducting structure (100) using a fabrication method according to any one of claims 1 to 8,

   - supply of a second support (201) comprising at least a third and a fourth connection zone (222A, 222B, 223A, 223B) corresponding to the first and second connection zones of the semiconducting structure (100), and a first and second bump made of a ductile conducting material (242A, 242B, 243A, 243B) in electrical contact with the third and the fourth connection zones (222A, 222B, 223A, 223B) respectively,

   - connection of the first and second connection zones with the third and fourth connection zones (222A, 222B, 223A, 223B) respectively by insertion of the first and second inserts (142A, 142B, 143A, 143B) in the first and second bumps made of a ductile conducting material (242A, 242B, 243A, 243B), respectively.
10. The method of fabrication of a device according to claim 9, wherein the semiconducting structure (100) is a light emitting diode, the second support (201) comprising a control circuit (202) adapted to supply and control said light emitting diode.

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