EP3649665A1 - Operation of a direct current circuit breaking device - Google Patents
Operation of a direct current circuit breaking deviceInfo
- Publication number
- EP3649665A1 EP3649665A1 EP17735530.2A EP17735530A EP3649665A1 EP 3649665 A1 EP3649665 A1 EP 3649665A1 EP 17735530 A EP17735530 A EP 17735530A EP 3649665 A1 EP3649665 A1 EP 3649665A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- breaking device
- circuit breaking
- current
- blocking
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000903 blocking effect Effects 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000004590 computer program Methods 0.000 claims abstract description 15
- 238000000926 separation method Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 description 16
- 230000008901 benefit Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000007704 transition Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000000116 mitigating effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- IVQOFBKHQCTVQV-UHFFFAOYSA-N 2-hydroxy-2,2-diphenylacetic acid 2-(diethylamino)ethyl ester Chemical compound C=1C=CC=CC=1C(O)(C(=O)OCCN(CC)CC)C1=CC=CC=C1 IVQOFBKHQCTVQV-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005404 monopole Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H9/00—Details of switching devices, not covered by groups H01H1/00 - H01H7/00
- H01H9/54—Circuit arrangements not adapted to a particular application of the switching device and for which no provision exists elsewhere
- H01H9/541—Contacts shunted by semiconductor devices
- H01H9/542—Contacts shunted by static switch means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H33/00—High-tension or heavy-current switches with arc-extinguishing or arc-preventing means
- H01H33/02—Details
- H01H33/59—Circuit arrangements not adapted to a particular application of the switch and not otherwise provided for, e.g. for ensuring operation of the switch at a predetermined point in the ac cycle
- H01H33/596—Circuit arrangements not adapted to a particular application of the switch and not otherwise provided for, e.g. for ensuring operation of the switch at a predetermined point in the ac cycle for interrupting dc
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H9/00—Details of switching devices, not covered by groups H01H1/00 - H01H7/00
- H01H9/54—Circuit arrangements not adapted to a particular application of the switching device and for which no provision exists elsewhere
- H01H9/541—Contacts shunted by semiconductor devices
- H01H9/542—Contacts shunted by static switch means
- H01H2009/543—Contacts shunted by static switch means third parallel branch comprising an energy absorber, e.g. MOV, PTC, Zener
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H9/00—Details of switching devices, not covered by groups H01H1/00 - H01H7/00
- H01H9/54—Circuit arrangements not adapted to a particular application of the switching device and for which no provision exists elsewhere
- H01H9/541—Contacts shunted by semiconductor devices
- H01H9/542—Contacts shunted by static switch means
- H01H2009/544—Contacts shunted by static switch means the static switching means being an insulated gate bipolar transistor, e.g. IGBT, Darlington configuration of FET and bipolar transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H9/00—Details of switching devices, not covered by groups H01H1/00 - H01H7/00
- H01H9/30—Means for extinguishing or preventing arc between current-carrying parts
Definitions
- the invention generally related to the interruption of currents in direct current power tran smission systems. More particularly, the invention relates to a direct current circuit breaking device to be connected in series with a power line as well as to a method and computer program product for controlling the direct current circuit breaking device.
- High Voltage Direct Current (HVDC) systems are known to be used in different power transmission situations, such as for tran smitting power over long distances using power lines that may be over-headlines or cables.
- a direct current circuit breaker may then comprise a number of parallel branches, where one branch comprises a mechanical disconnector in series with a load commutation switch, another branch comprises a main breaker made up of a number of series-connected power semiconductor switches and a further branch comprises at least one non- linear resistor often in the form of a surge arrester or varistor.
- the DC breaker In case of a fault in the tran smission line, the DC breaker is operated t clear the fault. This operation involves opening or blocking the main breaker in order to force the fault current to flow through the surge arrester branch .
- the arrester branch dissipates energy and gradually brings the fault current to zero.
- Transition of the fault current from the main breaker to the surge arrester branch is carried out in the order of few microseconds through the blocking of the main breaker. Due to high value of the fault current and small tran sition time, the rate of change of current (di/ dt) through the surge arrester branch is high .
- the circuit breaker may because of this be exposed to an exceedingly high transient voltage.
- the present invention is concerned with this problem .
- One object of the invention is therefore to provide an improvement in the mitigating of overvoltages experienced by a direct current circuit breaking device.
- This object is according to a first aspect achieved by a direct current circuit breaking device to be connected in series with a power line and
- each current diverting module comprising a non-linear resistor in parallel with a corresponding power switch, where the power switches together form a main operable to be opened for diverting a current through the main breaker to the non-linear resistors,
- the power switches being controllable, upon the circuit breaking device being set to interrupt a current through the power line, to be blocked according to a sequential blocking scheme.
- This object is according to a second aspect also achieved by a method of controlling a direct current circuit breaking device when interrupting a current in a power line connected in series with the circuit breaking device, where the circuit breaking device comprises a branch comprising a number of series-connected current diverting blocks, where each current diverting block comprises a non-linear resistor in parallel with a
- a computer program product for controlling a direct current circuit breaking device when interrupting currents in a power line connected in series with the circuit breaking device, where the circuit breaking device comprises a branch comprising a number of series-connected current diverting blocks, where each current diverting block comprises a non-linear resistor in parallel with a corresponding power switch and the power switches together form a main breaker,
- the computer program product comprising a data carrier with computer program code configured to :
- the invention according to the above-mentioned aspects has a number of advantages. It reduces overvoltages experienced in the circuit breaking device when currents are diverted to the non-linear resistors. Thereby elements with lower ratings may also be used. This is furthermore obtained without any additional components. It may be implemented only using some modified control software.
- fig. 1 schematically shows a simple HVDC system comprising a power transmission medium in the form of a power line or cable connected to a DC circuit breaking device
- fig. 2 schematically shows a multi-terminal HVDC system comprising a number of power tran smission lines or cables, each connected to a DC circuit breaking device,
- fig. 3 schematically shows the structure of a DC circuit breaking device
- fig. 4 schematically shows the voltage across a disconnector of the DC circuit breaking device during conventional circuit breaking activity
- fig. 5 schematically shows a flow chart of a number of method steps performed by a control unit of the DC circuit breaking device when performing a modified circuit breaking activity according to the invention
- fig. 6 schematically shows the voltage across the disconnector of the DC circuit breaking device when the modified circuit breaking activity is performed
- fig. 7 schematically shows a computer program product computer program medium comprising computer program code for implementing the adjusted circuit breaking activity.
- Fig. 1 shows one variation of a high voltage direct current (HVDC) power transmission system .
- the system in fig. 1 is a point-to-point system for connection between two Alternating Current (AC) power tran smission systems.
- the HVDC system includes a first and a second converter station 10 and 12, where the first converter station 10 includes a first transformer Tl.
- the first converter station 10 also comprises a first converter 14 for conversion between AC and DC, which converter therefore comprises an AC side connected to the transformer Tl and a DC side connected to a first reactor LI.
- the first transformer Tl thus connects the first converter 14 to the first AC power tran smission system (not shown) .
- the first converter 14 is connected to a second converter 16 of a second converter station 12 via a
- DC tran smission medium 18 which DC transmission medium may be a power line 18 such as an overhead line or a cable.
- the first converter 10 may here be connected to a first end of the tran smission medium via a first reactor LI and the second converter may be connected to a second end of the transmission medium 18 via a second reactor L2.
- the second converter 16 also converts between AC and DC and may be an inverter.
- the second converter station 12 may also include a second transformer T2, which connects the second converter 16 to the second AC power transmission system (not shown) .
- the converters 14 and 16 may be any type of converters, such as line- commutated Current Source Converters (CSC) or forced commutated Voltage Source Converters (VSC) .
- the converters may more particularly comprise a number of converter valves.
- a voltage source converter may be a two-level voltage source converter or a multi-level voltage source converter employing submodules. In series with the tran smission medium there is finally also a Direct Current (DC) circuit breaking device 20 .
- DC Direct Current
- the HVDC system in fig. 1 is a monopole system . It should however be realized that the system may also be a bipole system .
- Fig. 2 shows another type of HVDC system .
- the system is here a multi- terminal HVDC system, such as an HVDC system comprising a number of converters converting between AC and DC.
- Each converter comprises an AC side and a DC side, where the DC side of a third converter 24 is connected to the DC side of a fourth converter 26 via a power transmission medium in the form of a power line that may be a second overhead line or cable 32, the DC side of a fifth converter 28 is connected to the DC side of a sixth converter 30 via a third DC line or cable 34.
- Fig. 3 shows a first embodiment of the DC circuit breaking device 20 .
- the DC circuit breaking device 20 may comprise two parallel branches. There is a first branch comprising a mechanical disconnector, which may be a so-called ultrafast disconnector UFD, in series with a load commutation switch LCS that is a fast electronic switch . There is also a second branch with a number of series-connected current diverting modules, where each current diverting module comprises a non-linear resistor in parallel with a corresponding electronic power switch . The totality of power switches may together form a main breaker MB, while the totality of non-linear resistors may be seen as forming a surge arrester branch . There is in the example in fig.
- a first current diverting module comprising a first surge arrester SA1 in parallel with a first power switch S I, a second current diverting module comprising a second surge arrester SA2 in parallel with a second power switch S2, a third current diverting module comprising a third surge arrester SA3 in parallel with a third power switch S3 and finally a fourth current diverting module comprising a fourth surge arrester SA4 in parallel with a fourth power switch S4.
- the main breaker MB is furthermore operable to be opened for diverting a current through the main breaker MB to the non-linear resistors, i.e. to the surge arrester branch .
- Each power switch S I, S2, S3 or S4 may be realized in the form of a switching element together with an anti-parallel freewheeling unidirectional conduction element, which may be a diode.
- the power switches are each realized with switching elements that are controllable to be turned on and off via control terminals, such as gates or bases.
- the switching elements are realized as IGBTs (In sulated Gate Bipolar Tran sistor) and the unidirectional conduction elements as diodes.
- the main breaker MB shown in fig. 3 is only an example of one type of circuit breaker device only capable of performing blocking in one current direction . However, it should be realized that it is possible to modify the main breaker MB so that it can block current in two direction s. The same is of course also true for the load commutation switch LCS.
- control unit 40 which is shown as controlling the ultra fast disconnector UFD, the load commutation switch LCS as well as gates of the individual power electronic switches S I, S2, S3 and S4.
- the control unit 40 may be realized in the form of as computer or processing circuitry, such as a Field-Programmable Gate Array (FPGA) .
- FPGA Field-Programmable Gate Array
- circuit breaking device 20 being connected in series with a power line is to interrupt the current in the power line and to possibly also obtain a mechanical separation from the power line.
- the DC circuit breaking device 20 is operated to interrupt the fault current through the power line and to clear the fault.
- the operation involves forcing a fault current running through the main breaker MB to be diverted to the surge arrester branch, which typically involves blocking of the main breaker MB. Once the main breaker MB has been blocked, the fault current is forced to flow through the surge arrester branch . This operation is typically performed after the load commutation switch LCS has been blocked and the mechanical disconnector UFD has been opened.
- Transition of the fault current from the main breaker MB to the surge arrester branch may take place quickly, such as in the order of a few microseconds. Due to the value of the fault current and small tran sition time, the rate of change of current (di/ dt) through the surge arrester branch is high .
- the stray parameters of the direct current circuit breaking device due to connection wires, current sen sors, arrester mechanical arrangement and the physical property of the arrester, may lead to a voltage above the designed arrester protective voltage due to high di/ dt. This high voltage developed across the surge arrester branch is seen by the other elements of the DC circuit breaking device 20 , i.e. by the mechanical disconnector UFD, the load commutation switch LCS and the main breaker MB. These elements thus have to withstand the additional voltage over and above the arrester protection voltage.
- the voltage distribution across each element in the first branch i.e. the branch comprising the mechanical disconnector UFD and the load commutation switch LCS, during initial transient, mainly depends on the capacitance across it.
- the net capacitance across the LCS switch in blocked condition is significantly higher than the net capacitance across the UFD in open position . Therefore, the initial peak voltage developed by the arrester branch, along with the stray parameters in other branches, is seen by the UFD during the initial transient and the voltage across the LCS is negligible or is limited to a voltage magnitude by the arrester across it.
- the voltage across the first branch over time is shown in fig. 4 for a
- the main breaker MB i.e. the totality of power switches may be set to take the system overrating for which the surge arresters have been designed, i.e. the arrestor protection voltage.
- the power switches may as an example be designed for an overrating of 40 %. They may thus as an example be designed for a voltage that is 1.4 times the operational steady-state voltage Vss. It can here be seen that the first branch and therefore also the mechanical disconnector UFD may experience a voltage well above the protection voltage Vp .
- the various elements, such as the UFD are designed to withstand the arrester protection voltage Vp with a certain margin .
- the method which is a modified circuit breaking activity, is possible to perform due to the modular structure of the used main breaker MB.
- the operation will now be described with reference being made also to fig.
- a current is initially, in steady state fault free operation of the system, running through the first branch comprising the mechanical disconnector UFD and load commutation switch LCS.
- the first branch is thereby the normal current path .
- Both the mechanical disconnector UFD and the load commutation switch LCS are thereby closed.
- the main breaker MB is closed.
- the control unit 40 first open s the load commutation switch LCS, step 42, in order to commutate the current over to the main breaker MB. Once the current has been commutated over to the main breaker MB, the control unit 40 then open s the mechanical disconnector UFD, step 44. Thereby the main current path has been disconnected and the fault current in stead runs through the main breaker MB.
- the main breaker MB is to be opened in order to commutate the fault current over to the surge arrester branch .
- This is done through the control unit 40 turning off or blocking the power switches S I, S2, S3 and S4 of the main breaker MB according to a sequential blocking scheme, step 46.
- the power switches are thus blocked according to a blocking sequence.
- the sequential blocking scheme defines a sequence of blocking in stances at which the power switches are blocked. Thereby at least some of the power switches are being blocked at different points in time.
- Fig. 6 shows the voltage across the first branch and thus also the voltage experienced by the disconnector UFD, during the operation of the main breaker MB according to the sequential blocking scheme.
- the voltage levels are here the same as those shown in fig. 4.
- the operation of seven power switches is shown .
- Fig. 6 thus exemplifies the operation of a circuit breaking device
- the power switches may be set to be blocked sequentially, i.e. in a sequence of blocking instances. In the example in fig. 6, only one power switch is blocked at each blocking instance and the blocking in stances are separated by the same blocking in stance separation time or time delay. . It can be seen that the overvoltage experienced by the circuit breaking device 20 , here exemplified by the mechanical disconnector UFD, is significantly reduced as compared with the case when all power switches were blocked simultaneously, see fig. 4. It is thereby possible to use elements with lower ratings or perhap s increase the period between scheduled maintenance. This is especially advantageous with respect of the ultrafast disconnector UFD, which may be the most sen sitive element of the circuit breaking device 20 .
- the power switches of the main breaker MB may thus be blocked successively, one, two or more at a time, perhaps with a delay, so that the power switches of the current diverting blocks conduct in group s of one, two or more after each other.
- One power switch may thus be controlled to be blocked at each blocking instance.
- the voltage withstand levels of these power switches may need to be comparable with each other.
- the voltage developed by each of the current diverting blocks are a fraction of the protection voltage Vp . Therefore, the voltage across the UFD builds to the protection voltage in steps- with a finite delay between each step .
- the fault current is limited by blocking the main breaker MB and diverting it through the arrester. Since all of the arresters are forced to conduct an arrester protection voltage develop s across each module. Therefore, across the UFD the voltage seen will be the superposition of the arrester protection voltage and ringing voltage due to parasitics.
- the proposed scheme takes advantage of this fact.
- the main breaker is made up of a series connection of power switches in current diverting blocks
- the block structure provides the flexibility to connect several such blocks in series to develop a main breaker with desired voltage level.
- Each block then receives a separate control command to block or de-block the corresponding power switch .
- the proposed method takes advantage of this fact. Therefore, when the main breaker MB as a unit has to be blocked, a separate control command is sent to all the power semiconductor switches of the main breaker MB connected in series.
- the rate of rise of voltage (dv/ dt) and the peak voltage across the UFD is controlled by sequentially blocking the main breaker semiconductor switches.
- the blocking in stance separation time or delay between blocking of each main breaker power switch may be so chosen to avoid a large overshoot and to achieve the desired rate of rise of voltage across the element, such as the UFD.
- the delay may be set such that the amplitude of the ringing experienced by the element is damped to an acceptable level,.
- the delay may more particularly be set to allow a sufficient degree of the ringing caused by the parasitics of the circuit breaking device to be damped.
- amplitude of the ringing may for instance be set so that the amplitude of the ringing is damped to a suitable level where it settles across the element, like 50 , 40 , 30 , 20 or 10 % of the initial ringing amplitude before a following blocking instance takes place.
- a suitable level where it settles across the element, like 50 , 40 , 30 , 20 or 10 % of the initial ringing amplitude before a following blocking instance takes place.
- the duration of the sequence is not really time critical as long as it can be completed within a maximum allowed time for completion of the circuit breaking operation after the detection of a fault, which as an example may be 5 ms.
- the maximum allowed time may then also have to include the opening times of the mechanical disconnector UFD and the load
- the blocking scheme it is possible that more than one power switch is being blocked at the same time. It is thus possible that more than one power switch is blocked at a blocking instance. It is as an example possible that two or even more power switches are blocked at a blocking instance. It is more particularly possible that power switches of current diverting modules that together make up a voltage corresponding to the operational voltage Vss are being blocked at the same blocking in stance. This may in turn be followed by singly blocked power switches.
- the delay between blocking instances may also depend on the number of power switches being blocked.
- the delay following a blocking in stance may as an example generally be set as n times the delay of a single blocked power switch, where n is the number of simultaneously blocked power switches.
- one or more of the blocking instances at the end of the sequence each only involves the blocking of a single power switch . It is for in stance possible that the last blocking instance in the sequence only blocks one power switch . The advantage of this can be clearly seen in fig. 6. The ringing at the last blocking of the sequence will, if the ringing of previous blocking instances have been sufficiently damped, have a low amplitude and thereby the circuit breaking device will essentially only have to be dimen sioned for a voltage comprising the rated overvoltage Vp together with the amplitude of the ringing of a singly blocked power switch .
- the actual power switch selected for being blocked at a certain blocking in stance is not important.
- the power switches all perform the same function . It may therefore be wise if the order in which the power switches are selected to be blocked in a blocking sequence is changed from time to time.
- the power switches may thus be controlled to be blocked in a first sequence for a first interrupting of a current through the power line and in a second sequence for a second interrupting of a current through the power line, where the second sequence is different from the first sequence.
- the order in which power switches are selected in the first sequence may thus be different than the order in which the same power switches are selected in the second following blocking sequence.
- the invention has a number of advantages. It mitigates the overvoltages experienced in the circuit breaking device when currents are diverted to the non-linear resistors. This is furthermore obtained without any additional components. It may be implemented only using some modified control software.
- a control unit may be realized in the form of discrete components, such as one or more FPGAs. However, it may also be implemented in the form of one or more processors with accompanying program memories comprising computer program code that performs the desired control functionality when being run on a processor.
- a computer program product carrying such code can be provided as a data carrier such as one or more CD ROM discs or one or more memory sticks carrying the computer program code, which performs the above-described control functionality.
- One such data carrier in the form of a CD ROM disk 48 carrying computer program code 50 is shown in fig. 7. While the invention has been described in connection with what is presently considered to be most practical and preferred embodiments, it is to be understood that the invention is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various
- circuit breaking device may be provided without the first branch .
- the first branch with mechanical disconnector and optional load commutation switch may thus be omitted.
- the main breaker is used for conducting current in steady state fault free operation . Therefore the invention is only to be limited by the following claims.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Driving Mechanisms And Operating Circuits Of Arc-Extinguishing High-Tension Switches (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP2017/066818 WO2019007505A1 (en) | 2017-07-05 | 2017-07-05 | Operation of a direct current circuit breaking device |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3649665A1 true EP3649665A1 (en) | 2020-05-13 |
EP3649665B1 EP3649665B1 (en) | 2021-09-01 |
Family
ID=59285234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP17735530.2A Active EP3649665B1 (en) | 2017-07-05 | 2017-07-05 | Operation of a direct current circuit breaking device |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP3649665B1 (en) |
CN (1) | CN110800078B (en) |
WO (1) | WO2019007505A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ES2861157B2 (en) * | 2021-03-15 | 2022-03-21 | Univ Madrid Politecnica | PROTECTION SYSTEM FOR DIRECT CURRENT NETWORKS |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101342333B1 (en) * | 2009-10-27 | 2013-12-16 | 에이비비 테크놀로지 아게 | An hvdc breaker and control apparatus for controlling an hvdc breaker |
WO2011141054A1 (en) * | 2010-05-11 | 2011-11-17 | Abb Technology Ag | A high voltage dc breaker apparatus |
CN105531893B (en) * | 2013-12-11 | 2018-06-01 | 三菱电机株式会社 | Direct current interruption device |
US10243357B2 (en) * | 2013-12-20 | 2019-03-26 | Siemens Aktiengesellschaft | Apparatus and method for switching a direct current |
CN103928913B (en) * | 2014-03-31 | 2016-05-25 | 华中科技大学 | A kind of high voltage DC breaker based on rapid repulsion mechanism and insulating transformer |
CN104158171B (en) * | 2014-08-18 | 2017-06-06 | 国家电网公司 | A kind of high-voltage direct-current breaker topology circuit |
CN104901269B (en) * | 2015-06-02 | 2018-05-01 | 梦网荣信科技集团股份有限公司 | All-solid-state direct current breaker and control method thereof |
CN106253243B (en) * | 2016-08-09 | 2018-09-28 | 南京南瑞继保电气有限公司 | A kind of shutting-brake control method of high voltage DC breaker |
-
2017
- 2017-07-05 CN CN201780092556.XA patent/CN110800078B/en active Active
- 2017-07-05 WO PCT/EP2017/066818 patent/WO2019007505A1/en active Search and Examination
- 2017-07-05 EP EP17735530.2A patent/EP3649665B1/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN110800078B (en) | 2021-04-09 |
WO2019007505A1 (en) | 2019-01-10 |
EP3649665B1 (en) | 2021-09-01 |
CN110800078A (en) | 2020-02-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Li et al. | Continuous operation of radial multiterminal HVDC systems under DC fault | |
US10389262B2 (en) | Device for temporarily taking over electrical current from an energy transfer or distribution device, when needed | |
US9208979B2 (en) | High voltage DC breaker apparatus | |
US8687389B2 (en) | Apparatus having a converter | |
CN109586327B (en) | Energy consumption device and control method thereof | |
EP3001552A1 (en) | Voltage source converter and control thereof | |
US6075684A (en) | Method and arrangement for direct current circuit interruption | |
CN113872425A (en) | Control of voltage source converter | |
EP3353881B1 (en) | A multilevel converter with a chopper circuit | |
EP3008822B1 (en) | Semiconductor switching circuit | |
WO2014177874A2 (en) | Apparatus and method for controlling a dc current | |
EP3424137B1 (en) | Fault protection for voltage source converters | |
Peng et al. | A protection scheme against DC faults VSC based DC systems with bus capacitors | |
Berg et al. | Analytical design considerations for MVDC solid-state circuit breakers | |
Li et al. | A DC fault handling method of the MMC-based DC system | |
Mackey et al. | Progressive switching of hybrid DC circuit breakers for faster fault isolation | |
US20180115253A1 (en) | Improvements in or relating to electrical assemblies | |
US11239657B2 (en) | AC switching arrangement | |
Sander et al. | A novel current-injection based design for HVDC circuit breakers | |
EP3649665B1 (en) | Operation of a direct current circuit breaking device | |
CN115280448A (en) | Fault current limiter circuit breaker | |
JP2005295796A (en) | Power generator having incorporated electric power switch | |
Palav et al. | On using the solid state breaker in distribution systems | |
Xie et al. | Improved MVDC breaker operation by active fault current sharing (FCS) of existing power converters for shipboard applications | |
CN111987705A (en) | Direct current energy consumption system, electric power system and energy consumption method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: UNKNOWN |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20191230 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
AX | Request for extension of the european patent |
Extension state: BA ME |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) | ||
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01H 9/54 20060101AFI20210120BHEP Ipc: H01H 9/30 20060101ALI20210120BHEP Ipc: H01H 33/59 20060101ALI20210120BHEP |
|
INTG | Intention to grant announced |
Effective date: 20210208 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: ABB POWER GRIDS SWITZERLAND AG |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE PATENT HAS BEEN GRANTED |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP Ref country code: AT Ref legal event code: REF Ref document number: 1427095 Country of ref document: AT Kind code of ref document: T Effective date: 20210915 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 602017045170 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D |
|
REG | Reference to a national code |
Ref country code: LT Ref legal event code: MG9D |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: MP Effective date: 20210901 |
|
RAP4 | Party data changed (patent owner data changed or rights of a patent transferred) |
Owner name: HITACHI ENERGY SWITZERLAND AG |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: RS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: HR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: BG Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20211201 Ref country code: LT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: NO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20211201 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: MK05 Ref document number: 1427095 Country of ref document: AT Kind code of ref document: T Effective date: 20210901 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: PL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: LV Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20211202 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20220101 Ref country code: SM Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: RO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20220103 Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: AL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 602017045170 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R081 Ref document number: 602017045170 Country of ref document: DE Owner name: HITACHI ENERGY SWITZERLAND AG, CH Free format text: FORMER OWNER: ABB POWER GRIDS SWITZERLAND AG, BADEN, CH Ref country code: DE Ref legal event code: R081 Ref document number: 602017045170 Country of ref document: DE Owner name: HITACHI ENERGY LTD, CH Free format text: FORMER OWNER: ABB POWER GRIDS SWITZERLAND AG, BADEN, CH |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 |
|
26N | No opposition filed |
Effective date: 20220602 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
REG | Reference to a national code |
Ref country code: BE Ref legal event code: MM Effective date: 20220731 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20220705 Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20220731 Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20220731 Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20220731 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20220731 |
|
P01 | Opt-out of the competence of the unified patent court (upc) registered |
Effective date: 20230527 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20220705 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R082 Ref document number: 602017045170 Country of ref document: DE Representative=s name: DENNEMEYER & ASSOCIATES S.A., DE Ref country code: DE Ref legal event code: R081 Ref document number: 602017045170 Country of ref document: DE Owner name: HITACHI ENERGY LTD, CH Free format text: FORMER OWNER: HITACHI ENERGY SWITZERLAND AG, BADEN, CH |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: HU Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO Effective date: 20170705 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E Free format text: REGISTERED BETWEEN 20240718 AND 20240724 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210901 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20240719 Year of fee payment: 8 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20240725 Year of fee payment: 8 |