EP3635781A1 - Module convertisseur de puissance et procédé de fabrication de ce dernier - Google Patents
Module convertisseur de puissance et procédé de fabrication de ce dernierInfo
- Publication number
- EP3635781A1 EP3635781A1 EP18729647.0A EP18729647A EP3635781A1 EP 3635781 A1 EP3635781 A1 EP 3635781A1 EP 18729647 A EP18729647 A EP 18729647A EP 3635781 A1 EP3635781 A1 EP 3635781A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- power
- semiconductor module
- power semiconductor
- power switches
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Definitions
- the invention relates to a power semiconductor module, in particular a drive converter module for operating a vehicle drive, and to a production method for such a power semiconductor module and a vehicle having such a power semiconductor module.
- converters can be used to convert types of current into one another or to change characteristic parameters such as frequency or voltage.
- Special types of power converters, such as rectifiers or inverters, can convert an available AC voltage into a DC voltage or a DC voltage provided into an AC voltage.
- circuits play an important role especially in the operation of electrical machines, such as three-phase motors, and in energy storage technology. They are therefore of particular importance in the field of electromobility, where electric power is provided by an energy storage as DC and used as AC to drive a vehicle, or where in the so-called recuperation of the drive serves as a generator for alternating electrical current, which is rectified , so that the energy storage can be recharged with DC.
- a first aspect of the invention relates to a power semiconductor module, preferably a drive converter module for operating a vehicle drive, in particular a motor vehicle drive.
- the power semiconductor module has an electrically insulating, planar carrier substrate with a first and a second main area and a bridge circuit with a plurality of circuit breakers, in particular power transistors.
- a first subset of one or more of the power switches is part of a first current-conducting current branch of the power semiconductor module, which runs between a first DC voltage connection and an AC voltage connection of the power semiconductor module.
- a second subset of one or more of the power switches is part of a second current-conducting current branch of the power semiconductor module, which extends between a second direct-voltage terminal opposite to the first direct-voltage terminal and the alternating-voltage terminal of the power semiconductor module.
- the first current branch and the second current branch are electrically connected to the AC voltage terminal in such a way that together they form a half-bridge connected in parallel with the DC voltage terminals.
- a single current path associated with the power switch is defined by each individual one of the associated circuit breakers between the two DC voltage connections.
- the associated power switches are symmetrically arranged and interconnected with respect to the DC voltage connections such that one is in high-frequency operation of the power semiconductor module, preferably above 10 kHz, more preferably above 100 kHz, in particular above 1 MHz, and / or in operation, the circuit breaker with high voltage gradients, preferably of over 10 V / ns, in particular of about 100 V / ns, in the individual respective one of the circuit breaker associated current paths and / or in at least one of the current branches formed current density, at least substantially, is homogeneously distributed.
- At least one of the power switches is disposed on the first major surface of the carrier substrate and at least one further of the power switches is disposed on the second major surface of the carrier substrate.
- a substantially homogeneously distributed current density in the individual current paths associated with each of the circuit breakers and / or in at least one of the current branches corresponds in the sense of the invention to a spatial distribution of the current density, in which relative deviations are less than 25%, preferably less than 15%, especially less than 2%.
- the symmetrical loading of the circuit breaker also leads to an increase in the life of the power semiconductor module, since a concentration of the current flow in individual circuit breakers, which would damage the circuit breaker and thus the power semiconductor module, such as by local temperature increase, is reliably avoided.
- the symmetrical arrangement and interconnection of the power switches in at least one branch of current leads to the formation of a homogeneous current density distribution in the current paths in high-frequency operation of the power semiconductor module and thus also enables the avoidance or at least the reduction of a constriction of the electrical current in the current paths and / or current branches.
- the supply lines run from the DC connections or from the AC connection to the circuit breakers, ie, the current paths associated with the power switches, preferably electrically and / or geometrically substantially parallel.
- each of the switching elements with the current path assigned to it can lie in one plane, the planes of electrically connected power switches also being geometrically parallel to one another.
- the arrangement of the power switches on the first and second major surfaces allows for guiding the electrical current during operation of the power semiconductor module about an edge of the module, such that the surface surrounded by the electrical current is substantially perpendicular to a first or second cross-sectional area of the carrier substrate Main area corresponds.
- This also makes it possible to reduce, in particular minimize, the total inductance of the power semiconductor module according to the invention. As a result, overvoltages and switching losses can at least be reduced, so that a correspondingly more efficient operation of the power semiconductor module according to the invention is made possible.
- the inventive arrangement of the power switch and / or the associated current paths it is also possible to achieve a substantially homogeneous temperature distribution during operation of the power semiconductor module according to the invention.
- the power semiconductor module, or at least its power switch may preferably be operated at high operating temperatures, preferably above 150 ° C., more preferably above 185 ° C., in particular above 200 ° C.
- the installation space of the power semiconductor module available for the power switches and their leads can also be increased compared to a purely planar power semiconductor module, in which the bridge circuit is formed exclusively two-dimensionally on a substrate surface , Accordingly, an increased integration density of the power semiconductor module is made possible.
- the electromagnetic compatibility of the module can be improved by manufacturing the carrier substrate, which is preferably designed as a heat sink for dissipating heat, from an electrically insulating material, since a capacitive coupling to the carrier substrate, which is preferably designed as a heat sink and thus also to a housing, which accommodates the carrier substrate, can be avoided or at least reduced.
- the invention provides an efficient and also in high-frequency operation and / or operation with high voltage gradients long-lasting power semiconductor module, in particular with a low total inductance and a homogeneous during operation temperature distribution available.
- the first subset of one or more of the power switches is disposed on the first major surface of the planar carrier substrate and the second subset of one or more of the power switches is disposed on the second major surface of the planar carrier substrate.
- the first and second current-conducting current branches are respectively arranged on mutually opposite main surfaces of the carrier substrate, whereby an equal distribution of the current density in the current paths and / or current branches can be realized particularly easily.
- such a symmetrical, in particular a geometric parallel circuit the respective circuit breaker in the power branches can be realized particularly easily.
- a 2-level module ie, a power semiconductor module whose AC voltage output side voltage changes between 2 voltage values, such as an inverter based on a B6 bridge
- this may also include a 3-level module, such as a bridge circuit with an I-type topology (I-type inverter), in which in each case at least one power switch from the first and second branch current also in a third branch current is to be formed.
- I-type inverter I-type topology
- the power switches of the first subset are arranged symmetrically with respect to the carrier substrate with respect to the power switches of the second subset, ie, each power switch of the first subset is compared with a power switch of the second subset, such that the inductances of the current paths of each pair of opposing power switches the first major surface and the second major surface are substantially identical.
- This allows a homogeneous current distribution to all power switches or supply lines and makes a constriction of the current in a plane parallel to the first or second main surface in the operation of Power semiconductor module at high frequencies avoidable or at least reducible.
- a third subset of one or more of the power switches is part of a third power branch of the power semiconductor module extending between a third DC voltage terminal having a polarity opposite to the first and second DC voltage terminals and the AC voltage terminal of the power semiconductor module.
- a DC link capacitance electrically connected to the DC voltage terminals has two series-connected DC link capacitors, between which the third DC voltage connection is arranged, so that an N PC-type inverter (NPC, neutral point clamped), such as an I-type inverter or a T-type inverter in which each of the power switches is contained only in one branch current is formed.
- NPC N PC-type inverter
- the harmonic content of a voltage converted by the power semiconductor module compared with a voltage converted by a 2-level module can be reduced, while at the same time an increase in electromagnetic compatibility (EMC) can be achieved, since the two additional voltage levels cause the voltage connected per unit time halved.
- EMC electromagnetic compatibility
- the first subset comprises two or more of the power switches, which are electrically connected in parallel with each other.
- the second subset comprises two or more of the power switches, which are electrically connected in parallel with each other.
- the third subset also has two or more of the power switches, which are electrically connected in parallel with each other.
- the associated power switches are symmetrically arranged and interconnected with respect to the DC voltage connections such that the inductances formed by the respective individual current paths of one of the power switches are at least substantially equal to each other.
- substantially equal inductances can be formed in each of the current paths of a current branch.
- all power switches of a current branch can also carry essentially the same current in high-frequency operation, so that a particularly homogeneous distribution of the current density in the current paths and / or current branches is made possible.
- Substantially identical inductances which are formed by the current switches associated with the current paths, correspond in the context of the invention inductances, which have a relative deviations of less than 25%, preferably less than 15%, in particular less than 2%.
- the first DC connection is arranged areally along a first edge of the first main area and the second DC connection is arranged areally along a second edge of the second main area opposite the first edge of the first main area.
- the intermediate circuit capacitance can be contacted surface-wide and thus the so-called commutation inductance, i. the occurring inductance when changing the current-carrying current branch, which regularly causes power losses during operation of the power semiconductor module can be reduced. In this way, an increase in the energy efficiency of the power semiconductor module can be achieved.
- the DC connections are spatially close, whereby the area enclosed by the first and second, optionally also the third, current branch and thus also the total inductance of the power semiconductor module can advantageously be reduced, ie Overvoltages and power losses during operation of the power semiconductor module can be reduced.
- the first subset of two or more of the power switches and at least one power switch of the third subset of two or more of the power switches are disposed on the first main surface of the sheet carrier substrate, and the second subset of two or more of the power switches and at least a third subset of two or more of the power switches is disposed on the second main surface of the sheet carrier substrate.
- a part of the power switches from the first and / or second subset form the third subset.
- a half-bridge with I-type topology I-type inverter
- circuit breakers with a lower blocking voltage can be used than in a comparable 2-level module.
- a diode is arranged in each of the current paths defined by the power switches from the third subset, whereby the current flow between the first, second and third DC connection and the AC voltage connection can be controlled such that the current flow between the first, second and third current branch commutated and thereby a voltage applied to the DC voltage terminals DC voltage is converted into an AC voltage, such as a sinusoidal voltage with respect to a 2-level module reduced harmonic content.
- the first and second subset of two or more of the power switches are disposed on the first major surface of the sheet carrier substrate, and the third subset of two or more of the power switches is disposed on the second major surface of the sheet carrier substrate.
- T-type inverter T-type inverter
- An advantage of this embodiment compared to an embodiment in I-type topology is that several circuit breakers from the first, second and / or third subset of circuit breakers can be easily symmetrically arranged and interconnected, so that a structure with a particularly low inductance is realized ,
- the first subset of two or more of the power switches on the first major surface of the sheet carrier substrate is preferably symmetrical with respect to second subset of two or more of the power switches arranged on the first main surface of the planar support substrate.
- the first subset may be arranged in a first subarea and the second subset in a second subarea of the first main surface.
- the first and second sub-areas each occupy the same area, wherein the first and second sub-areas of the first main area are defined by an axis which is preferably symmetrical between the first DC terminal and the second DC terminal.
- the first and second direct current connections are arranged flat along an edge of one of the main surfaces next to one another.
- the third direct current connection can be arranged flat along an edge of the opposite main surface, so that the first and second direct current connection are opposite to the third direct current connection.
- the planar carrier substrate is made of an electrically insulating material, in particular a ceramic or a plastic, and is adapted to dissipate heat generated during operation of the power semiconductor module, in particular the circuit breaker.
- conductor layers such as a metallization
- the module can be designed to be particularly flat, so that during operation, the cross-sectional area of the carrier substrate surrounded by the current and limited by the first and second main surfaces and thus the total inductance of the module becomes particularly small.
- the planar carrier substrate is metallized in the areas in which the plurality of power switches, the DC connections and / or the AC connection is arranged.
- the metallization contains in a preferred embodiment, a copper layer, in particular with a thickness of 100 to 1500 ⁇ , preferably from 250 to 1000 ⁇ , preferably of 500 ⁇ .
- the metallization can be applied directly to the carrier substrate, for example, in the context of a DCB (direct copper bonding) or AMB (active metal brazing) process.
- the thermal resistance which is caused by the metallization between the power switches and the carrier substrate, compared to the thermal resistance, which is formed by layer structures between the circuit breakers and a conventional electrically conductive carrier substrate, substantially halved, in particular to less than 0.5 K. / W, preferably to less than 0.4 K / W, preferably reduced to less than 0.3 K / W.
- An electrical contact of the circuit breaker can be made in the form of contact tabs, in particular bonding wires, which connect the circuit breaker with another metallized area.
- the carrier substrate between the first and second main surface on a first side surface on which the AC power connection is arranged.
- the AC connection is preferably formed by a metallization, in particular a copper layer, of the side surface.
- the AC terminal is formed by a terminal tab that engages around the first side surface and each contacts a metallized area on the first and second major surfaces.
- a flat design of the power semiconductor module can be achieved, in which the area enclosed by the current paths of the current branches and thus the total inductance of the Power semiconductor module is reduced compared to planar constructed power semiconductor modules.
- the first direct current connection has a first electrically conductive spring device and the second direct current connection has a second electrically conductive spring device, and the intermediate circuit capacitance is arranged between the first spring device and the second spring device.
- the DC link capacitance can be connected via the first and second spring device to the first and second DC connection.
- the planar carrier substrate has on the first main surface a metallized first region, in which at least one of the power switches is arranged, and on the second main surface a metallized second region, in which at least one further power switch is arranged, wherein the first metallized region is electrically conductively connected to the second metallized region via an electrical connection extending through the planar carrier substrate.
- This so-called through-connection promotes the possibilities of a symmetrical arrangement and interconnection of the power switches from the first and second, and possibly also third, sub-groups, so that the inductances formed by the current paths are substantially equal.
- a damping capacity which neutralizes interfering high frequencies or voltage peaks, is arranged in at least one of the current branches.
- a so-called snubber the commutation inductance can be further reduced.
- voltage rise rates at the circuit breakers can be limited.
- planar carrier substrate in a region of at least one of the power switches on a cooling channel, which is flowed through by a cooling medium for cooling the at least one of the circuit breaker.
- a cooling channel for guiding the cooling medium to dissipate the heat of at least two opposing circuit breakers serve, whereby the number of cooling channels compared to a planar design power semiconductor module with the same number of circuit breakers can be substantially halved.
- the power switches on the first main surface may be staggered relative to the power switches on the second main surface.
- the heat generated by the circuit breakers in the operation of the module distributed over a larger area and allows a more homogeneous temperature distribution.
- the heat generated in the circuit breakers in the operation of the power semiconductor module can be dissipated by the turbulent flow particularly effective, while due to the further area with the substantially laminar flow of energy to maintain the thus only partially turbulent flow compared to a completely turbulent flow can be reduced , As a result, the power semiconductor module can be operated efficiently.
- a second aspect of the invention relates to a production method for a power semiconductor module, in particular drive converter module for operating a vehicle drive, according to the first aspect of the invention, comprising the following manufacturing steps: manufacturing a planar carrier substrate having a first and a second main surface; Providing a plurality of circuit breakers; and applying and interconnecting, in particular contacting, at least one of the power switches on the first main surface of the carrier substrate and at least one further of the power switches on the second main surface of the carrier substrate such that a first subset of one or more of the power switches is part of a first current branch of the power semiconductor module, which runs between a first DC voltage connection and an AC voltage connection of the power semiconductor module.
- a second subset of one or more of the power switches is thereby preferably part of a second current branch of the power semiconductor module, which runs between a second direct voltage connection opposite to the first direct voltage connection and the alternating voltage connection of the power semiconductor module.
- the first branch and the second branch are connected to the AC terminal in such a way that together they form a half-bridge connected in parallel with the DC terminals, wherein in each of the two branches by each one of the associated circuit breaker a between the two DC terminals extending, the circuit breaker associated individual current path is defined and within at least one, preferably each, the power branches the associated circuit breaker with respect to the DC voltage connections are arranged and interconnected symmetrically such that in high frequency operation of the power semiconductor module, preferably at over 10 kHz, more preferably at about 100 kHz, in particular at more than 1 MHz, and / or during operation of the circuit breakers with high voltage gradients, preferably of more than 10 V / ns, in particular of more than 100 V / ns, in the
- the carrier substrate is preferably metallized, in particular by applying a copper layer.
- the metallization can be applied by a DCB process (direct copper bonding process), an AMB process (active metal brazing process), thick film technology or rapid prototyping or 3D printing.
- a first substrate part of the planar carrier substrate, which has the first main area, and a second substrate part of the planar carrier substrate, which has the second main area, are manufactured.
- the circuit breaker can be applied and interconnected and the two substrate parts, in particular by resintering with slip, gluing, soldering or sintering, are joined together.
- the plurality of circuit breakers can be applied to the first or second main surface of the carrier substrate by means of a production device that is set up to produce purely planar power semiconductor modules.
- the first and / or second substrate part of the carrier substrate preferably has a cooling channel through which cooling medium can flow or in each case a part of a cooling channel.
- the cooling channel can be easily, in particular in the range of at least one of the circuit breaker, provided with a means for promoting a turbulent flow.
- the power switches are applied by sintering to the first main surface and the second main surface of the carrier substrate and interconnected, in particular contacted.
- electrically conductive connections such as bonding wires or leadframes, between the circuit breakers and / or electrically conductive layers can be applied to the carrier substrate by sintering on the carrier substrate or connected to the circuit breakers and / or the electrically conductive layers.
- the power switches are connected by sintering electrically conductive with a metallization, in particular metallized areas on the carrier substrate.
- a third aspect of the invention relates to a vehicle, in particular motor vehicle, with a vehicle drive, which has a power semiconductor module according to the first aspect of the invention to the current direction.
- FIG. 1 shows an embodiment of a power semiconductor module in a side view
- Figure 2 shows an embodiment of a 2-level module in a developed form
- 3 shows an embodiment of a T-type inverter
- FIG 4 shows an embodiment of an I-type inverter.
- a power semiconductor module 1 with circuit breakers 2 is shown in a side view, wherein the circuit breaker 2 are each arranged in a current branch 3a, 3b.
- the current branches 3a, 3b extend between a first DC voltage connection 4a, for example a positive pole, and an AC voltage connection 5 on a first main surface 6a of a planar carrier substrate 6 or between a second DC voltage connection 4b, for example a negative pole, and the AC voltage connection 5 on a second main surface 6b the carrier substrate 6.
- the current branches 3a, 3b are composed of the circuit breakers 2 and the respective electrical supply and discharge lines, ie the electrical connections from the circuit breakers 2 to the DC voltage terminals 4a, 4b and the AC voltage terminal 5, together.
- the electrical supply and discharge lines are at least partially formed by a metallization 7, in particular an approximately 500 ⁇ thick copper layer, which are applied in the context of the manufacturing process to the carrier substrate 6 made of an electrically insulating material.
- the power switches 2, the DC voltage terminals 4a, 4b and the AC voltage terminal 5 may be soldered to the metallization 7 and / or be formed by this.
- the corresponding solder layer 8 preferably has a thickness of 40 to 120 ⁇ , preferably 60 to 100 ⁇ , in particular about 80 ⁇ on.
- the power switches 2, the DC voltage terminals 4a, 4b and the AC voltage terminal 5 may be applied to the metallization 7 by sintering.
- the carrier substrate 6 can be provided in a particularly simple manner on both main surfaces 6a, 6b with the abovementioned components, without the need for complicated two-sided soldering processes.
- the metallization 7 is preferably composed of a plurality of metallized regions 7a, 7b on each of the main surfaces 6a, 6b, which may be electrically connected to each other, for example by means of bonding wires 9 or leadframes (not shown).
- one or more damping capacitors may also be contained or arranged in the current branches 3a, 3b.
- the metallized regions 7a, 7b can be electrically connected to one another via an electrically conductive connection 9 ', which is guided through the carrier substrate 6.
- the AC voltage terminal 5 is formed as a terminal lug, which surrounds a first side surface 1 1 a of the carrier substrate 6 and each contacted a metallized region on the first and second main surface 6a, 6b.
- the AC voltage terminal 5 can also be formed by a metallized region on the first side surface 11a, which extends around the edges between the first side surface 11a and the first and second main surfaces 6a, 6b.
- a DC link capacitor 10 such as a capacitor
- the first and second main surfaces 6a, 6b Circuit breaker 2 together with the DC link capacitance 10 a half-bridge, wherein each half of the half-bridge on the first main surface 6a and on the second main surface 6b is arranged.
- the two halves of the half-bridge can be constructed substantially symmetrically with respect to one another, i. the circuit breaker 2 and supply and discharge lines of bonding wires 9 and metallized areas or the current branches 3a, 3b are arranged substantially symmetrically, in particular mirror or rotationally symmetrical with respect to a point or axis 12.
- the power semiconductor module 1 is easily scalable with respect to the number of power switches 2, by the DC terminals 4a, 4b, the AC voltage terminal 5 and the metallization 7 are carried out correspondingly flat in a direction perpendicular to the image plane, so that a plurality of power switches 2 in this direction next to each other can be arranged and simply electrically connected in parallel (see, for example, Figure 2).
- the inductance of the individual current paths formed thereby, which together form the current branches 3a, 3b, are kept equal and, in particular, low, so that a homogeneous current density distribution is realized in the individual current paths and the power semiconductor module can convert a higher power during operation.
- the electric current also does not have to be guided in the direction perpendicular to the image plane, as a result of which, in high-frequency operation, current constriction in planes perpendicular to the image plane can be avoided.
- the carrier substrate 6 has a plurality of cooling channels 13, through which a cooling medium for removing the heat generated during operation of the power semiconductor module 1 can be flowed.
- FIG. 2 shows an exemplary embodiment of a power semiconductor module 1 embodied as a 2-level module in an unwound form, with a first main area 6a, a second main area 6b and a first side area 11a of a planar carrier substrate "unfolded" next to each other for better illustration are shown.
- the carrier substrate is provided on the main surfaces 6a, 6b and the first side surface 11a with a metallization 7 in such a way that different electrically conductive regions are formed.
- a metallization 7 In each one of these areas on the first and second main surface 6a, 6b are electrically connected in parallel circuit breaker 2, which are electrically connected via bonding wires 9 with another metallized region.
- the thereby spanned by the bonding wires 9 areas 7 ' are used to drive the circuit breaker 2, in particular when using field effect transistors, IGBTs and / or the like as a circuit breaker 2 as the gate terminal.
- the regions 7 'can also be metallized.
- the regions 7 'can also be formed by printed circuit boards connected to the carrier substrate, in particular adhered to the carrier substrate, which are set up to control the power switches 2 and can be connected to a power switch driver (not shown) outside the module 1.
- the metallized region along an edge of the carrier substrate on the first main surface 6a forms a planar first DC voltage connection 4a, from which electrical current can flow uniformly across the circuit breaker 2 arranged in this region to the first side surface 11a.
- the metallized region on the first side surface 1 a forms an AC voltage connection 5.
- the metallized region along an edge of the carrier substrate on the second main surface 6b forms a planar second DC voltage connection 4b, from which electric current can flow uniformly across the power switches 2 on the second main surface 6b to the first side surface 11a.
- the first and second DC voltage terminals 4a, 4b are each electrically connected to a DC link capacitance (not shown).
- a 2-level module in particular a B6 inverter, with a plurality of power transistors connected in parallel to increase the current carrying capacity can be formed. Due to the symmetrical arrangement on the first and second main surfaces 6a, 6b, a uniform current distribution results on the power transistors, wherein the total inductance of the module due to the flat design (DC link capacity can on a second, the first side surface 1 1 a opposite side surface (not shown) connected to the DC voltage terminals 4a, 4b) remains low.
- FIG. 3 shows an exemplary embodiment of a power semiconductor module 1 embodied as a T-type inverter in a top view, again for the better Representation of a first main surface 6a, a second main surface 6b and a first side surface 1 1 a of a flat carrier substrate "unfolded" are shown side by side.
- a metallization 7 is applied in such a way that along an edge on the first main surface 6a a first direct voltage connection 4a, for example a positive pole, and a second direct voltage connection 4b, for example a negative pole, are formed.
- the DC voltage terminals 4a, 4b are electrically connected via bonding wires 9 and circuit breaker 2 to a further metallized region on the first main surface 6a, which merges into a metallized region forming an AC voltage connection 5 arranged on the first side surface 1a.
- a metallized region forms a third DC voltage connection 4c, for example a pole which is neutral with respect to the positive pole and the negative pole, to which substantially no voltage is applied when connected to an electrical machine during operation of the module, via bonding wires 9 and power switch 2 also with a further metallized region on the second major surface 6b, which merges into the AC voltage terminal 5 on the first side surface lla, is electrically conductively connected.
- the areas 7 'spanned by the bonding wires 9 also form the connections for activating the circuit breaker 2 and can be formed by a metallization or circuit boards for controlling the circuit breaker 2.
- FIG. 4 shows an exemplary embodiment of a power semiconductor module 1 embodied as an I-type inverter in a plan view, with a first main area 6a, a second main area 6b and a first side area 11a of a planar carrier substrate "unfolded" next to one another for better illustration are shown.
- the carrier substrate is metallized in such a way that different conductive regions are formed on the first main surface 6a, the second main surface 6b and the first side surface 1a of the carrier substrate.
- a metallization 7 along one edge of the carrier substrate forms a first DC voltage connection 4a, for example a positive pole, which via bonding wires 9 and circuit breaker 2 with a further metallized region on the first main surface 6a is electrically connected, which merges into a metallized region on the first side surface 1 1 a.
- the metallization 7 on the first side surface 11a forms an AC voltage connection 5.
- a metallization 7 along one edge of the carrier substrate forms a second DC voltage connection 4b, for example a negative pole, which is electrically conductively connected via bonding wires 9 and power switch 2 to a further metallized region on the second main surface 6b. This further area merges into the AC voltage connection 5 on the first side surface 11a.
- a further metallized region Arranged on the first main surface 6a is a further metallized region, which extends over the first side surface 1a to the second main surface 6b and forms a third direct voltage connection 4c, approximately opposite the positive pole and the negative pole neutral pole.
- the third DC voltage connection 4c is also electrically conductively connected via bonding wires 9, diodes 2 'and power switch 2 to the AC voltage connection 5.
- a 3-level module in particular in I-type topology, are formed. Between the illustrated metallized areas extending boards for controlling the gates of the circuit breaker 2 are not shown for reasons of clarity.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Inverter Devices (AREA)
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE102017209515.6A DE102017209515A1 (de) | 2017-06-06 | 2017-06-06 | Leistungsumrichtermodul und Verfahren zu dessen Herstellung |
PCT/EP2018/064728 WO2018224480A1 (fr) | 2017-06-06 | 2018-06-05 | Module convertisseur de puissance et procédé de fabrication de ce dernier |
Publications (1)
Publication Number | Publication Date |
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EP3635781A1 true EP3635781A1 (fr) | 2020-04-15 |
Family
ID=62555067
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP18729647.0A Pending EP3635781A1 (fr) | 2017-06-06 | 2018-06-05 | Module convertisseur de puissance et procédé de fabrication de ce dernier |
Country Status (5)
Country | Link |
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US (1) | US11296054B2 (fr) |
EP (1) | EP3635781A1 (fr) |
CN (1) | CN111033734B (fr) |
DE (1) | DE102017209515A1 (fr) |
WO (1) | WO2018224480A1 (fr) |
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Publication number | Priority date | Publication date | Assignee | Title |
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US11678468B2 (en) * | 2020-09-24 | 2023-06-13 | Dana Tm4 Inc. | High density power module |
DE102020214607A1 (de) | 2020-11-19 | 2022-05-19 | Zf Friedrichshafen Ag | Topologischer Halbleiterschalter, Halbleiterpackage, Halbbrückenmodul, B6-Modul, Inverter, Elektromotoranordnung sowie Kraftfahrzeug |
DE102020214932A1 (de) | 2020-11-27 | 2022-06-02 | Robert Bosch Gesellschaft mit beschränkter Haftung | Verbesserte Performance der Leistungselektronik durch zweiseitige Nutzung des Kühlkörpers |
DE102021213782A1 (de) | 2021-12-03 | 2023-06-07 | Zf Friedrichshafen Ag | Leistungshalbleitermodul mit gegenüberliegenden schalterchips |
DE102022204400A1 (de) | 2022-05-04 | 2023-11-09 | Volkswagen Aktiengesellschaft | Wechselrichter mit mindestens einer Halbbrücke |
DE102022208583A1 (de) | 2022-08-18 | 2023-08-03 | Zf Friedrichshafen Ag | Leistungshalbleitermodul mit innerem kühlkanal |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
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DE4421319A1 (de) * | 1994-06-17 | 1995-12-21 | Abb Management Ag | Niederinduktives Leistungshalbleitermodul |
JP4478618B2 (ja) * | 2005-06-28 | 2010-06-09 | 本田技研工業株式会社 | パワー半導体モジュール |
JP4862937B2 (ja) * | 2009-12-08 | 2012-01-25 | トヨタ自動車株式会社 | 蓄電装置の内部抵抗推定装置、蓄電装置の劣化判定装置、および電源システム |
DE102010002627B4 (de) * | 2010-03-05 | 2023-10-05 | Infineon Technologies Ag | Niederinduktive Leistungshalbleiterbaugruppen |
JP5259016B2 (ja) * | 2010-05-21 | 2013-08-07 | 三菱電機株式会社 | パワー半導体モジュール |
US8942020B2 (en) * | 2012-06-22 | 2015-01-27 | General Electric Company | Three-level phase leg for a power converter |
DE102012218868B3 (de) * | 2012-10-17 | 2013-11-07 | Semikron Elektronik Gmbh & Co. Kg | Leistungshalbleitermodul |
DE102013003527A1 (de) * | 2013-03-04 | 2014-09-04 | Danfoss Silicon Power Gmbh | Vorrichtung zum Niedertemperatur-Drucksintern, Verfahren zum Niedertemperatur-Drucksintern und leistungselektronische Baugruppe |
US8847328B1 (en) * | 2013-03-08 | 2014-09-30 | Ixys Corporation | Module and assembly with dual DC-links for three-level NPC applications |
ES2743052T3 (es) * | 2013-04-09 | 2020-02-18 | Otis Elevator Co | Arquitectura de unidad de accionamiento que emplea conmutadores de nitruro de galio |
CN203839372U (zh) * | 2013-04-29 | 2014-09-17 | Abb技术有限公司 | 功率半导体模块和接触组件 |
DE102013104522B3 (de) * | 2013-05-03 | 2014-06-26 | Semikron Elektronik Gmbh & Co. Kg | Leistungshalbleitermodul mit Subeinheiten und Anordnung hiermit |
WO2015159751A1 (fr) * | 2014-04-14 | 2015-10-22 | 富士電機株式会社 | Dispositif à semi-conducteur |
WO2016084622A1 (fr) * | 2014-11-28 | 2016-06-02 | 富士電機株式会社 | Dispositif semiconducteur |
EP3032581B1 (fr) * | 2014-12-11 | 2019-10-09 | Dr. Johannes Heidenhain GmbH | Agencement de cellule de commutation pour onduleur |
EP3147941A1 (fr) * | 2015-09-23 | 2017-03-29 | ABB Technology AG | Produit semi-fini et procédé de fabrication d'un module semi-conducteur de puissance |
DE202016102722U1 (de) * | 2016-05-23 | 2016-06-20 | Danfoss Silicon Power Gmbh | Umrichteranordnung |
-
2017
- 2017-06-06 DE DE102017209515.6A patent/DE102017209515A1/de active Pending
-
2018
- 2018-06-05 WO PCT/EP2018/064728 patent/WO2018224480A1/fr unknown
- 2018-06-05 US US16/620,318 patent/US11296054B2/en active Active
- 2018-06-05 CN CN201880037682.XA patent/CN111033734B/zh active Active
- 2018-06-05 EP EP18729647.0A patent/EP3635781A1/fr active Pending
Also Published As
Publication number | Publication date |
---|---|
DE102017209515A1 (de) | 2018-12-06 |
CN111033734B (zh) | 2023-09-15 |
CN111033734A (zh) | 2020-04-17 |
WO2018224480A1 (fr) | 2018-12-13 |
US11296054B2 (en) | 2022-04-05 |
US20200152611A1 (en) | 2020-05-14 |
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