EP3606869B1 - Liaison eutectique avec alge - Google Patents

Liaison eutectique avec alge Download PDF

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Publication number
EP3606869B1
EP3606869B1 EP18781061.9A EP18781061A EP3606869B1 EP 3606869 B1 EP3606869 B1 EP 3606869B1 EP 18781061 A EP18781061 A EP 18781061A EP 3606869 B1 EP3606869 B1 EP 3606869B1
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Prior art keywords
layer
substrate
wafer
aluminum
germanium
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German (de)
English (en)
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EP3606869B8 (fr
EP3606869A1 (fr
EP3606869A4 (fr
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Martin Heller
Toma Fujita
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Rohm Co Ltd
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Kionix Inc
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B15/043—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of metal
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/20—Layered products comprising a layer of metal comprising aluminium or copper
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0315—Cavities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0127—Using a carrier for applying a plurality of packaging lids to the system wafer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0172—Seals
    • B81C2203/019—Seals characterised by the material or arrangement of seals between parts
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/03—Bonding two components
    • B81C2203/033—Thermal bonding
    • B81C2203/035—Soldering

Definitions

  • the present invention relates to wafer bonding, and more particularly to eutectic bonding for sealing MEMS devices.
  • MEMS Micro Electro-Mechanical Systems
  • a MEMS motion sensor may be, for example, an accelerometer for detecting linear motion, or a gyroscope for detecting rotation and angular velocity.
  • Advanced planar silicon processes are being increasingly used to manufacture MEMS devices.
  • Glass frit bonding has been used for wafer-level packaging of MEMS devices, such as accelerometers.
  • gyroscopes due to its limitation in achievable minimum seal width, cost, and lead content, a substantial number of the current generation of gyroscopes are made using other wafer-level packaging solutions, such as eutectic solder bonding.
  • a eutectic wafer bonding processes require clean surfaces. Excessive amounts of native oxides and other organic contaminants on the surfaces may damage surface bond formation, strength, and integrity. Depending on the materials in the seal layer stack and device configurations, the removal of the native oxide layer and other contaminants from the surface being bonded may cause difficulties. Robust wafer bonding and sealing of MEMS devices using eutectic wafer bonding processes continues to pose challenges.
  • the moving portion can be made to move between the lower electrode and the upper substrate.
  • the method further includes, in part, forming an adhesive layer below the Aluminum Germanium structure in the first substrate. In one embodiment, the method further includes, in part, forming an Alumina layer between the Aluminum Germanium structure and the adhesive layer. In one embodiment the adhesive layer is a Titanium Nitride layer. In one embodiment, the method further includes, in part, forming an Alumina layer below the Polysilicon layer in the second substrate. In one embodiment, the method further includes, in part, forming a Polycide layer below the Polysilicon layer in the second substrate. In one embodiment, the method further includes, in part, forming an adhesive layer below the Alumina layer in the second substrate.
  • a method of sealing a MEMS device formed in a first semiconductor substrate using a second semiconductor substrate includes, in part, forming a Silicide layer either in or above the first substrate; forming an Aluminum Germanium structure above the Silicide layer of the first substrate; forming a Silicide layer either in or above a substrate of the second substrate; covering the first substrate with the second substrate so as to cause the Aluminum Germanium structure of the first substrate to contact the Silicide layer of the second substrate; and performing eutectic bonding between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form a AlGeSi sealant thereby to seal the MEMS device.
  • a method of sealing a MEMS device formed in a first semiconductor substrate using a second semiconductor substrate includes, in part, forming a Silicide layer either in or above the second substrate; forming an Aluminum Germanium structure above the Silicide layer of the second substrate; covering the first substrate with the second substrate so as to cause the Aluminum Germanium structure of the second substrate to contact the Silicide layer of the first substrate; and performing eutectic bonding between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form a AlGeSi sealant thereby to seal the MEMS device.
  • a method of sealing a MEMS device formed in a first semiconductor substrate using a second semiconductor substrate includes, in part, forming a Silicide layer either in or above a substrate of the first substrate; forming an Aluminum Germanium structure above the Silicide layer of the first substrate; forming a Silicide layer either in or above a substrate of the second substrate; forming an Aluminum Germanium structure above the Silicide layer of the second substrate; covering the first substrate with the second substrate so as to cause the Aluminum Germanium structure of the first substrate to contact the Aluminum Germanium structure of the first substrate; and performing eutectic bonding between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form a AlGeSi sealant thereby to seal the MEMS device.
  • a method of sealing a MEMS device formed in a first semiconductor substrate using a second semiconductor substrate includes, in part, forming a Silicide layer either in or above a substrate of the first substrate; forming an Aluminum Germanium structure above the Silicide layer of the first substrate; forming a Silicide layer either in or above a substrate of the second substrate; forming an Aluminum structure above the Silicide layer of the second substrate; covering the first substrate with the second substrate so as to cause the Aluminum Germanium structure of the first substrate to contact the Aluminum structure of the second substrate; and performing eutectic bonding between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form a AlGeSi sealant thereby to seal the MEMS device.
  • a method of sealing a MEMS device formed in a first semiconductor substrate using a second semiconductor substrate includes, in part, forming a Silicide layer either in or above a substrate of the first substrate; forming a Germanium structure above the Silicide layer of the first substrate; forming a Silicide layer either in or above a substrate of the second substrate; forming an Aluminum Germanium structure above the Silicide layer of the second substrate; covering the first substrate with the second substrate so as to cause the Aluminum Germanium structure of the second substrate to contact the Germanium structure of the first substrate; and performing eutectic bonding between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form a AlGeSi sealant thereby to seal the MEMS device.
  • a MEMS device (alternatively referred to herein as sensor) is hermetically sealed in a cavity by applying Aluminum-Germanium-Silicon (AlGeSi) eutectic wafer bonding between a first silicon wafer in which the MEMS device is formed (hereinafter referred to as device wafer) and a second silicon wafer (hereinafter referred to as lid wafer) covering the top surface of the device wafer.
  • AlGeSi Aluminum-Germanium-Silicon
  • the eutectic wafer bonding is adapted to enable a structure that includes Aluminum and/or Germanium, formed on either the device wafer, the lid wafer, or both, to bond with Silicon atoms present in a structure/region of either the device wafer, the lid wafer, or both, to form a strong AlGeSi sealant sealing/encasing the MEMS device.
  • the processing steps for forming the device wafer and the lid wafer, in accordance with a number of exemplary embodiments of the present invention, are described below.
  • FIG. 1 is a cross-sectional view of a device wafer (also referred to herein as substrate) 100 following the formation of multiple layers thereon, in accordance with one exemplary embodiment of the present invention.
  • Device wafer 100 is shown as including, in part, an adhesion layer 230, which may be a Titanium Nitride TiN layer having a thickness ranging, for example, from 100 nm to 200 nm.
  • Device wafer 100 is also shown as including a layer 240 of Alumina (Al2O3), having a thickness ranging, for example, from 100 nm to 200 nm, and formed above adhesion layer 230.
  • Both TiN layer 230 and Alumina layer 240 may be deposited using well known techniques, such as ALD, CVD or PVD processes.
  • Device wafer 100 is also shown as including an Aluminum layer 250 overlaying Alumina layer 240, and a Germanium layer 260 overlaying Aluminum layer 250.
  • the thicknesses of Aluminum layer 250 and Germanium layer 260 are selected so as to enable eutectic bonding to take place when the required temperature and pressure are applied.
  • Aluminum layer 250 and Germanium layer 260 may be selected to have thicknesses of 980 nm and 530 nm, respectively.
  • layers 230, 240, 250, and 260 are removed to form an opening 285 having sidewalls 292, as shown in Figure 2A .
  • the device structure shown in Figure 2B is similar to the device structure shown in Figure 2A except that in Figure 2B , an opening 255 is formed in Alumina 240 to enhance electrical connection between Titanium Nitride layer 230 undelaying Alumina layer 240, and Aluminum layer 250 and Germanium layer 260 overlaying Alumina layer 240.
  • FIG. 3A a cavity 110 is formed at opening 285 in Silicon substrate in which MEMS device 120 is formed using any one of a number of conventional semiconductor processing techniques.
  • Figure 3B is a top view of device wafer 100 shown in Figure 3A . It is understood that cross-hatched region 300 in Figure 3B corresponds to layers 230, 240, 250 and 260 of Figure 3A .
  • FIGS. 4A and 4B respectively are cross-sectional and top views of device wafer 100 after the patterning and etching processes are carried out to form an AlGe structure 280.
  • FIG. 5 is a cross-sectional view of lid wafer 500 adapted to cover device wafer 100 to hermetically seal cavity 110 and device 120, in accordance with one exemplary embodiment of the present invention.
  • Lid wafer 500 is shown as including an adhesion layer 510, an Alumina layer 520, and a Polysilicon layer 530.
  • Adhesion layer 520 may include Titanium nitride TiN, having a thickness ranging, for example, from 100 nm to 200 nm.
  • Alumina layer 520 may have a thickness ranging, for example, from 20 nm to 100 nm.
  • Polysilicon layer 530 may have a thickness ranging, for example, from 100nm to 150nm.
  • layer 520 may be a Polycide layer in place of an Alumina layer.
  • a Polycide layer may be a WSi layer, a MoSi layer, a CoSi layer, a NiSi layer, and the like.
  • lid wafer 500 As a cover for device wafer 100, using conventional patterning and etching processes, layers 510, 520 and 530 are etched to form a structure 580, as shown in Figure 6A .
  • the width W 2 of step structure 580 may be greater than width Wi of step structure 280 shown in Figure 4A .
  • Figure 6B is a top view of lid wafer 500 shown in Figure 6A .
  • the top surface of device wafer 100-shown in Figures 4A, 4B - is brought into contact with the top surface of lid wafer 500-shown in Figures 6A and 6B .
  • device wafer 100 may be placed over lid wafer 500.
  • Aluminum and Germanium disposed in structure 280 change their phases from solid to liquid to form an AlGe eutectic melt which subsequently reacts with the Silicon atoms present in the Polysilicon layer 530 to form a ternary AlGeSi.
  • the AlGeSi so formed wets the undelaying Polycide or Alumina layer.
  • Alumina layer 240 provides a barrier against gas permeation and the highly reactive eutectic melt.
  • the Alumina also provides a suitable adhesion layer for the eutectic melt.
  • the Polycide further acts as a barrier against the conduction diffusion and the highly reactive eutectic melt.
  • the Silicide layer reduces the reaction speed of the AlGe eutectic melt with the silicon contained in the silicide layer.
  • the rate of silicon incorporation into the liquid AlGe eutectic melt is made slower to provide a more controlled transformation from an AlGe eutectic melt into a tertiary AlGeSi. Any excessive uptake of Si and the resulting spike of Al or Ge into Silicon can be avoided or substantially reduced.
  • a silicon layer (amorphous, polysilicon or any other type) on top of the silicide layer can be used as an initial, easily accessible silicon source for the AlGe eutectic melt to start the silicon incorporation into the AlGe eutectic melt at a high rate, slowing down after the layer is completely dissolved.
  • the silicide acts as a diffusion barrier to reduce the undesirablet diffusion of Al and Ge atoms away from the liquid eutectic melt into the layers below.
  • the silicide layer further acts as an adhesion layer for the AlGe eutectic melt.
  • the device structure shown in Figure 7B is similar to the device structure shown in Figure 7A except that in Figure 7B , an opening 255 is formed in Alumina 240 to enhance the electrical connection between adhesion layer 230, which may be for example, Titanium Nitride TiN layer as described above or a Silicide layer as described further below, and Aluminum layer 250 and Germanium layer 260 overlaying Alumina layer 240.
  • adhesion layer 230 which may be for example, Titanium Nitride TiN layer as described above or a Silicide layer as described further below, and Aluminum layer 250 and Germanium layer 260 overlaying Alumina layer 240.
  • a Silicide layer formed and patterned on the device wafer, the lid wafer, or both provides the Silicon atoms for the AlGe eutectic melt, as described further below.
  • Figure 8A is a simplified cross-sectional view of an exemplary device wafer 100 after it has been processed to include a Silicide step structure 610, as well as a MEMS device 120 in its associated cavity 110.
  • Figure 8B is a corresponding top view of device wafer 100 showing Silicide step structure 610, cavity 110 and MEMS device 120.
  • FIGS. 9A and 9B respectively are cross-sectional and top views of device wafer 100 after the patterning and etching processes are carried out to form structure 280.
  • FIG 10A is a cross-sectional view of a lid wafer 700 adapted to cover device wafer 100 of Figure 9B to hermetically seal cavity 110 and device 120, in accordance with one exemplary embodiment of the present invention.
  • Silicide structure 710 is formed on the surface of the lid wafer.
  • Figure 10B is a corresponding top view of device wafer 700 showing Silicide structure 710 on its top surface.
  • the top surface of device wafer 100-shown in Figures 9A, 9B - is brought into contact with the top surface of lid wafer 700-shown in Figures 10A and 10B .
  • device wafer 100 may be placed over lid wafer 700.
  • Aluminum and Germanium in structure 280 change their phases from solid to liquid to form an AlGe eutectic melt which subsequently reacts with the Silicon atoms present in Silicide structures 610 and/or 710 to form a ternary AlGeSi.
  • Incorporating Silicon atoms into the AlGe eutectic melt increases the eutectic point temperature thus solidifying the melt and controlling/limiting its flow.
  • device wafer 100 of Figures 9A-9B is shown as including only a Silicide layer 610 disposed between the surface of its substrate and Aluminum layer 250, it is understood that in other embodiments one or more layers that include other materials (not shown) may be disposed between the surface of Silicon substrate 100 and Silicide structure 610. Furthermore, although device wafer 100 of Figures 9A-9B is shown as including only a single layer of Aluminum and Germanium, it is understood that in other embodiments (not shown), device wafer 100 may include multiple layers of Aluminum and Germanium deposited thereon in an alternating manner.
  • cover wafer 700 of Figures 10A-10B is shown as including only a Silicide structure 710 above its substrate surface, it is understood that in other embodiments, one or more layers that include other materials (not shown) may be disposed between the surface of the Silicon substrate 700 and Silicide structure 710.
  • a Silicide region formed and patterned within the substrate of the device wafer, the lid wafer, or both provides the Silicon atoms for the AlGe eutectic melt, as described further below.
  • Figure 12 is a simplified cross-sectional view of a device wafer 100 after it has been processed to include a Silicide region 610, as well as a MEMS device 120 in its associated cavity 110.
  • FIGS. 13A and 13B respectively are cross-sectional and top views of device wafer 100 after it has been processed, as described above, to include cavity 110, MEMS device 120, Silicide region 610 and structure 280 that includes an Aluminum layer 250 and a Germanium layer 260.
  • FIG 14 is a cross-sectional view of an exemplary embodiment of a lid wafer 700 adapted to cover device wafer 100 of Figures 13A-13B to hermetically seal cavity 110 and device 120, in accordance with one exemplary embodiment of the present invention.
  • Lid wafer 700 is shown as including a Silicide region 710 formed in its substrate.
  • the top surface of device wafer 100-shown in Figures 13A, 13B - is brought into contact with the top surface of lid wafer 700-shown in Figure 14 .
  • device wafer 100 may be placed over lid wafer 700.
  • Aluminum and Germanium present in structure 280 change their phases from solid to liquid to form an AlGe eutectic melt which subsequently reacts with the Silicon atoms present in the Silicide region 610 and/or 710 to form a ternary AlGeSi.
  • Incorporating Silicon atoms into the AlGe eutectic melt increases the eutectic point temperature thus solidifying the melt and controlling/limiting its flow.
  • device wafer 100 of Figures 13A, 13B is shown as including an Aluminum layer 250 above Silicide region 610, it is understood that in other embodiments, one or more layers that include other materials (not shown) may be present between Aluminum layer 250 and Silicide region 610.
  • device wafer 100 of Figures 13A and 13B is shown as including only a single layer of each Aluminum and Germanium, it is understood that in other embodiments (not shown), device wafer 100 may include multiple layers of Aluminum and Germanium deposited thereon in an alternating manner.
  • lid wafer 700 is shown as including only a Silicide region 710 formed in its substrate, it is understood that other embodiments of lid wafer 700 may include one or more layers disposed above Silicide region 710.
  • Figure 16 is a cross-sectional view of a device wafer 100 having a top surface that is covered by lid wafer 700, in accordance with another exemplary embodiment of the present invention.
  • the embodiment shown in Figure 16 is similar to that shown in Figure 15 , except that in the embodiment of Figure 16 , structure 780 that includes an Aluminum layer 750 and a Germanium layer 760 is formed over Silicide region 710 of lid wafer 700 and not on the device wafer 100.
  • Device wafer 100 is shown as including a silicide region 610, as well as MEMS device 120 formed in cavity 110.
  • Aluminum and Germanium present in structure 280 change their phases from solid to liquid to form an AlGe eutectic melt which subsequently reacts with the Silicon atoms present in the Silicide region 610 and/or 710 to form a ternary AlGeSi.
  • Incorporating Silicon atoms into the AlGe eutectic melt increases the eutectic point temperature thus solidifying the melt and controlling/limiting its flow.
  • lid wafer 700 of Figure 16 is shown as including an Aluminum layer 750 and a Germanium layer 760 above Silicide region 710, it is understood that in other embodiments, one or more layers that include other materials (not shown) may be present between Aluminum layer 750 and Silicide region 710. Furthermore, although lid wafer 700 of Figures 16 is shown as including only a single layer of each Aluminum and Germanium, it is understood that in other embodiments (not shown), lid wafer 700 may include multiple layers of Aluminum and Germanium deposited thereon in an alternating manner. Moreover, although in the embodiment shown in Figure 16 , device wafer 100 is shown as including only a Silicide region 610 formed in its substrate, it is understood that other embodiments of device wafer 100 may include one or more layers disposed above Silicide region 610.
  • Figure 17 is a cross-sectional view of a device wafer 100 having a top surface that is covered by lid wafer 700, in accordance with another exemplary embodiment of the present invention.
  • Device wafer 100 is shown as including an aluminum layer 250 as well as a Germanium layer 260 that collectively form an AlGe structure 280 disposed above silicide region 610 of device wafer 100.
  • Device wafer 100 is also shown as including, in part, a MEMS device 120 formed in cavity 120.
  • Lid wafer 700 is shown as including an aluminum layer 750 and a Germanium layer 760 that collectively form an AlGe structure 780 disposed above silicide region 710 of lid wafer 700.
  • AlGe eutectic melt reacts with the Silicon atoms present in the Silicide region 610 and/or Silicide region 710 to form a ternary AlGeSi.
  • incorpororating the Si atoms into the AlGe eutectic melt in accordance with embodiments of the present invention, increases the eutectic point temperature thus solidifying the melt while controlling and limiting its flow.
  • Silicide regions 610 and 710 may be formed above their respective substrate surfaces, as shown for example, in Figure 11 .
  • one or more layers of other materials may be disposed between Silicide region 610 and Aluminum layer 250 of device wafer 100, and/or between the Silicide region 710 and Aluminum layer 750 of lid wafer 700.
  • the embodiment of Figure 17 is shown as including only a single layer of each Aluminum and Germanium on each of the device and lid wafers, it is understood that in other embodiments (not shown), both the device and lid wafers may include multiple layers of Aluminum and Germanium deposited thereon in an alternating manner.
  • Figure 18 is a cross-sectional view of a device wafer 100 having a top surface that is covered by lid wafer 700, in accordance with yet another exemplary embodiment of the present invention.
  • Device wafer 100 is shown as including an Aluminum layer 250 as well as a Germanium layer 260 that are patterned and etched to collectively form an AlGe step structure 280 disposed above silicide region 610 of device wafer 100.
  • Device wafer 100 is also shown as including, in part, a MEMS device 120 formed in cavity 120.
  • Lid wafer 700 is shown as including a Germanium layer 750 disposed above silicide region 710 of lid wafer 700.
  • Aluminum and Germanium change their phases from solid to liquid to form an AlGe eutectic melt which subsequently reacts with the Silicon atoms present in the Silicide region 610 and/or 710 to form a ternary AlGeSi.
  • Incorporating the Si atoms into the AlGe eutectic melt in accordance with embodiments of the present invention, increases the eutectic point temperature thus solidifying the melt while controlling and limiting its flow.
  • Silicide regions 610 and 710 may be formed above their respective substrate surfaces, as shown for example, in Figure 11 .
  • one or more layers of other materials may be disposed between Silicide region 610 and Aluminum layer 250 of device wafer 100, and/or between the Silicide region 710 and Germanium layer 750 of lid wafer 700.
  • the embodiment of Figure 17 is shown as including only a single layer each of Aluminum and Germanium on each of the device and lid wafers, it is understood that in other embodiments (not shown), both the device and lid wafers may include multiple layers of Aluminum and Germanium deposited thereon in an alternating manner.
  • Figure 19 is a cross-sectional view of a device wafer 100 having a top surface that is covered by lid wafer 700, in accordance with another exemplary embodiment of the present invention.
  • Device wafer 100 is shown as including a Germanium layer 260 formed above its Silicide region 610.
  • Device wafer 100 is also shown as including, in part, a MEMS device 120 formed in cavity 120.
  • Lid wafer 700 is shown as including an aluminum layer 750 as well as a Germanium layer 760 that are patterned and etched to collectively form an AlGe structure 780 disposed above Silicide region 710 of lid wafer 700.
  • Aluminum and Germanium change their phases from solid to liquid to form an AlGe eutectic melt which subsequently reacts with the Silicon atoms present in the Silicide region 610 and/or 710 to form a ternary AlGeSi.
  • Incorporating the Si atoms into the AlGe eutectic melt in accordance with embodiments of the present invention, increases the eutectic point temperature thus solidifying the melt while controlling and limiting its flow.
  • Silicide regions 610 and 710 may be formed above their respective substrate surfaces, as shown for example, in Figure 11 .
  • one or more layers of other materials may be disposed between Silicide region 610 and Germanium structure 260 of device wafer 100, and/or between the Silicide region 710 and Aluminum layer 750 of lid wafer 700.
  • the embodiment of Figure 19 is shown as including only a single layer each of Aluminum and Germanium on lid wafer 700, it is understood that in other embodiments (not shown), the lid wafer may include multiple layers of Aluminum and Germanium deposited thereon in an alternating manner.
  • FIG 20 is a simplified top layout view of a MEMS device 800 which includes details compatible with the method of the present invention. Disposed near the center of MEMS 800 are drive masses 810. Formed along the periphery of the device is a Silicide layer 810. Positioned above the Silicide layer is the Aluminum Germanium stack layer 830. Also shown are a multitude of routing interconnects 830 formed from, for example, TiN/Al/TiN stack layer 840. Also shown in Figure 20 is area 870 within which two regions, namely 850 and 870 of TiN/Al/TiN are identified. The Alumina layer (not shown in these Figures) in these two regions have openings to provide electrical connection between undelaying Silicide layer 230 and overlaying Aluminum Germanium stack layer 830.
  • Figure 21 provides a more detailed view of the structure shown in region 860 of Figure 20 .
  • Region 860 is shown as including a Silicide layer 820, an Aluminum Germanium stack layer 830 and a TiN/Al/TiN stack routing layer 840.
  • Region 870 is shown as including a circular TiN/Al/TiN stack layer 840.
  • Figure 22A provides a more detailed view of region 860 showing opening 845 formed in the Alumina layer.
  • Aluminum Germanium stack layer 830 and the Alumina layer are not shown in Figure 22A .
  • Figure 22A are Tungsten via plugs with TiN liner 855.
  • Figure 22B provides a more detailed view of region 870 showing opening 845 formed in the Alumina layer.
  • Aluminum Germanium stack layer 830 and the Alumina layer are not shown in Figure 22B .
  • Figure 22B are Tungsten via plugs with TiN liner 855.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Micromachines (AREA)

Claims (8)

  1. Un Procédé de scellement d'un dispositif MEMS (120) formé dans une cavité (110) d'un premier substrat semi-conducteur (100) en utilisant un second substrat semi-conducteur (500), le procédé comprenant la formation d'une structure d'aluminium et germanium (250, 260) au-dessus du premier substrat (100) autour de la périphérie de la cavité (110), le procédé caractérisé par ;
    la formation d'une couche de polysilicium (530) au-dessus du second substrat (500) ;
    le fait de couvrir le premier substrat (100) avec le second substrat (500) de manière à amener la couche de polysilicium (530) à entrer en contact avec la structure d'aluminium et germanium (250, 260) ; et
    la réalisation d'une liaison eutectique entre les premier et second substrats (100, 500) de manière à amener la structure d'aluminium et germanium (250, 260) à fondre et former un produit de scellement AlGeSi pour sceller ainsi le dispositif MEMS (120).
  2. Le procédé selon la revendication 1 dans lequel ladite structure d'aluminium et germanium (250, 260) comprend une couche de germanium (260) recouvrant une couche d'aluminium (250).
  3. Le procédé selon la revendication 1 comprenant en outre la formation d'une couche adhésif (230) sous la structure d'aluminium et germanium (250, 260).
  4. Le procédé selon la revendication 3 comprenant en outre la formation d'une couche d'alumine (240) disposée entre la structure d'aluminium et germanium (250, 260) et la couche adhésif (230).
  5. Le procédé selon la revendication 3 dans lequel ladite couche adhésif (230) est une couche de nitrure de titane.
  6. Le procédé selon la revendication 1 comprenant en outre la formation d'une couche d'alumine (520) sous la couche de polysilicium (530) dans le second substrat (500).
  7. Le procédé selon la revendication 1 comprenant en outre la formation d'une couche de silicium polycristallin siliciuré (520) sous la couche de polysilicium (530) dans le second substrat (500).
  8. Le procédé selon la revendication 6 comprenant en outre la formation d'une couche adhésif (510) sous la couche d'alumine (520) dans le second substrat (500).
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US15/677,994 US10793427B2 (en) 2017-04-04 2017-08-15 Eutectic bonding with AlGe
PCT/US2018/026111 WO2018187490A1 (fr) 2017-04-04 2018-04-04 Liaison eutectique avec alge

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CN110709350B (zh) 2024-02-23
US20190263656A1 (en) 2019-08-29
US10766767B2 (en) 2020-09-08
WO2018187490A1 (fr) 2018-10-11
CN110709350A (zh) 2020-01-17
EP3606869A1 (fr) 2020-02-12
US20180282153A1 (en) 2018-10-04
JP2020515426A (ja) 2020-05-28
US20200048078A1 (en) 2020-02-13
EP3606869A4 (fr) 2021-01-06
JP7001707B2 (ja) 2022-01-20
US10793427B2 (en) 2020-10-06
US11724933B2 (en) 2023-08-15

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