EP3529828A1 - Method for the production of a microelectronic chip to be hybridised to a second chip - Google Patents
Method for the production of a microelectronic chip to be hybridised to a second chipInfo
- Publication number
- EP3529828A1 EP3529828A1 EP17792128.5A EP17792128A EP3529828A1 EP 3529828 A1 EP3529828 A1 EP 3529828A1 EP 17792128 A EP17792128 A EP 17792128A EP 3529828 A1 EP3529828 A1 EP 3529828A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- chip
- coefficient
- thermal expansion
- interest
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
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- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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Definitions
- the field of the invention is that of the assembly or hybridization of two microelectronic chips to one another, comprising the application of a so-called hybridization temperature.
- the invention relates more specifically to the production of a first microelectronic chip intended to be hybridized to a second microelectronic chip, as well as to a hybridization process of the two microelectronic chips.
- the invention finds an application in the assembly of chips of different materials, such as an optoelectronic chip comprising a matrix of light-emitting diodes or GaN-based photodiodes on a chip comprising a silicon-based readout circuit. .
- the microelectronic chips can be both electronic devices such as an integrated circuit for reading and / or processing electrical signals, as optoelectronic devices such as a matrix of light emitting diodes or photodiodes.
- the microelectronic chips are assembled at their respective connection face, on which each chip comprises a matrix of N * M electrical interconnection pads.
- the assembly method then comprises a step of aligning and contacting the interconnection pads, two by two, then a step of applying a so-called hybridization temperature, thereby achieving a mechanical link between the two. chips by fusion or inter-diffusion interconnection pads of one and / or the other microelectronic chip.
- the microelectronic chips Pi, P2 are first brought into contact with each other, so that the respective interconnection pads 12, 22 are aligned and superimposed two by two, and put in contact.
- the interconnection pads 12, 22 are here spaced from each other on a periodic basis following a step p.
- the interconnection pads 22 of the second chip P2 comprise a fusible material, for example based on indium or another metal or alloy, such as a eutectic SnAg or SnAgCu alloy, and the dots interconnection 12 of the first chip Pi are made of a material wettable by the fuse material when the latter is in the liquid phase.
- the chips Pi, P2 are then subjected to the hybridization temperature ⁇ greater than or equal to the melting temperature of the fusible material of the interconnection pads 22 of the second chip P2. for example at 220 ° C.
- a relative misalignment AL of the interconnection pads 12, 22 may then appear due to the difference between the thermal expansion coefficients of the two chips Pi, P2.
- the relative misalignment AL can reach half of the pitch p, here about 25 ⁇ or more.
- the relative misalignment can lead, especially in the case of small steps and large interconnect matrices, to a loss of mechanical contact and therefore to a lack of electrical connection between the respective interconnection pads.
- the invention aims to remedy at least in part the disadvantages of the prior art, and more particularly to provide a method for producing a first microelectronic chip to be hybridized to a second microelectronic chip so that that, during the subsequent hybridization phase, the relative misalignment between the respective interconnection pads is less than a predetermined threshold value.
- the object of the invention is a method of producing a first microelectronic chip comprising a so-called layer of interest having a first face, said connection, on which are located electrical interconnect pads , and having a coefficient of thermal expansion a c i, and intended to be assembled at a so-called hybridization temperature Th, a second microelectronic chip, having a second face, called connection, on which are located pads electrical interconnection, and having a coefficient of thermal expansion o P2 , said apparent, at the second connecting face, lower than the coefficient of thermal expansion a c i.
- the method comprises the following steps:
- a layer of glue on one face of the layer of interest opposite to the first connection face, said glue layer having a thickness e cc less than or equal to a predetermined maximum value e TM ax , and a modulus d Young E cc between minimum values E TM in and maximum Ej3 ⁇ 4 ax predetermined;
- a so-called handle layer on the adhesive layer said handle layer having a thickness e cp greater than or equal to a minimum value e3 ⁇ 4 in predetermined, and a coefficient of thermal expansion a cp less than or equal to the apparent coefficient of thermal expansion P2 ;
- the method may comprise a step of determining a maximum value ap ax of the apparent thermal expansion coefficient P1 of the first chip at the first connection face, for which the relative misalignment AL is substantially equal to the predetermined threshold value AL max .
- the interconnection pads may be distributed periodically with a pitch p, and the predetermined threshold value AL max may be less than or equal to p / 2.
- the adhesive layer may have a coefficient of thermal expansion a cc greater than that a c i of the layer of interest and that a cp of the handle layer.
- the method may comprise a prior step of growth of the layer of interest from a growth substrate made of a material having a coefficient of thermal expansion greater than the apparent thermal expansion coefficient ô P2 of the second chip.
- the layer of interest of the first chip may comprise light emitting diodes or photodiodes.
- the layer of interest of the first chip may be made based on a III-V semiconductor compound or a semiconductor compound II-VI.
- the second chip may comprise a said support layer and an IC layer located between the second connection face and the support layer, the apparent thermal expansion coefficient OC P2 being substantially equal to the thermal expansion coefficient of the support layer.
- the support layer may be made of silicon.
- the adhesive layer may have a thickness e cc less than or equal to 4 times the thickness e c i of the layer of interest.
- the adhesive layer may have a Young's modulus E cc between MPa and 40GPa.
- the thickness e cp of the handle layer may be greater than or equal to 20 times the thickness e c i of the layer of interest.
- the invention also relates to a hybridization method of a first microelectronic chip with a second microelectronic chip having a second face, said connection, on which are located electrical interconnect pads, and having a coefficient of thermal expansion ⁇ c P2 , said apparent, the method comprising the following steps:
- hybridization T h Hybrid the first and second chips to each other at the temperature value called hybridization T h .
- FIGS. 1A and 1B are schematic and partial sectional views of a step of contacting the microelectronic chips so that the interconnection pads are in pairs (fig.iA), and a step of temperature rise up to the hybridization value Th, illustrating the relative misalignment of the interconnection pads (fig.iB);
- FIG. 2 is a flowchart of a method for producing a first microelectronic chip intended to be hybridized at the hybridization temperature Th to a second microelectronic chip;
- FIG. 3 illustrates an example of a change in the value of the apparent thermal expansion coefficient F1 of the first chip at its connection face as a function of the number N ⁇ N of interconnection pads;
- FIGS. 4A to 4C illustrate examples of changes in the value of the apparent thermal expansion coefficient F1 of the first chip at its connection face as a function of the thickness e cs of the support layer (FIG. , the thickness e cc of the adhesive layer (fig.4B), and the dYoung module E cc of the adhesive layer (fig.4C);
- FIGS. 5A to 5I are schematic and partial sectional views of different steps of a preparation of a layer of interest, of making a first microelectronic chip comprising the layer of interest according to the method illustrated in FIG. fig.2, then hybridization of the first microelectronic chip to a second microelectronic chip.
- the invention relates to a method for producing a first microelectronic chip intended to be hybridized to a second microelectronic chip at a temperature of hybridization Th greater than room temperature.
- Hybridization means an assembly of two microelectronic chips so as to ensure a mechanical attachment of the chips to each other, as well as an electrical connection.
- the microelectronic chips may include integrated circuits and / or optically active elements such as light emitting diodes or photodiodes.
- the first chip is an optoelectronic chip comprising a matrix of light emitting diodes or photodiodes
- the second microelectronic chip comprises an integrated circuit forming a read circuit for applying a control or reading signal to the light-emitting diodes or photodiodes.
- a chip may be made from a semiconductor plate, or w afer, and have dimensions of width, length or diameter, substantially equal to those of the semiconductor plate. It may also have dimensions smaller than those of the semiconductor plate.
- Each microelectronic chip may comprise one or more layers of different materials each having a coefficient of thermal expansion proper.
- the coefficient of thermal expansion of a material expresses the relative elongation (l 2 -li) / li of the material for a given temperature difference T 2 -Ti.
- a (1 2 - li) / (Li (T 2 - Ti)), where h is the length of the material at temperature ⁇ , and 1 2 is the length at temperature T 2 greater than T
- the coefficient of apparent thermal expansion at the level of a given face of the chip is defined as being the relative elongation ( ⁇ 2 -i 1) / ù of the chip at the level of the face considered for the given temperature difference T 2 -T x .
- at (I 2 - Ii) / (Ii - (T 2 - ⁇ )), where and I 2 are here the lengths measured at the level of the considered face.
- the coefficient of apparent thermal expansion can therefore be measured simply at the level of the considered face of the chip.
- the coefficient of apparent thermal expansion of a chip differs from the average thermal expansion coefficient of the chip, which essentially corresponds to a weighting of the coefficients of thermal expansion of each layer of the chip according to their volume fraction, thickness and / or elasticity coefficients (Young's modulus and Poisson's ratio).
- a layer or a chip is said to be made based on a material when its average thermal expansion coefficient is substantially equal to the coefficient of thermal expansion of the material.
- a layer comprising a plurality of light-emitting diodes made of GaN may comprise electrical insulation portions of the diodes between them made of a dielectric material, for example an oxide or a silicon nitride. Such a layer is then said to be made based on GaN when its average expansion coefficient is substantially equal to that of GaN.
- the first and second microelectronic chips each comprise NxM electrical interconnection pads by which the mechanical assembly and the electrical connection between the chips are intended to be obtained.
- N and M values may be the same or different.
- the NxM interconnection pads are located on a connection face of the chip, and are spaced from each other, preferably periodically in a pitch p.
- the pitch p is here considered identical along the axis of N pads and following that of the M pads, but it may be different. They are made of at least one electrically conductive material.
- the interconnection pads of the first chip and / or the second chip, here of the second chip comprise a fusible material whose melting temperature is less than or equal to the hybridization temperature. For example, they may be indium balls or SnAgCu (SAC), or their alloys.
- SAC SnAgCu
- the invention relates primarily to a method of producing a first microelectronic chip so that, when hybridized to a second microelectronic chip, the interconnect pads have a relative misalignment less than or equal to a predetermined threshold value .
- relative misalignment is meant the distance, in the plane parallel to the connection faces, between the center, or center of gravity, of an interconnection pad of the first chip with respect to the center, or barycenter of the pad of interconnection of the second chip with which it was initially aligned.
- FIG. 2 is a flowchart of a method for producing a first microelectronic chip Pi intended to be hybridized to a second microelectronic chip P2 at a hybridization temperature Th, such as that described with reference to FIGS. 5A to 5I. .
- the first chip Pi comprises a layer 13, said to be of interest, having a coefficient of thermal expansion a c i, a thickness denoted e c i, and a dYoung module E c ;.
- the layer of interest 13 is made based on a material of interest, here a crystalline semiconductor material.
- the coefficient a c i of the layer of interest 13 is substantially equal to the coefficient of thermal expansion of the material of interest.
- the material of interest may be a III-V semiconductor compound, that is to say comprising elements III and elements of the elements V of the periodic table, for example GaN, or a compound semiconductor II-VI, or even an IV semiconductor compound such as germanium. It may extend continuously in the plane of the layer and over all or part of the thickness of the layer, or alternatively may extend to form portions or areas distinct from each other.
- the first chip Pi is an optoelectronic chip whose layer of interest 13 comprises a matrix of light-emitting diodes made of GaN (not shown).
- the light emitting diodes may have a structure identical or similar to that described in the patent application FR3023061, or that described in the publication of Fan et al entitled III-n itride m icro-itter arrays developm ent and applications, J. Phys . D: Appl. Phys. 41 (2008) 094001.
- the first chip Pi comprises a so-called connection face 11 at which is located a matrix of NxM pads 12 of electrical interconnection.
- the interconnection pads 12 are spaced from one another, preferably periodically in a p-spacing.
- the second microelectronic chip P2 has a second face 21 said connection on which is located a matrix of NxM pads 22 of electrical interconnection.
- the interconnection pads 22 here comprise a fusible material at the hybridization temperature ⁇ , and are spaced from each other in a manner identical to the pads 12 of the chip P1.
- the chip P2 has a coefficient of thermal expansion, said apparent, noted ôc P2 , defined at the connection face 21.
- the chip P2 comprises a so-called support layer 24 having a thickness e cs and made of a material having a coefficient of thermal expansion a cs .
- the support layer 24 may be a substrate, or w afer, with a thickness of 725 ⁇ .
- the coefficient of thermal expansion a cs is then approximately 2.6.1 ⁇ 6 K 1 .
- the chip P2 may comprise other layers than the support layer 24, in particular a so-called integrated circuit layer 23 formed of an electrically insulating material, for example a dielectric material such as S102, in which electrical connection lines (not shown) of an electrically conductive material, for example a metallic material.
- This integrated circuit layer 23 is located between the connection face 21 and the support layer 24.
- the second chip P2 is made based on the material of the support layer 24, so that it has an apparent coefficient of thermal expansion ⁇ c P2 , at the level of the connecting face 21, substantially equal to the coefficient of thermal expansion a cs of the support layer 24, in other words: öc P2 ⁇ a cs .
- the apparent coefficient of thermal expansion ⁇ c P2 of the chip P2 is smaller than the coefficient of thermal expansion a c i of the layer of interest 13 of the chip Pi.
- the coefficient a c i is of the order of 5.6.1 ° 6 K 1 for a GaN-based layer of interest 13
- the apparent coefficient ⁇ c P2 is of the order of 2.6 ⁇ 6 K 1 for a P2 chip based on silicon.
- it is sought to mechanically constrain the layer of interest 13 of the chip Pi to control and limit the relative misalignment AL of the interconnection pads 12 vis-à-vis those 22 of the chip P2.
- thermomechanical properties of the layer of interest 13 of the chip Pi on the one hand and those of the second chip P2 on the other hand.
- a second step consists in determining a maximum threshold value AL max of relative misalignment AL between the interconnection pads 12 of the chip Pi and the interconnection pads 22 of the chip P2, so as to limit or even eliminate the risks. loss of mechanical contact and therefore electrical between the interconnection pads.
- This maximum threshold value AL max depends in particular on the spacing between the interconnection pads 12, 22 adjacent to the same connection face 11, 21.
- the maximum threshold value AL max of relative misalignment AL may be less than or equal to p / 2, and preferably be less than or equal to p / 4.
- the pads may have an average dimension, in the XY plane, substantially equal to p / 2.
- the maximum threshold value AL max of relative misalignment AL may be less than or equal to the average dimension of the pads, for example equal to p / 2, and preferably be less than or equal to half the average dimension of the pads, for example equal to p / 4.
- dimension of a pad is meant the dimension of width or length of the stud, or diameter, along an axis passing through the N or M interconnect pads.
- the maximum threshold value AL max may be expressed in terms of the thermal expansion coefficient apparent to Fl of the chip Pi at its connection face 11.
- the maximum threshold value AL max of relative misalignment is reached for a maximum value ⁇ ? ⁇ the apparent coefficient of expansion ⁇ ⁇ ⁇ of the chip Pi at its connection face 11, according to the relationship: ⁇ ** ⁇ 2.AL max /(L.AT) + a P2 .
- FIG. 3 illustrates an example of a relationship between the coefficient of thermal expansion apparent at F1 of the chip Pi at its connection face 11 as a function of the number N ⁇ N of interconnect pads, for a maximum threshold value AL max. substantially equal to p / 4, and for a temperature difference of ⁇ of about 200 ° C.
- the dashed line represents the coefficient of thermal expansion apparent P2 of the chip P2, here substantially equal to 2.6.1 6 K 1 for a chip P2 made of silicon.
- the maximum value at x is about 3.10 6 K 1 .
- a third step is to determine threshold values of dimensional and thermomechanical characteristics of the chip Pi, which is then formed of the layer of interest 13 to which is attached a layer 15, said handle, by means of an intermediate adhesive layer 14, so that, during the hybridization of the chips Pi and P2, the relative misalignment AL is substantially equal to the maximum threshold value AL max .
- the apparent expansion coefficient Pl of the chip Pi is then substantially equal to the maximum value at x .
- the handle layer 15 is made of a material, preferably identical to that of the support layer 24 of the chip P2, so that:
- a cp is less than or substantially equal to, and preferably substantially equal to, the coefficient of thermal expansion apparent P2 of the chip P2;
- the adhesive layer 14 has the following characteristics:
- the coefficient of thermal expansion a cc has a value which may be greater, at least 10 times or even twenty times, than that of the layer of interest 13 and of the handle layer 15.
- Determining the minimum thickness e TM in of the handle layer 15 on the one hand, and the maximum value ej3 ⁇ 4 ax and the minimum values E TM in and maximum E TM ax of the adhesive layer 14 of on the other hand, can be realized by a parametric study carried out by numerical simulation, in particular by means of the software ANSYS® simulating the thermomechanical behavior of the Pi chip modelized by finite elements.
- FIGS. 4A to 4C are examples illustrating the influence of said variables on the apparent expansion coefficient P1 of the chip Pi.
- the chip P2 is made of silicon, and has a coefficient of expansion.
- thermal apparent P2 of 2.6.1 ⁇ 6 K 1 .
- the chip Pi comprises a layer of interest 13 made of GaN, and has a coefficient of thermal expansion a c i equal to 5.6.1 ⁇ 6 K 1 approximately, a thickness e c i of approximately 5 ⁇ , a dYoung module E c ; equal to about 3 oGPa and a Poisson's ratio v c i equal to about 0.33.
- the adhesive layer 14 has a coefficient of thermal expansion a cc equal to 86.10 6 K 1 approximately, a thickness e cc whose maximum value is to be determined, a dyoung Ecc module whose minimum and maximum values are to be determined, and a coefficient approximately 0.35 Poisson, here in the case of an epoxy glue, for example an EPO-TEK adhesive E360.
- the handle layer 15 is made of silicon. It has a coefficient of thermal expansion a cp equal to 2.6.1 ⁇ 6 K 1 approximately, a thickness e cp whose minimum value is to be determined, a Young modulus E cp equal to approximately i30GPa, and a Poisson's ratio of About 0.28.
- the hybridization of a chip Pi to a chip P2 by 4000 ⁇ 4000 interconnection pads at a hybridization temperature of 200 ° C., ie a ⁇ about 200 ° C, with a relative misalignment less than or equal to the pitch p / 4, implies that the chip Pi has an apparent coefficient of expansion ⁇ ⁇ ⁇ less than or equal to a maximum value at ⁇ x equal to 3.1er 6 K 1 about.
- FIG. 4A illustrates the influence of the thickness e cp of the handle layer 15 on the value of the apparent expansion coefficient ⁇ ⁇ ⁇ of the chip Pi at the connection face 11, in the case where the adhesive layer 14 has a thickness of 2.5 ⁇ and a Young's modulus of 2.8GPa at room temperature.
- the maximum value at x x of 3.1 6 6 K 1 of the apparent coefficient of thermal expansion at P1 of the chip Pi is reached for a minimum value e n of the handle layer 15 of approx.
- the relative misalignment AL will be less than or equal to the predetermined threshold value, namely here p / 4.
- FIG. 4B illustrates the influence of the thickness e cc of the adhesive layer 14 on the value of the apparent expansion coefficient ⁇ ⁇ ⁇ of the chip Pi at the face 11, in the case where the layer handle 15 has a thickness of 3 ⁇ and where the adhesive layer 14 has a Young's modulus of 2.8GPa.
- the maximum value 3.1er 6 K 1 of the apparent thermal expansion coefficient Pi of the chip Pi is reached for a maximum value e3 ⁇ 4 ax of the adhesive layer 14 of ⁇ approximately.
- the relative misalignment AL will be less than or equal to the predetermined threshold value, namely here p / 4.
- FIG. 4C illustrates the influence of the Young's modulus E cc of the adhesive layer 14 on the value of the apparent expansion coefficient 3 ⁇ 4 i of the chip Pi at the face 11.
- the handle layer 15 has a thickness of approximately 3 ⁇ and the adhesive layer 14 has a thickness of approximately 2.5 ⁇ .
- the inventors have shown that, in general, the value of the apparent coefficient of thermal expansion Pi of the chip Pi at the connection face 11 is less than or equal to the maximum value at x when the value of the Young modulus Ecc of the adhesive layer 14 belongs to an interval delimited by minimum values E TM in and maximum E TM ax , the terminals being included.
- a fourth step consists in depositing the adhesive layer 14 on the face 13a of the layer of interest 13 opposite to the connection face 11, and then fixing the handle layer 15 on the adhesive layer 14.
- the adhesive layer 14 is chosen so that on the one hand its thickness e cc is less than or equal to the maximum value ej3 ⁇ 4 ax previously determined, and on the other hand that its dYoung module E cc is between the values minimum E TM n and maximum Ej3 ⁇ 4 ax previously determined.
- the handle layer 15 is chosen so that on the one hand its thickness e cp is greater than or equal to the minimum value e TM n previously determined, and secondly that its coefficient of thermal expansion a cp is lower or equal to the apparent coefficient ⁇ c P2 of the chip P2.
- the adhesive layer 14 may have a coefficient of thermal expansion a cc greater than the coefficient a c i of the layer of interest 13 and the coefficient a cp of the handle layer 15.
- a cc coefficient of thermal expansion
- the adhesive layer 14 may have a coefficient of thermal expansion a cc greater than the coefficient a c i of the layer of interest 13 and the coefficient a cp of the handle layer 15.
- the adhesive layer 14 has a thickness e cc less than or equal to 4 times the thickness e c i of the layer of interest 13, and preferably less than or equal to 2 times this thickness e c i. It is also advantageous for the adhesive layer 14 to have a Young's modulus E cc of between PMa and 4oGPa. In addition, it is advantageous for the thickness e cp of the handle layer 15 to be at least 20 times greater than the thickness e c i of the layer of interest 13. A relative misalignment of less than or equal to p / 2 is then obtained between the chips Pi and P2 each having NxM interconnection pads, the maximum value between N and M being less than or equal to about 4000.
- FIGS. 5A to 5I are schematic and partial sectional views of an exemplary hybridization method of a first microelectronic chip Pi with a second microelectronic chip P2, comprising steps of preparation and realization of the first Pi chip.
- a three-dimensional direct reference ( ⁇ , ⁇ , ⁇ ) is defined here, where the X and Y axes form a plane parallel to the main plane of the layer of interest 13, and where the Z axis is oriented substantially orthogonal to the main plane of the layer of interest 13.
- the terms “vertical” and “vertically” extend as being relative to an orientation substantially parallel to the axis.
- Z and the terms “horizontal” and “horizontally” as being relative to an orientation substantially parallel to the plane (X, Y).
- growth of the layer of interest 13 is carried out from a growth substrate 16.
- the growth can be carried out by epitaxy, for example by the organometallic vapor phase (MOCVD, for MetalOrgan ic Chem ical Vapou r Deposition, in English).
- MOCVD MetalOrgan ic Chem ical Vapou r Deposition
- the growth substrate 16 may have a coefficient of thermal expansion greater than that of the layer of interest 13.
- the growth substrate 16 may be sapphire (Al2O3), whose coefficient of thermal expansion is equal to 7.5.1 ⁇ 6 K 1 .
- a matrix of light-emitting diodes (not shown) is produced, for example according to the method described in the application FR3023061.
- the NxN or NxM interconnection pads 12 are then made on the connection face 11 of the layer of interest 13.
- the interconnection pads 12 are here portions of an electrically conductive and transparent material, such as ⁇ , electrically connected to the light emitting diodes.
- a temporary adhesive layer 17 is deposited, for example an epoxy adhesive, so as to cover the connection face 11 of the layer of interest 13, and then a temporary handle layer 18 is fixed, for example a substrate or w afer, silicon or a material whose coefficient of thermal expansion is close to that of the Si (FIG 5B).
- the growth substrate 16 is removed, for example by laser (LLO, for Laser Lift-Off, in English) or by abrasion and chemical mechanical polishing (CMP, for Chem ical Mechan ical Polishing, in English) (fig. BSc).
- LLO Laser Lift-Off
- CMP chemical mechanical polishing
- the adhesive layer 14 may be a thick epoxy adhesive. About 2.5 ⁇ and a dYoung module of 2.8GPa.
- the handle layer 15 is made of silicon and has a thickness of 3 ⁇ , or even 725 ⁇ in the case of a w afer of silicon.
- connection face 11 of the Pi chip and the interconnection pads 12 (fig.sF).
- the two chips Pi and P2 are brought into contact so that the interconnection pads 12, 22 of each chip are two by two, aligned and superimposed, and in mutual contact.
- the chip P2 is made of silicon. It comprises a layer 23 of integrated circuit at its connection face 21 forming a read circuit, which rests on a support layer 24 of silicon with a thickness here of 725 ⁇ . It further comprises interconnection pads 22 formed in particular of a fusible material at the temperature of hybridization Th. A rise in temperature is then applied, from the ambient temperature T a to the temperature of hybridization Th. thus merging the interconnection pads 22 of the chip P2. The hybridization of the two chips Pi, P2 at the interconnection pads 12, 22 is then obtained during the cooling of the chips.
- a suppression of the support layer 24 may be envisaged if the integrated circuit layer 23, associated with the chip Pi, has a thickness sufficient to ensure good mechanical strength of the stack. Thinning facilitates heat dissipation. We can also remove the handle layer 15 and the adhesive layer 14 of the chip Pi (fig.51). A stack of an optoelectronic chip Pi and an electronic chip P2 with a read circuit are thus obtained, whose relative misalignment AL between the interconnection pads 12, 22 is less than or equal to a predetermined threshold AL max , thus limiting the mechanical and therefore electrical contact faults. In addition, in this example, the stack has a relatively low overall thickness, which makes it possible to improve the thermal evacuation of the heat produced by the optoelectronic chip.
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Abstract
Description
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Application Number | Priority Date | Filing Date | Title |
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FR1660118A FR3057706B1 (en) | 2016-10-19 | 2016-10-19 | METHOD FOR PRODUCING A MICROELECTRONIC CHIP FOR HYBRIDING A SECOND CHIP |
PCT/FR2017/052828 WO2018073517A1 (en) | 2016-10-19 | 2017-10-16 | Method for the production of a microelectronic chip to be hybridised to a second chip |
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EP3529828A1 true EP3529828A1 (en) | 2019-08-28 |
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EP17792128.5A Withdrawn EP3529828A1 (en) | 2016-10-19 | 2017-10-16 | Method for the production of a microelectronic chip to be hybridised to a second chip |
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US (1) | US11165005B2 (en) |
EP (1) | EP3529828A1 (en) |
FR (1) | FR3057706B1 (en) |
WO (1) | WO2018073517A1 (en) |
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US11569091B2 (en) * | 2019-05-07 | 2023-01-31 | Meta Platforms Technologies, Llc | Hybrid-bonded and run-out compensated light emitting diodes |
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JP2827414B2 (en) * | 1990-03-15 | 1998-11-25 | 富士通株式会社 | Semiconductor device |
JPH0536966A (en) * | 1991-07-19 | 1993-02-12 | Fujitsu Ltd | Semiconductor device |
JP3114759B2 (en) * | 1992-03-13 | 2000-12-04 | 富士通株式会社 | Semiconductor device |
US7786592B2 (en) * | 2005-06-14 | 2010-08-31 | John Trezza | Chip capacitive coupling |
US7671460B2 (en) * | 2006-01-25 | 2010-03-02 | Teledyne Licensing, Llc | Buried via technology for three dimensional integrated circuits |
US7592594B2 (en) | 2006-11-13 | 2009-09-22 | Raytheon Company | Method of construction of CTE matching structure with wafer processing and resulting structure |
FR2982415B1 (en) | 2011-11-09 | 2014-06-13 | Commissariat Energie Atomique | PROCESS FOR OBTAINING SUBSTRATE FOR MANUFACTURING SEMICONDUCTOR AND CORRESPONDING SUBSTRATE |
JP6003283B2 (en) * | 2012-06-21 | 2016-10-05 | 富士通株式会社 | Infrared detector manufacturing method and infrared detector |
FR3023061B1 (en) | 2014-06-27 | 2017-12-15 | Commissariat Energie Atomique | MESA STRUCTURE DIODE WITH SUBSTANTIALLY PLANE CONTACT SURFACE |
-
2016
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2017
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US11165005B2 (en) | 2021-11-02 |
US20200058837A1 (en) | 2020-02-20 |
FR3057706B1 (en) | 2018-12-07 |
WO2018073517A1 (en) | 2018-04-26 |
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