EP3382567B1 - Dispositifs de stockage multiples mis en uvre à l'aide d'un connecteur commun - Google Patents

Dispositifs de stockage multiples mis en uvre à l'aide d'un connecteur commun Download PDF

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EP3382567B1
EP3382567B1 EP18154453.7A EP18154453A EP3382567B1 EP 3382567 B1 EP3382567 B1 EP 3382567B1 EP 18154453 A EP18154453 A EP 18154453A EP 3382567 B1 EP3382567 B1 EP 3382567B1
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Prior art keywords
interface protocol
bus
bus interface
connector
implementing
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German (de)
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EP3382567A1 (fr
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Deniel S. WILLIS
Anthony M. Constantine
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0032—Serial ATA [SATA]

Definitions

  • Embodiments described herein generally relate to computing devices, systems and methods including the use of storage implemented through a connector.
  • a computational device may be coupled to one or more physical storage devices in which data may be stored.
  • the computational device may communicate with a physical storage device over a bus such as a PCIe (Peripheral Component Interconnect Express bus, (see http://www.pcsig.com)), and a variety of interfaces to different type of storage devices, such as SATA (Serial ATA) drives (see http://www.sata-ip.org) and NVMe (Non-Volatile Memory Express) drives (see http://www.nvmexpress.org).
  • SATA Serial ATA
  • NVMe Non-Volatile Memory Express
  • System designers have typically predetermined the allocation of storage and connections thereto at the time of board design.
  • EP 2 559 225 is disclosing selecting functions to be enabled for connecting host device to the accessory device based on the received accessory device information.
  • an input/output (IO) buffer may be used to allocate HSIO (high speed IO) for various usages such as, for example, USB (Universal Serial Bus), PCIe, and SATA.
  • HSIO high speed IO
  • a variety of storage connection specifications for coupling a storage device to a motherboard may be utilized, including a mix of SATA connectors, M.2 connectors, and U.2 connectors.
  • SATA 3.0 Serial ATA Revision 3.0 Specification (released June 2009), operates at 6 Gb/s (Gigabits/second) or 600 MB/s (Megabytes/sec).
  • NVMe over M.2 or U.2 (using PCIe 3.0 (PCI Express Base Specification Revision 3.0 (released Nov.
  • the U.2 connector originally known as SFF-8639 (Enterprise SSD Form Factor Version 1.0 (released Dec. 20, 2011), comprises a connector that is mechanically identical to the SATA Express device plug, but provides four PCIe lanes through a different usage of available pins.
  • the M.2 specification e.g., PCI Express M.2 Specification Revision 1.0 (released Nov. 1, 2013)
  • PCI Express M.2 Specification Revision 1.0 released Nov. 1, 2013
  • M.2 connector provides up to four PCIe lanes and one logical SATA 3.0 (6 Gbit/s) port, and exposes the PCIe and SATA lanes through the same connector so both PCIe and SATA storage devices may exist in form of M.2 modules.
  • Fig. 1 illustrates a system in accordance with certain embodiments, including a computational device 10 that communicates with a storage device 26 coupled to the system through a cable 24 coupled to a connector 22.
  • the computational device 10 may include a central processing unit (CPU) 12 and main memory 14. Communication between the CPU 12 and the storage device 26 and the connector may be carried out over a bus interface 16 coupled to the connector 22.
  • the I/O buffer 20 may be used to allocate buffers, such as HSIO buffers, for various bus protocols such as USB, PCIe, and SATA.
  • the computational device 10 further includes initialization logic (including, for example, firmware such as a basic input output system (BIOS)) 28 that initializes the hardware and devices connected to the bus 16 and in the system 10.
  • initialization logic including, for example, firmware such as a basic input output system (BIOS)
  • the initialization logic 28 may in certain embodiments be provided on an integrated circuit die, an application specific integrated circuit (ASIC), and/or a processor executing software stored in a non-volatile memory device.
  • the initialization logic 28 may dynamically detect which type(s) of storage drive(s) are coupled to the cable 24 at the time of system boot.
  • Figs. 2a and 2b illustrate a flow chart of operations for detecting the type of storage device(s) attached to a system at the time of system boot.
  • the initialization logic 28 begins (at block 103) bus 16 initialization, which includes PCIe training of a first four lane HSIO group.
  • a bus using the PCIe protocol may be a high speed I/O bus in which multiple lanes of the bus may combine their data transfer capability to send the read or write command from the host to the storage device.
  • a bus using the SATA protocol may include use of a high-speed serial cable (e.g., cable 24) to send the read or write command from the host to the storage device.
  • an interface capable of interfacing with buses using both SATA and PCIe protocols may be arranged to route the read or write commands from a computational device to a storage device via the high speed serial cable.
  • the initialization logic 28 determines (at block 105) whether a PCIe device is detected.
  • the initialization logic 28 turns off (at block 107) the PCIe clock 18 and reprograms (at block 109) the I/O buffer 20 as SATA on four ports (one for each of the lanes in the first four lanes 20a, 20b, 20c, 20d in an HSIO group).
  • the initialization logic 28 detects (at block 111) whether any SATA drives 26 are present. If (at block 111) no SATA drives 26 are present, then the initialization logic 28 turns off (at block 115) the HSIO buffers 20 and then proceeds to configure (at block 117) the next four lane HSIO group for initialization.
  • the initialization logic 28 finishes (at block 119) initializing the storage device(s) 26 as SATA. Once the device(s) 26 are initialized, the initialization logic 28 turns-off (at block 121) any unused HSIO buffers. Then, the initialization logic 28 proceeds (at block 117) to processing (at block 103) the next four lane HSIO group for training and initialization.
  • the initialization logic 28 determines (at block 123) whether the detected PCIe device uses four lanes. It is possible in certain configurations that a non-storage PCIe device may be detected As a result, if a PCIe device is detected, the initialization logic 28 determines (at block 141) whether the detected PCIe device is an NVMe storage device. If not, then the initialization logic 28 completes (at block 145) initialization of the non-storage PCIe device, and proceeds (at block 117) to the next four lane HSIO group for training and initialization block 103. If (at block 141) there is a NVMe storage device detected as storage device 26, then the initialization logic 28 finishes (at block 145) initializing the detected NVMe storage device 26 connected to four lanes of the cable 24 as a PCIe device.
  • the initialization logic 28 determines (at block 125) whether the device uses two lanes of the cable 24. If the device does not use two lanes, then the initialization logic 28 determines (at block 127) whether the device is a NVMe storage device. If the device is not an NVMe storage device, then the initialization logic 28 completes (at block 129) initialization of the non-storage PCIe device. Then the initialization logic 28 (at block 137) reprograms any remaining HSIO buffers as SATA.
  • the initialization logic 28 (at block 131) completes initializing the NVMe storage device connected to one lane of the cable 24 as a PCIe device. Then, the initialization logic 28 (at block 137) reprograms any remaining HSIO buffers as SATA.
  • the initialization logic 28 determines whether the device is an NVMe storage device. If the device is not an NVMe storage device, then the initialization logic 28 (at block 129) completes initialization of the non-storage PCIe device. Then the initialization logic 28 (at block 137) reprograms any remaining HSIO buffers as SATA. If the device uses two lanes and is a NVMe storage device, then the initialization logic 28 (at block 135) completes initializing the NVMe storage device connected to two lanes of the cable 24 as a PCIe device. Then, the initialization logic 28 (at block 137) reprograms any remaining HSIO buffers as SATA.
  • the initialization logic 28 (at block 137) reprograms the remaining HSIO buffers as SATA, the initialization logic 28 (at block 139) determines whether at least one SATA drive is detected. If yes, then the initialization logic 28 (at block 119) completes initializing the device(s) as SATA. Once the device(s) are initialized, the initialization logic 28 (at block 121) turns off any unused HSIO buffers. Then, the initialization logic 28 (at block 117) moves on to the next four lane HSIO group for training and initialization (at block 103).
  • the initialization logic 28 determines whether the device is an NVMe storage device. If the device using four lanes is an NVMe storage device, then the initialization logic 28 (at block 145) completes initializing the NVMe device connected to four lanes of the cable 24 as a PCIe device. Then, the initialization logic 28 (at block 117) moves on to the next four lane HSIO group for training and initialization (at block 103). If the device using four lanes is not an NVMe storage device, then the initialization logic 28 (at block 143) completes initializing the NVMe device connected to four lanes of the cable 24 as a PCIe device. Then, the initialization logic 28 (at block 117) moves on to the next four lane HSIO group for training and initialization (at block 103).
  • Certain embodiments enable one to resolve storage connector limitations by dynamically detecting and configuring a plurality of computer storage architectures. This enables the system to determine which type of storage device is coupled to the system through a connector and cable during the system boot operation.
  • One embodiment enables the use of SATA and/or NVMe drives coupled to a system through either U.2 or M.2 connectors and cables.
  • the initialization logic tests for the presence of PCIe drives and if PCIe drives are detected, then the boot continues with the PCIe drive (NVMe drive) operational. If no PCIe drives are detected, then the PCIe clock for either a U.2 or M.2 connector is turned off, and the IO buffer is reprogramed to assume SATA protocols are used on all the HSIO lanes in the group of HSIO lanes being tested.
  • any SATA drives (assuming a U.2 or M.2 connector and a U.2 or M.2 cable having a SATA connector at the drive end) are detected and if present, boot operations continue with the SATA drives initialized and made operational. If no PCIe drives and no SATA drives are detected, then the boot operation continues with no drives in the selected HSIO lanes.
  • Certain embodiments also relate to a cable that may be used to couple SATA drives to a system having a U.2 or M.2 connector thereon.
  • conventional systems may utilize, for example, four SATA connectors to couple four SATA drives thereto
  • certain embodiments may utilize, for example, a single U.2 or M.2 connector to couple one, two, three, or four SATA drives to the system.
  • the same U.2 or M.2 connector may be used to couple a NVMe drive to the system through a U.2 or M.2 cable having an NVMe connector at the drive end.
  • Such embodiments permit a system integrator and/or end user to be able to dynamically choose which type of cable and hard drives to populate in a system, whereas other systems require predetermined cable and hard drive selection.
  • Certain embodiments relating to systems utilizing SATA drives and NVMe drives are illustrated in Figs. 3-5 .
  • Fig. 3 illustrates a system including a circuit board 208 such as a motherboard, on which one or more processors 212 and one or more memory regions 214 may be positioned.
  • the board 208 also includes a board connector 222 for coupling one or more drives thereto.
  • the board 208 may also include other features (not shown), such as board management hardware and routing, and other external input/output connections such as, for example, Ethernet connections, USB connections, and video connections.
  • the connector 222 may, in certain embodiments, be selected from a U.2 connector and an M.2 connector.
  • the connector 222 may utilize four lanes for data transfer.
  • a cable 224 is coupled to the connector 222.
  • the cable 224 includes a first end attached to the connector and a second end that includes four fingers 224a, 224b, 224c, and 224d each extending to a SATA drive connector 228 for attaching to a SATA drive 226.
  • the first end of the cable 224 may be configured to mate with a U.2 connector or an M.2 connector, while the second end is configured to mate with one or more SATA drives.
  • the SATA drives may utilize one HSIO lane for input/output, and the U.2 or M.2 connector may utilize four HSIO lanes.
  • the cable 224 may include up to four SATA drives 226 coupled thereto.
  • Fig. 4 illustrates a system including the same circuit board 208 as in Fig. 3 , with the same components thereon including the same board connector 222.
  • the connector is a U.2 or an M.2 connector
  • a single NVMe drive 227 may be coupled to the connector 222 through the cable 225, which includes a first end configured to mate with the U.2 or M.2 connector 222, and the other extending to an NVMe drive connector 229 (e.g., SFF-8639 connector) configured to mate with the NVMe drive 227.
  • the NVMe drive 227 may utilize four HSIO lanes for input/output, and as a result, a single NVMe 227 drive is connected to the cable 225.
  • FIG. 5 illustrates a system including the same circuit board 208 as in Figs. 3-4 , with the same components thereon including the same board connector 222.
  • the first end of the cable 231 may be configured to mate with a U.2 connector or an M.2 connector, while the second end is configured to mate with a SATA drive 226 and a NVMe drive 227.
  • the cable 231 includes a second end having two fingers 231a and 231b, with finger 231a including a NVMe drive connector 229 to couple to the NVME drive 227, and finger 231b including a SATA drive connector 228 to couple to the SATA drive 226.
  • NVMe drive 227 is capable of utilizing four HSIO lanes, it will operate when utilizing less than four lanes. It may not have the same performance as when four HSIO lanes are used, but there may be other considerations that would motivate one to utilize one or more SATA drives together with a NVMe drive. While the embodiment illustrated in Fig, 5 shows one SATA drive 226 and one NVMe drive 227, embodiment may include additional fingers and drives.
  • the initialization logic 28 operations described with respect to FIGs. 2a and 2b may be used to detect and configure the attachment of devices as shown with respect to FIGs. 3, 4, and 5 .
  • the systems described above may comprise a personal computer, server, mobile device or embedded computer device.
  • a silicon-on-chip (SOC) implementation at least some of the architecture may be implemented in an integrated circuit die.
  • an embodiment means “one or more (but not all) embodiments of the present invention(s)" unless expressly specified otherwise.

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Claims (11)

  1. Procédé pour configurer des architectures de stockage informatique pendant une opération d'amorçage d'un système comprenant un bus et une horloge de bus en communication avec le bus, ce procédé comprenant, pour chacun d'une pluralité de groupes de couloirs d'un bus (16) dans le système (10) :
    la détection (105), par le système (10), de si un dispositif implémentant un premier protocole d'interface de bus est couplé ou pas au bus (16) par l'intermédiaire d'un connecteur (22) ;
    la programmation (107), par le système (10), de la désactivation de l'horloge du bus (18) en réponse à la détection qu'aucun dispositif implémentant le premier protocole d'interface de bus n'est couplé au bus (16) par l'intermédiaire du connecteur (22) ;
    la reprogrammation (109 ; 137), par le système (10), après la programmation de la désactivation de l'horloge du bus (18), d'une mémoire tampon Entrée/Sortie, IO (20), connectée au bus conformément à un deuxième protocole d'interface de bus afin de connecter à un dispositif (26) implémentant le deuxième protocole d'interface de bus ;
    la détection (111), par le système (10), après la reprogrammation de la mémoire tampon, de si un dispositif implémentant le deuxième protocole d'interface de bus est couplé ou pas au bus (16) par l'intermédiaire du connecteur (22) ; et
    l'initialisation, par le système (10), du dispositif (26) implémentant le deuxième protocole d'interface de bus en réponse à la détection que le dispositif implémentant le deuxième protocole d'interface de bus est couplé au bus (16) par l'intermédiaire du connecteur (22) ;
    la détermination de si le dispositif implémentant le premier protocole d'interface de bus est un dispositif de stockage implémentant un protocole d'interface de dispositif logique en réponse à la détection que le dispositif implémentant le premier protocole d'interface de bus est couplé au bus (16) dans le système par l'intermédiaire du connecteur ; et
    l'initialisation du dispositif de stockage en réponse à la détermination que le dispositif implémentant le premier protocole d'interface de bus implémente aussi un protocole d'interface de dispositif logique,
    après l'initialisation du dispositif de stockage en réponse à la détermination que le dispositif implémentant le premier protocole d'interface de bus implémente aussi un protocole d'interface de dispositif logique, la reprogrammation de toute mémoire tampon IO à grande vitesse, HSIO, inutilisée de la mémoire tampon pour faire en sorte que le connecteur implémente le deuxième protocole d'interface de bus,
    le premier protocole d'interface de bus consistant en un protocole d'interface de bus PCIe, Peripheral Component Interconnect Express, le deuxième protocole d'interface de bus consistant en un protocole d'interface de bus SATA, Serial Advanced Technology Attachment, et le protocole d'interface de dispositif logique consistant en un protocole d'interface de bus de dispositif logique NVMe, Non-Volatile Memory Express.
  2. Procédé selon la revendication 1, comprenant en outre l'initialisation (119 ; 129 ; 131 ; 135 ; 145) d'un dispositif (26) implémentant le premier protocole d'interface de bus afin de communiquer sur le bus (16) en réponse à la détection qu'un dispositif implémentant le premier protocole d'interface de bus est couplé au bus (16) dans le système par l'intermédiaire du connecteur (22).
  3. Procédé selon la revendication 1 ou 2, dans lequel le premier protocole d'interface de bus consiste en un protocole d'interface de bus PCIe, Peripheral Component Interconnect Express, et le deuxième protocole d'interface de bus consiste en un protocole d'interface de bus SATA, Serial Advanced Technology Attachment.
  4. Procédé selon l'une quelconque des revendications précédentes, dans lequel la détection de si un dispositif implémentant un premier protocole d'interface de bus est couplé ou pas au bus (16) dans le système par l'intermédiaire d'un connecteur comprend l'évaluation d'un groupe entrée/sortie à grande vitesse, HSIO, à quatre couloirs.
  5. Procédé selon l'une quelconque des revendications précédentes, dans lequel la reprogrammation de la mémoire tampon comprend la reprogrammation de la mémoire tampon sur quatre ports.
  6. Procédé selon l'une quelconque des revendications précédentes, comprenant en outre la désactivation de toute mémoire tampon non utilisée après l'initialisation du dispositif.
  7. Procédé selon l'une quelconque des revendications précédentes, dans lequel l'initialisation du dispositif de stockage implémentant le deuxième protocole d'interface de bus comprend l'initialisation d'une pluralité de pilotes SATA, Serial Advanced Technology Attachment.
  8. Logique d'initialisation comprenant des moyens configurés de façon à exécuter les étapes du procédé selon l'une quelconque des revendications 1 à 7.
  9. Système comprenant :
    un bus (16) ;
    une horloge de bus (18) en communication avec le bus (16) ;
    une mémoire tampon IO (20) en communication avec le bus (16) ;
    un dispositif de stockage (26) pour stocker des données ;
    un connecteur (22) configuré de façon à coupler le dispositif de stockage (26) au bus (16) ;
    une logique d'initialisation (28) selon la revendication 8.
  10. Système selon la revendication 9, comprenant en outre :
    un câble (24, 224) pour coupler le dispositif de stockage (26) à une carte (208), ce câble (24, 224) comprenant :
    une première extrémité configurée de façon à s'accoupler avec un connecteur de carte (22, 222) qui est compatible avec un premier protocole d'interface de bus et un deuxième protocole d'interface de bus ; et
    une deuxième extrémité comprenant un premier, un deuxième, un troisième et un quatrième connecteur (22, 228) et configurée de façon à s'accoupler avec un dispositif de stockage agencé de façon à implémenter le deuxième protocole d'interface de bus.
  11. Support lisible par machine comprenant des instructions lisibles par machine qui, lorsqu'elles sont exécutées par un appareil, font exécuter à cet appareil les étapes du procédé selon l'une quelconque des revendications 1 à 7.
EP18154453.7A 2017-03-31 2018-01-31 Dispositifs de stockage multiples mis en uvre à l'aide d'un connecteur commun Active EP3382567B1 (fr)

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US15/476,882 US10509759B2 (en) 2017-03-31 2017-03-31 Multiple storage devices implemented using a common connector

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US20180285307A1 (en) 2018-10-04
US10509759B2 (en) 2019-12-17
CN108694139A (zh) 2018-10-23

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