EP3379643B1

EP3379643B1 - Multilayer substrate and radar device

Info

Publication number: EP3379643B1
Application number: EP16866102.3A
Authority: EP
Inventors: Takehiro KISHIDA; Shuhei INOUE
Original assignee: Furuno Electric Co Ltd
Current assignee: Furuno Electric Co Ltd
Priority date: 2015-11-20
Filing date: 2016-10-25
Publication date: 2022-10-19
Anticipated expiration: 2036-10-25
Also published as: WO2017086100A1; CN108370078B; EP3379643A1; JPWO2017086100A1; US10594012B2; JP6491353B2; CN108370078A; US20180331407A1; EP3379643A4

Description

[Technical Field]

The present disclosure relates to a multilayer substrate used for transmitting/receiving a high frequency signal, and a radar device having the multilayer substrate.

[Background Art]

In a conventional multilayer substrate for transmitting/receiving a high frequency signal, for example, a filter circuit or a matching circuit is formed on the multilayer substrate to suppress harmonic waves.
Further, Patent Literature 1 discloses that a multilayer substrate having good high frequency characteristics can be formed by exposing an inner conductive layer in a multilayer substrate and bringing an exposed portion of the inner conductive layer into contact with a casing as a system ground.

[Citation List]

[Patent Literature]

[Patent Literature 1]
Japanese Unexamined Patent Application Publication No. 2005-244110

[Summary of Invention]

[Technical Problem]

However, when the filter circuit or the matching circuit is formed on the multilayer substrate as described above, accordingly, a pattern becomes complicated.
Further, in the multilayer substrate disclosed in Patent Literature 1, to expose the inner conductive layer to the outside, it is necessary to form a concave or stepped portion in the substrate, and a shape of the substrate becomes complicated, and thus it is not preferable in terms of cost.
JP 2000100994 A is related to a high-frequency package. Herein, a signal line is composed of a microstrip line structure that comprises a package inner part and a package outer part, a strip line structure that is a hermetically sealed part and an embedded microstrip line structure that is a tapered part which connects them together. Therefore, the tapered part can be prevented from causing characteristic impedance mismatching. Furthermore, the embedded microstrip line structure can be comparatively easily formed, so that a high-frequency package of this constitution can be lessened in manufacturing man-hours and manufacturing costs. Moreover, the distance between the edge of a ground plane and its connecting point connected to a conductor wire near to the edge of the ground plane can be made nearly zero so that a high-frequency package can be prevented from deteriorating in transmission characteristic of high-frequency signal due to circuitry structure of stub.
US 2013/0154773 A1 is related to a waveguide. Herein, a waveguide comprises a waveguide comprises an inner conductor arranged in a first layer, a pair of outer conductors comprising a first outer conductor and a second outer conductor, and a pair of slotted shields comprising a first slotted shield and a second slotted shield. The first slotted shield and the second slotted shield are arranged in a second layer with a spacing in between to form a section of a ground shield, wherein the second layer is parallel to the first layer. The first slotted shield is connected to the first outer conductor and the second slotted shield is connected to the second outer conductor.
Sturdivant R. et a.: "Transitions and interconnects using coplanar waveguide and other three conductor transmission lines", Bridging the spectrum: 1996 IEEE MTT-S International Microwave Symposium Digest, June 17 - 21, 1996, Moscone Convention Center, San Francisco, California, Piscataway, NJ: IEEE Publ. Order Dep., US, 17 June 1996, pages 235 - 238 vol. 1, XP032372672, DOI: 10.1109/MWSYM.1996.508501, ISBN: 978-0-7803-3246-1 is concerned with multilayer substrates allowing high density packaging of microwave components. Herein, multilayer boards often require the use of vertical interconnects and transitions to and from various transmission line types. By using three conductor lines such as CPW, it is possible to develop a packaging technique which permits operation up to 20 GHz. A packaging approached tailored for airborne radar is considered along with the interconnect transitions used in the model. This includes the use of 3-wire line. Transitions to/from CBCPW, stripline, 3-wire line and microstrip are described along with modelling and test data. In addition, test data is presented on solderless interconnects using button connectors.
It is an object of the present invention to provide a multilayer substrate having a simplified configuration and excellent high frequency characteristics.
This object is solved by the subject-matter of the independent claim. Further advantageous embodiments and refinements of the present invention are described in the respective subclaims.
(1) To solve the above-described problems, a multilayer substrate according to claim 1 is provided.
(2) Two input side ground layers and two output side ground layers may be formed, and three or more intermediate ground layers may be formed.
(4) A length of an intermediate region signal line portion formed in the intermediate region of the signal line may be set to be an integral multiple of the half wavelength of the harmonic wave.
(5) A length of an input side region signal line portion formed in the input side region of the signal line may be set on the basis of an impedance of the harmonic wave.
(6)
(7)
(8) To solve the above-described problems, a radar device according to claim 6 is provided.

[Advantageous Effects of Invention]

According to the present disclosure, it is possible to provide a multilayer substrate having a simplified configuration and good high frequency characteristics.

[Brief Description of Drawings]

Fig. 1 is a block diagram of a radar device having a multilayer substrate according to an embodiment not according to the claimed invention .
Fig. 2 is a plan view of the multilayer substrate illustrated in Fig. 1 and is a view illustrating a conductive pattern (first conductive pattern) of a top layer (first layer) with diagonal lines.
Fig. 3 is a schematic view illustrating a cross-sectional shape of the multilayer substrate illustrated in Fig. 2 taken along line III-III and is a view illustrating a state in which a part thereof is omitted.
Fig. 4 is a top view of a conductive pattern (second conductive pattern) of a second layer from the top and is a view illustrating a second conductive pattern with diagonal lines.
Fig. 5 is a top view of a conductive pattern (third conductive pattern) of a third layer from the top and is a view illustrating a third conductive pattern with diagonal lines.
Fig. 6 is a top view of a conductive pattern (fourth conductive pattern) of a bottom layer (fourth layer) and is a view illustrating a fourth conductive pattern with diagonal lines.
Fig. 7 is a view illustrating a state in which a simulation graph (illustrated by a broken line in Fig. 7) of a transmission characteristic of a multilayer substrate according to a comparative example is superimposed on a simulation graph (illustrated by a solid line in Fig. 7) of a transmission characteristic of the multilayer substrate not according to the claimed invention .
Fig. 8 is a view illustrating a state in which a simulation graph (illustrated by a broken line in Fig. 8) of a reflection characteristic of the multilayer substrate according to the comparative example is superimposed on a simulation graph (illustrated by a solid line in Fig. 8) of a reflection characteristic of the multilayer substrate not according to the claimed invention.
Fig. 9 is a view illustrating a state in which a graph illustrating a simulation result of the transmission characteristic of the multilayer substrate not according to the claimed invention, and a graph illustrating a simulation result of the transmission characteristic of the multilayer substrate according to the comparative example are superimposed.
Fig. 10 is an electric field simulation of a secondary harmonic wave in the multilayer substrate according to the embodiment outside the subject-matter of the claims.
Fig. 11 is an electric field simulation of the secondary harmonic wave in the multilayer substrate according to the comparative example.
Fig. 12 is a view illustrating a state in which the graph illustrating the simulation result of the transmission characteristic of the multilayer substrate according to the embodiment outside the subject-matter of the claims, and the graph illustrating the simulation result of the transmission characteristic of the multilayer substrate according to the comparative example are superimposed.
Fig. 13 is an electric field simulation of the secondary harmonic wave in the multilayer substrate according to the embodiment outside the subject-matter of the claims.
Fig. 14 is an electric field simulation of the secondary harmonic wave in the multilayer substrate according to the comparative example.
Fig. 15 is a Smith chart illustrating impedances of multilayer substrates having mutually different lengths L3 and is a graph in which an end on the center side of the chart in each of graphs G1 to G10 illustrated in a straight line indicates an impedance in a fundamental wave and an end on the outside of the chart in each of the graphs G1 to G10 indicates an impedance in the secondary harmonic wave.
Fig. 16 is a graph illustrating the simulation result of the transmission characteristic of the multilayer substrate according to the embodiment outside the subject-matter of the claims, and is a view illustrating a state in which a graph illustrating the transmission characteristic of the multilayer substrate in which a value of L4 is set to reduce the transmission characteristic of the secondary harmonic wave and a graph illustrating the transmission characteristic of the multilayer substrate in which the value of L4 is set to reduce the transmission characteristic of a tertiary harmonic wave are superimposed.
Fig. 17 is a plan view of a multilayer substrate according to a modified example and is a view illustrating a conductive pattern (first conductive pattern) of a top layer (first layer) with diagonal lines.
Fig. 18 is a schematic view illustrating a cross-sectional shape of the multilayer substrate illustrated in Fig. 17 taken along line XVIII-XVIII and is a view illustrating a state in which a part thereof is omitted.
Fig. 19 is an electric field simulation of a fundamental wave in the multilayer substrate according to the modified example.
Fig. 20 is an electric field simulation of a secondary harmonic wave in the multilayer substrate according to the modified example.
Fig. 21 is an electric field simulation of a tertiary harmonic wave in the multilayer substrate according to the modified example.
Fig. 22 is a view corresponding to Fig. 18 and schematically illustrating a cross-sectional shape of the multilayer substrate according to the modified example.

[Description of Embodiments]

Hereinafter, modes for implementing the present disclosure will be described with reference to the drawings. The present disclosure can be widely applied to a multilayer substrate for transmitting and receiving signals and a radar device having the multilayer substrate.
Fig. 1 is a block diagram of a radar device 1 having a multilayer substrate 10 according to an embodiment outside the subject-matter of the claims . The radar device 1 according to the embodiment is mounted in, for example, a vessel as a ship and is used for detecting another ship.
In the radar device 1, a transmission wave generated from a transmission signal generated by a transmission/reception device 3 is transmitted from an antenna 2, and a reflection wave in which a transmission wave is reflected by a target and returns is received by the antenna 2 as a reception wave. In the radar device 1, a signal processing unit 4 processes a received signal obtained from the reception wave and generates information (for example, a video signal of an echo image of the target) on the target, and the information is displayed on a display unit 5.
Additionally, the multilayer substrate 10 according to the embodiment ,outside the subject-matter of the claims, which disclosure is used for the transmission/reception device 3. Specifically, the multilayer substrate 10 has an input side terminal 17 and an output side terminal 18 (refer to Fig. 2). In the multilayer substrate 10, in a state in which it is connected to a transmission signal generation unit 6 of the transmission/reception device 3 by a transmission/reception switching unit (not illustrated), the transmission signal generated by the transmission signal generation unit 6 is input to the input side terminal 17 and the transmission signal is output to the antenna 2 side via the output side terminal 18. On the other hand, in the multilayer substrate 10, in a state in which it is connected to a reception unit 7 of the transmission/reception device 3 by the transmission/reception switching unit, a reception signal obtained from the reception wave received by the antenna 2 is input from the output side terminal 18, and the received signal is output to the reception unit 7 via the input side terminal 17. The reception unit 7 outputs the received signal to the signal processing unit 4 after an A/D conversion of the reception signal.

[Configuration of multilayer substrate]

Fig. 2 is a plan view of the multilayer substrate 10 illustrated in Fig. 1 and is a view illustrating a conductive pattern (first conductive pattern 15) of a top layer (first layer) with diagonal lines. Also, Fig. 3 is a schematic view illustrating a cross-sectional shape of the multilayer substrate 10 illustrated in Fig. 2 taken along line III-III and is a view illustrating a state in which a part thereof is omitted. Also, Fig. 4 is a top view of a conductive pattern (second conductive pattern 25) of a second layer from the top and is a view illustrating a second conductive pattern 25 with diagonal lines. Also, Fig. 5 is a top view of a conductive pattern (third conductive pattern 30) of a third layer from the top and is a view illustrating a third conductive pattern 30 with diagonal lines. Also, Fig. 6 is a top view of a conductive pattern (fourth conductive pattern 35) of a bottom layer (fourth layer) and is a view illustrating a fourth conductive pattern 35 with diagonal lines. Further, in Fig. 3, to avoid making the drawing complicated, hatching of dielectric layers 11, 12 and 13 is omitted, and a longitudinal dimension of each component with respect to a transverse dimension thereof does not necessarily correspond to an actual dimension. In addition, in Figs. 4 to 6, an outer shape of the first conductive pattern 15 is illustrated to be superimposed with a broken line.
Further, in each of the drawings, for convenience of explanation, a direction indicated by an arrow marked as an input side is referred to as the input side, a direction indicated by an arrow marked as an output side is referred to as the output side, a direction indicated by an arrow marked as a right side is referred to as the right side, a direction indicated by the arrow marked as a left side is referred to as the left side, a direction indicated by an arrow marked as an upper side is referred to as the upper side or upper direction, and a direction indicated by an arrow marked as a lower side is referred to as the lower side or lower direction.
The multilayer substrate 10 of the embodiment ,outside the subject-matter of the claims, is a so-called four-layer substrate (a substrate in which four conductive layers are formed) and is a substrate having a particular thickness formed in a rectangular shape in a plan view. The multilayer substrate 10 may be divided into three regions in a plan view. Specifically, referring to Figs. 2, 4 and 6, the multilayer substrate 10 may be divided into an input side region Z_IN on the side in which a signal is input, an output side region Z_OUT in which a signal is output, and an intermediate region Z_MID sandwiched between the input side region Z_IN and the output side region Z_OUT.
The multilayer substrate 10 has three dielectric layers 11, 12 and 13 and four conductive patterns 15, 25, 30 and 35.
The three dielectric layers 11, 12 and 13 include a first dielectric layer 11, a second dielectric layer 12 and a third dielectric layer 13.
The first dielectric layer 11 is a dielectric layer provided at the top side among the three dielectric layers, the first conductive pattern 15 is formed on an upper side thereof, and the second conductive pattern 25 is formed on a lower side thereof.
The second dielectric layer 12 is a dielectric layer formed under the first dielectric layer 11 and is provided in close contact with a lower surface of the second conductive pattern 25. The third conductive pattern 30 is provided in close contact with a lower surface of the second dielectric layer 12.
The third dielectric layer 13 is a dielectric layer formed under the second dielectric layer 12. The third conductive pattern 30 is formed on an upper side of the third dielectric layer 13, and the fourth conductive pattern 35 is formed in close contact with a lower side thereof.
The four conductive patterns 15, 25, 30 and 35 include the first conductive pattern 15, the second conductive pattern 25, the third conductive pattern 30, and the fourth conductive pattern 35.
Referring to Fig. 2, the first conductive pattern 15 is formed on a front side (upper side) surface of the first dielectric layer 11. That is, the first conductive pattern 15 is provided as the top conductive pattern and is exposed on the front side (upper side) surface of the multilayer substrate 10.
Referring to Fig. 2 and Fig. 3, the first conductive pattern 15 includes a signal line 16 and a first ground pattern 20 (ground layer).
The signal line 16 is a conductive pattern which linearly extends from an input side end of the multilayer substrate 10 to an output side end thereof at a center portion of the multilayer substrate 10 in a rightward and leftward direction. The signal line 16 includes an input side region signal line portion 16a formed in the input side region Z_IN, an intermediate region signal line portion 16b formed in the intermediate region Z_MID, and an output side region signal line portion 16c formed in the output side region Z_OUT. An input side end of the signal line 16 is provided as the input side terminal 17 to which the transmission signal generated by the transmission signal generation unit 6 (refer to Fig. 1) is input. Also, an output side end of the signal line 16 is provided as the output side terminal 18 through which a signal passing through the signal line 16 is output to the antenna 2 side.
The first ground pattern 20 is a portion provided as a ground surface in the first conductive pattern. That is, the first ground pattern 20 is formed not to be in contact with the signal line 16. The first ground pattern 20 includes an input side region ground layer 21, an intermediate region ground layer 22, and an output side region ground layer 23.
The input side region ground layer 21 is a portion formed in the input side region Z_IN of the first ground pattern 20. The input side region ground layer 21 includes an input side region right ground layer 21R formed in a right side of the input side region Z_IN, and an input side region left ground layer 21L formed in a left side of the input side region Z_IN. Each of the input side region right ground layer 21R and the input side region left ground layer 21L is formed in a rectangular shape. A distance G_IN in the rightward and leftward direction between the input side region right ground layer 21R and the signal line 16, and a distance G_IN in the rightward and leftward direction between the input side region left ground layer 21L and the signal line 16 are appropriately set by a designer.
The intermediate region ground layer 22 is a portion formed in the intermediate region Z_MID of the first ground pattern 20. The intermediate region ground layer 22 includes an intermediate region right ground layer 22R formed in a right side of the intermediate region Z_MID, and an intermediate region left ground layer 22L formed in a left side of the intermediate region Z_MID. Each of the intermediate region right ground layer 22R and the intermediate region left ground layer 22L is formed in a rectangular shape. The intermediate region right ground layer 22R is integrally formed with the input side region right ground layer 21R, and the intermediate region left ground layer 22L is integrally formed with the input side region left ground layer 21L. A distance G_MID in the rightward and leftward direction between the intermediate region right ground layer 22R and the signal line 16, and a distance G_MID in the rightward and leftward direction between the intermediate region left ground layer 22L and the signal line 16 are set shorter than the above-described distances G_IN. That is, the intermediate region right ground layer 22R and the intermediate region left ground layer 22L are respectively provided to protrude toward the signal line 16 side than the input side region right ground layer 21R and the input side region left ground layer 21L.
The output side region ground layer 23 is a portion formed in the output side region Z_OUT of the first ground pattern 20. The output side region ground layer 23 includes an output side region right ground layer 23R formed in a right side of the output side region Z_OUT, and an output side region left ground layer 23L formed in a left side of the output side region Z_OUT. Each of the output side region right ground layer 23R and the output side region left ground layer 23L is formed in a rectangular shape. The output side region right ground layer 23R is integrally formed with the intermediate region right ground layer 22R, and the output side region left ground layer 23L is integrally formed with the intermediate region left ground layer 22L. A distance G_OUT in the rightward and leftward direction between the output side region right ground layer 23R and the signal line 16, and a distance G_OUT in the rightward and leftward direction between the output side region left ground layer 23L and the signal line 16 are set to be equal to the above-described distances G_IN.
Referring to Fig. 3, the second conductive pattern 25 is formed between the first dielectric layer 11 and the second dielectric layer 12. That is, the second conductive pattern 25 is provided as a second conductive pattern from the top and is embedded in the multilayer substrate 10.
Referring to Fig. 4, the second conductive pattern 25 is constituted by a second ground pattern 26 (ground layer or short distance ground layer). The second ground pattern 26 is uniformly formed in the intermediate region Z_MID and is not formed in the input side region Z_IN and the output side region Z_OUT. That is, the second ground pattern 26 is provided as an intermediate ground layer.
Referring to Fig. 3, the third conductive pattern 30 is provided between the second dielectric layer 12 and the third dielectric layer 13. That is, the third conductive pattern 30 is provided as a third conductive pattern from the top and is embedded in the multilayer substrate 10.
Referring to Fig. 5, the third conductive pattern 30 is constituted by a third ground pattern 31 (ground layer). The third ground pattern 31 is uniformly formed in the intermediate region Z_MID and is not formed in the input side region Z_IN and the output side region Z_OUT. That is, the third ground pattern 31 is provided as an intermediate ground layer. The third ground pattern 31 has the same shape as that of the second ground pattern 26.
Referring to Fig. 3, the fourth conductive pattern 35 is formed on a back side (lower side) surface of the third dielectric layer 13. That is, the fourth conductive pattern 35 is provided as a bottom conductive pattern and is exposed at a back side (lower side) surface of the multilayer substrate 10.
Referring to Fig. 6, the fourth conductive pattern 35 is constituted by a fourth ground pattern 36 (ground layer or long distance ground layer). The fourth ground pattern 36 is uniformly formed over an entire region on the back surface (lower surface) of the third dielectric layer 13. The fourth ground pattern 36 includes an input side region ground layer 37 (input side ground layer) formed in the input side region Z_IN, an intermediate region ground layer 38 (intermediate ground layer) formed in the intermediate region Z_MID, and an output side region ground layer 39 (output side ground layer) formed in the output side region Z_OUT. The fourth ground pattern 36 is provided as a system ground of the radar device 1.
Further, referring to Figs. 2 and 3, a plurality of vias 40 are formed in the multilayer substrate 10. Each of the vias 40 vertically passes through the multilayer substrate 10 and electrically connects the ground patterns 20, 26, 31 and 36 of the conductive patterns 15, 25, 30 and 35.
The plurality of vias 40 include a plurality of input side region vias 41, a plurality of intermediate region vias 42, and a plurality of output side region vias 43.
The plurality of input side region vias 41 are vias formed in the input side region Z_IN. The plurality of input side region vias 41 include a plurality of input side region right vias 41R and a plurality of input side region left vias 41L.
The plurality of (three in the embodiment) input side region right vias 41R are formed on the right side in the input side region Z_IN. Specifically, referring to Fig. 2, three input side region right vias 41R are arranged in one row from the input side to the output side on the signal line 16 side in the input side region right ground layer 21R. Referring to Fig. 2 and Figs, 4 to 6, the input side region right ground layer 21R of the first ground pattern 20 and the fourth ground pattern 36 are electrically connected by the plurality of input side region right vias 41R.
The plurality of (three in the embodiment) input side region left vias 41L are formed on the left side in the input side region Z_IN. Specifically, referring to Fig. 2, three input side region left vias 41L are arranged in one row from the input side to the output side on the signal line 16 side in the input side region left ground layer 21L. Referring to Fig. 2 and Figs. 4 to 6, the input side region left ground layer 21L of the first ground pattern 20 and the fourth ground pattern 36 are electrically connected by the plurality of input side region left vias 41L.
The plurality of intermediate region vias 42 are vias formed in the intermediate region Z_MID. The plurality of intermediate region vias 42 include a plurality of intermediate region right vias 42R (first vias) and a plurality of intermediate region left vias 42L (second vias).
The plurality of (six in the embodiment) intermediate region right vias 42R are formed on the right side in the intermediate region Z_MID. Specifically, referring to Fig. 2, six intermediate region right vias 42R are arranged in one row from the input side to the output side on the signal line 16 side in the intermediate region right ground layer 22R. Referring to Fig. 2 and Figs. 4 to 6, the intermediate region right ground layer 22R of the first ground pattern 20, the second ground pattern 26, the third ground pattern 31 and the fourth ground pattern 36 are electrically connected by the plurality of intermediate region right vias 42R.
The plurality of (six in the embodiment) intermediate region left vias 42L are formed on the left side in the intermediate region Z_MID. Specifically, referring to Fig. 2, six intermediate region left vias 42L are arranged in one row from the input side to the output side on the signal line 16 side in the intermediate region left ground layer 22L. Referring to Fig. 2 and Figs. 4 to 6, the intermediate region left ground layer 22L of the first ground pattern 20, the second ground pattern 26, the third ground pattern 31 and the fourth ground pattern 36 are electrically connected by the plurality of intermediate region left vias 42L.
The plurality of output side region vias 43 are vias formed in the output side region Z_OUT. The plurality of output side region vias 43 include a plurality of output side region right vias 43R and a plurality of output side region left vias 43L.
The plurality of (three in the embodiment) output side region right vias 43R are formed on the right side in the output side region Z_OUT. Specifically, referring to Fig. 2, three output side region right vias 43R are arranged in one row from the input side to the output side on the signal line 16 side in the output side region right ground layer 23R. Referring to Fig. 2 and Figs. 4 to 6, the output side region right ground layer 23R of the first ground pattern 20 and the fourth ground pattern 36 are electrically connected by the plurality of output side region right vias 43R.
The plurality of (three in the embodiment) output side region left vias 43L are formed on the left side in the output side region Z_OUT. Specifically, referring to Fig. 2, three output side region right vias 43R are arranged in one row from the input side to the output side on the signal line 16 side in the output side region left ground layer 23L. Referring to Fig. 2 and Figs. 4 to 6, the output side region left ground layer 23L of the first ground pattern 20 and the fourth ground pattern 36 are electrically connected by the plurality of output side region left vias 43L.

[Regarding the number of layers of ground pattern in each region of multilayer substrate]

Incidentally, in a conventional multilayer substrate, a filter circuit or a matching circuit is formed on the multilayer substrate to obtain excellent high frequency characteristics. However, in that case, accordingly, the pattern becomes complicated, and a size of the substrate increases.
Further, Patent Literature 1 discloses that a multilayer substrate having good high frequency characteristics can be formed by exposing an inner conductive layer in the multilayer substrate and bringing an exposed portion of the inner conductive layer into contact with a casing as a system ground. However, in this case, since a shape of the substrate becomes complicated, it is not preferable in in terms of cost.
Regarding this point, in the embodiment, referring to Fig. 2 and Figs. 4 to 6, two layers of ground patterns (the first ground pattern 20 and the fourth ground pattern 36) are formed in the input side region Z_IN and the output side region Z_OUT of the multilayer substrate 10. On the other hand, four layers of ground patterns (the first ground pattern 20, the second ground pattern 26, the third ground pattern 31 and the fourth ground pattern 36) are formed in the intermediate region Z_MID of the multilayer substrate 10. That is, the multilayer substrate 10 is formed so that the ground patterns of a portion (the input side region Z_IN and the output side region Z_OUT) thereof in which the signal is input/output has fewer layers than the ground patterns in the intermediate region Z_MID. In this case, since the disturbance of an electric field in the portion in which the signal is input/output hardly occurs, a quasi-TEM mode is likely to be formed in that portion. As a result, a transmission characteristic of the signal is improved.
Fig. 7 is a view illustrating a state in which a simulation graph (illustrated by a broken line in Fig. 7) of a transmission characteristic S₂₁ of a multilayer substrate according to a comparative example is superimposed on a simulation graph (illustrated by a solid line in Fig. 7) of a transmission characteristic S₂₁ of the multilayer substrate 10 according to the embodiment. Further, Fig. 8 is a view illustrating a state in which a simulation graph (illustrated by a broken line in Fig. 8) of a reflection characteristic S₁₁ of the multilayer substrate according to the comparative example is superimposed on a simulation graph (illustrated by a solid line in Fig. 8) of a reflection characteristic S₁₁ of the multilayer substrate 10 according to the embodiment outside the subject-matter of the claims. Also, referring to Figs. 4 and 5, in a multilayer substrate according to the comparative example, the ground patterns (the second ground pattern and the third ground pattern) of the inner layers are formed over the entire region (the input side region Z_IN, the intermediate region Z_MID, and the output side region Z_OUT) of the substrate, and other configurations are the same as those of the multilayer substrate 10.
As illustrated in Figs. 7 and 8, according to the multilayer substrate 10 of the embodiment, outside the subject-matter of the claims, it can be confirmed that excellent transmission and reflection characteristics are obtained in a frequency band (9.4 GHz) of the transmitted signal as compared with the multilayer substrate according to the comparative example.

[Regarding dimensions of each part]

Referring to Figs. 2 and 3, in the multilayer substrate 10 according to the embodiment, outside the subject-matter of the claims, dimensions L1 to L5 are appropriately set. Therefore, high frequency performance of the multilayer substrate 10 can be enhanced. In the multilayer substrate 10 according to the embodiment, outside the subject-matter of the claims, each value of L1 to L5 is set as follows. Specifically, the value of L1 is set to be a half wavelength of a wavelength λ_r of a secondary harmonic wave (18.8 GHz). Also, the value of L2 is set to be an integral multiple of the half wavelength (λ_r/2) of the secondary harmonic wave. Further, as will be described in detail below, by adjusting the value of L3, an impedance of the secondary harmonic wave may be arbitrarily set without affecting an impedance of a fundamental wave (9.4 GHz). Further, a value obtained by adding L4 and L5 is set to be a quarter of the wavelength λ_r of the secondary harmonic wave (18.8 GHz).

[Regarding dimension L1]

Referring to Fig. 2, L1 is a distance between the intermediate region right via 42R and the intermediate region left via 42L. More specifically, L1 is a distance between an end of the intermediate region right via 42R on the signal line 16 side and an end of the intermediate region left via 42L on the signal line 16 side. In the multilayer substrate 10 according to the embodiment, outside the subject-matter of the claims, the dimension of L1 is set to be the half wavelength of the wavelength λ_r of the secondary harmonic wave (18.8 GHz). Further, the wavelength λ_r is a wavelength in consideration of a wavelength shortening effect due to a dielectric constant of the dielectric layer in which the signal line 16 through which the signal is transmitted is formed. The wavelength λ_r can be calculated, for example, by dividing the wavelength of the secondary harmonic wave in a vacuum by a square root of the dielectric constant of the dielectric layer.
Fig. 9 is a view illustrating a state in which a graph (illustrated by a square in Fig. 9) illustrating a simulation result of the transmission characteristic of the multilayer substrate 10 according to the embodiment ,outside the subject-matter of the claims, and a graph (illustrated by a circle in Fig. 9) illustrating a simulation result of the transmission characteristic of the multilayer substrate 100 according to the comparative example are superimposed. Further, Fig. 10 is an electric field simulation of the secondary harmonic wave in the multilayer substrate 10 according to the embodiment outside the subject-matter of the claims. Further, Fig. 11 is an electric field simulation of the secondary harmonic wave in the multilayer substrate 100 according to the comparative example. Also, dimensions of the multilayer substrate 100 according to the comparative example are the same as those of the multilayer substrate 10, except for the fact that the value of L1 is set to be a quarter of the wavelength λ_r of the secondary harmonic wave (18.8 GHz). Also, the electric field simulations illustrated in Figs. 10 and 11 are electric field simulations when the multilayer substrate is seen from the input side.
As illustrated in Fig. 9, the transmission characteristic of the fundamental wave (9.4 GHz) is substantially the same in both the multilayer substrate 10 and the multilayer substrate 100 according to the comparative example. However, regarding the transmission characteristic of the secondary harmonic wave (18.8 GHz), the multilayer substrate 10 according to the embodiment ,outside the subject-matter of the claims, has superior characteristics (it is difficult to transmit the secondary harmonic wave).
To confirm the reason, the inventor of the present disclosure conducted an electric field simulation, and as illustrated in Fig. 11, according to an electric field simulation result of the multilayer substrate 100 according to the comparative example, it was confirmed that the secondary harmonic wave propagates between the signal line 16 and the conductor of the second layer (the second ground pattern 26). That is, in the multilayer substrate 100 according to the comparative example, the secondary harmonic wave is transmitted to the output side through the signal line.
On the other hand, according to the electric field simulation in the multilayer substrate 10 according to the embodiment, outside the subject-matter of the claims, it was confirmed that the secondary harmonic wave propagates between the conductor of the second layer (the second conductive pattern 25) and the conductor of the fourth layer (the fourth conductive pattern 35), as illustrated in Fig. 10. In the second to fourth conductors (the second conductive pattern 25, the third conductive pattern 30 and the fourth conductive pattern 35), since the output sides are in an open state, it was confirmed that it is difficult for the secondary harmonic wave to propagate to the output side, as illustrated in Fig. 9.

[Regarding dimension L2]

Referring to Fig. 2, L2 is a length of a portion of the signal line 16 included in the intermediate region Z_MID, that is, the intermediate region signal line portion 16b. In the multilayer substrate 10 according to the embodiment, outside the subject-matter of the claims, the dimension of L2 is set to be an integral multiple of the half wavelength (λ_r/2) of the secondary harmonic wave.
Fig. 12 is a view illustrating a state in which the graph (illustrated by a square in Fig. 12) illustrating the simulation result of the transmission characteristic of the multilayer substrate 10 according to the embodiment , outside the subject-matter of the claims, and a graph (illustrated by a circle in Fig. 12) illustrating a simulation result of a transmission characteristic of a multilayer substrate 101 according to the comparative example are superimposed. Further, Fig. 13 is an electric field simulation of the secondary harmonic wave in the multilayer substrate 10 according to the embodiment outside the subject-matter of the claims. Further, Fig. 14 is an electric field simulation of the secondary harmonic wave in the multilayer substrate 101 according to the comparative example. Also, dimensions of the multilayer substrate 101 according to the comparative example are the same as those of the multilayer substrate 10, except for the fact that the value of L2 is set to be a value obtained by adding a quarter of the wavelength λ_r of the secondary harmonic wave (18.8 GHz) to a value obtained by multiplying a half wavelength (λ_r/2) of the secondary harmonic wave by an integer. Further, the electric field simulations illustrated in Figs. 13 and 14 are electric field simulations when the multilayer substrate is seen from the input side.
As illustrated in Fig. 12, the transmission characteristic of the fundamental wave (9.4 GHz) is substantially the same in both the multilayer substrate 10 and the multilayer substrate 101 according to the comparative example. However, regarding the transmission characteristic of the secondary harmonic wave (18.8 GHz), the multilayer substrate 10 according to the embodiment has superior characteristics (it is difficult to transmit the secondary harmonic wave).
To confirm the reason, the inventor of the present disclosure conducted an electric field simulation, and as illustrated in Fig. 14, according to an electric field simulation result of the multilayer substrate 101 according to the comparative example, it was confirmed that the secondary harmonic wave propagates between the signal line 16 and the conductor of the second layer (the second conductive pattern 25). That is, in the multilayer substrate 101 according to the comparative example, the secondary harmonic wave is transmitted to the output side through the signal line 16.
On the other hand, according to the electric field simulation in the multilayer substrate 10 according to the embodiment, it was confirmed that the secondary harmonic wave propagates between the conductor of the second layer (the second conductive pattern 25) and the conductor of the fourth layer (the fourth conductive pattern 35), as illustrated in Fig. 13. In the second to fourth conductors (the second conductive pattern 25, the third conductive pattern 30 and the fourth conductive pattern 35), since the output sides are in an open state, it was confirmed that it is difficult for the secondary harmonic wave to propagate to the output side, as illustrated in Fig. 12.

[Regarding dimension L3]

Referring to Fig. 2, L3 is a length of a portion of the signal line 16 included in the input side region Z_IN, that is, an input side region signal line portion 16a. In the multilayer substrate 10 according to the embodiment, outside the subject-matter of the claims, by adjusting the dimension of L3, the impedance of the secondary harmonic wave may be arbitrarily set without affecting the impedance of the fundamental wave (9.4 GHz).
Fig. 15 is a Smith chart illustrating impedances of multilayer substrates 10 having mutually different lengths L3 and is a graph in which an end (illustrated by a circle) on the center side of the chart in each of graphs G1 to G10 illustrated in a straight line indicates the impedance in the fundamental wave and an end (illustrated by an X mark) on the outside of the chart in each of the G1 to G10 indicates the impedance in the secondary harmonic wave. Further, in each of the graphs G1 to G10, a circle mark indicating the impedance in the fundamental wave and an X mark indicating the impedance in the secondary harmonic wave are connected by a broken straight line, but this is merely connecting the circle mark and the X mark with a straight line, and it is not intended that the impedance between the fundamental wave (9.4 GHz) and the secondary harmonic wave (18.8 GHz) is along the straight line. As illustrated in Fig. 15, it was confirmed by this simulation that the impedance of the secondary harmonic wave can be adjusted by adjusting the length of L3 without greatly affecting the impedance of the fundamental wave.

[Regarding dimension L4 and dimension L5]

Referring to Fig. 3, L4 is a distance between a portion of the signal line 16 included in the intermediate region Z_MID, that is, the intermediate region signal line portion 16b and the intermediate region right via 42R (or the intermediate region left via 42L) in the rightward and leftward direction. Also, L5 is a distance between the second ground pattern 26 and the fourth ground pattern 36. In the multilayer substrate 10 according to the embodiment, outside the subject-matter of the claims, a value obtained by adding L4 and L5 is set to be a quarter of the wavelength λ_r of the secondary harmonic wave (18.8 GHz).
Referring to Fig. 3, when the dimensions of L4 and L5 are set as described above, for a point A which is in a short-circuit state with the system ground due to a connection with the system ground, a point B which is a position separated by a distance of λ_r/4 from the point A is in an open state. In this case, for the secondary harmonic wave, the ground is in a floating state, and the secondary harmonic wave is not transmitted to the output side via the signal line 16. For this reason, it is possible to attenuate the harmonic wave.
Fig. 16 is a graph illustrating the simulation result of the transmission characteristic of the multilayer substrate 10 according to the embodiment , outside the subject-matter of the claims, and is a view illustrating a state in which a graph illustrating the transmission characteristic of the multilayer substrate 10 in which a value of L4 is set to reduce the transmission characteristic of the secondary harmonic wave and a graph illustrating the transmission characteristic of the multilayer substrate 10 in which the value of L4 is set to reduce the transmission characteristic of a tertiary harmonic wave are superimposed. When the value obtained by adding L4 and L5 is set to be a quarter of the wavelength of the secondary harmonic wave (18.8 GHz), it was confirmed that a signal of the secondary harmonic wave can be sufficiently attenuated while a signal of the fundamental wave (9.4 GHz) is transmitted as illustrated by the square mark in Fig. 16. Further, when the value obtained by adding L4 and 5 is set to be a quarter of the wavelength of the tertiary harmonic wave (28.2 GHz), it was confirmed that a signal of the tertiary harmonic wave can be sufficiently attenuated while the signal of the fundamental wave (9.4 GHz) is transmitted as illustrated by the circle mark in Fig. 16.

[Effect]

As described above, in the multilayer substrate 10 of the radar device 1 according to the embodiment, outside the subject-matter of the claims, the ground layers (two layers of the input side region ground layers 21 and 37 in the embodiment) formed in the input side region Z_IN, and the ground layers (two layers of the output side region ground layers 23 and 39 in the embodiment) formed in the output side region Z_OUT are formed to have fewer layers than the ground layers (four layers of the intermediate region ground layer 22, the second ground pattern 26, the third ground pattern 31 and the intermediate region ground layer 38 in the embodiment) formed in the intermediate region Z_MID. In this case, the disturbance of the electric field in the portion in which the signal is input/output hardly occurs, and thus the quasi-TEM mode is likely to be formed in that portion. As a result, the transmission characteristic of the signal is improved.
Therefore, according to the multilayer substrate 10, it is possible to provide a multilayer substrate having a simplified configuration and excellent high frequency characteristics.
Further, in the multilayer substrate 10, two ground layers are formed in each of the input side region Z_IN and the output side region Z_OUT, and three or more (four in the embodiment) ground layers are formed in the intermediate region Z_MID. Therefore, as can be understood from the simulation result illustrated in Fig. 7, good transmission characteristics can be obtained.
Further, in the multilayer substrate 10, the value of L1 illustrated in Fig. 2 (the distance between the intermediate region right via 42R and the intermediate region left via 42L) is set to be equal to or more than the half wavelength of the secondary harmonic wave and less than the wavelength of the secondary harmonic wave (specifically, in the present embodiment, it is set to be the half wavelength of the secondary harmonic wave). Therefore, as can be seen from the simulation result illustrated in Fig. 9, the secondary harmonic wave transmitted to the output side can be reduced.
Further, in the multilayer substrate 10, the value of L2 illustrated in Fig. 2 (the length of the intermediate region signal line portion 16b) is set to be an integral multiple of the half wavelength of the secondary harmonic wave. Therefore, as can be understood from the simulation result illustrated in Fig. 12, the secondary harmonic wave transmitted to the output side can be reduced.
Further, in the multilayer substrate 10, the value of L3 (the length of the input side region signal line portion 16a) illustrated in Fig. 2 is set on the basis of the impedance of the secondary harmonic wave to be set. In this case, as illustrated in Fig. 15, only by adjusting the value of L3, only the impedance of the secondary harmonic wave can be easily adjusted without affecting the impedance of the fundamental wave.
Further, in the multilayer substrate 10, the values of L4 and L5 are set so that the value obtained by adding L4 and L5 illustrated in Fig. 3 is a quarter of the wavelength of the secondary harmonic wave (or tertiary harmonic wave). In this case, as illustrated in Fig. 16, the secondary harmonic wave (or tertiary harmonic wave) transmitted to the output side can be reduced.
(1) Fig. 17 is a plan view of a multilayer substrate 10a according to a modified example and is a view illustrating a conductive pattern (first conductive pattern) of a top layer (first layer) with diagonal lines. Further, Fig. 18 is a schematic view illustrating a cross-sectional shape of the multilayer substrate 10a illustrated in Fig. 17 taken along line XVIII-XVIII and is a view illustrating a state in which a part thereof is omitted. The multilayer substrate 10a according to the modified example has different positions and the number of vias (intermediate region vias) formed in the intermediate region Z_MID, as compared with the multilayer substrate 10 according to the above embodiment. In the following description, portions different from those of the above-described embodiment will be described, and explanation of other portions will be omitted. Further, in Fig. 18, the hatching of the dielectric layers 11, 12 and 13 is omitted to avoid making the drawing complicated.
In the multilayer substrate 10a according to a modified example, twenty-four intermediate region vias 42a are formed. Twelve of the twenty-four intermediate region vias 42a are formed on the right side in the intermediate region Z_MID, and the remaining twelve are formed on the left side in the intermediate region Z_MID.
A plurality of (six in the modified example) intermediate region rightmost vias 44R (first vias) and a plurality of (six in the modified example) intermediate region right vias 45R (third vias) are formed as the intermediate region vias 42a on the right side of the intermediate region Z_MID.
Referring to Fig. 17, the six intermediate region rightmost vias 44R are arranged in one row from the input side to the output side on the signal line 16 side in the intermediate region right ground layer 22R. Further, referring to Fig. 18, the intermediate region rightmost vias 44R are provided to extend between the third ground pattern 31 (second long distance ground layer) and the fourth ground pattern 36 (first long distance ground layer) in a vertical direction. Therefore, the third ground pattern 31 and the fourth ground pattern 36 are electrically connected.
Referring to Fig. 17, the six intermediate region right vias 45R are arranged in one row from the input side to the output side between the signal line 16 in the intermediate region right ground layer 22R and the intermediate region rightmost vias 44R. Further, referring to Fig. 18, the intermediate region right vias 45R are provided to extend between the first ground pattern 20 (reference ground layer) and the third ground pattern 31 in a vertical direction. Therefore, the first ground pattern 20, the second ground pattern 26 and the third ground pattern 31 are electrically connected.
A plurality of (six in the modified example) intermediate region leftmost vias 44L (second vias) and a plurality of (six in the modified example) intermediate region left vias 45L (fourth vias) are formed as the intermediate region vias 42a on the left side of the intermediate region Z_MID.
Referring to Fig. 17, the six intermediate region leftmost vias 44L are arranged in one row from the input side to the output side on the signal line 16 side in the intermediate region left ground layer 22L. Further, referring to Fig. 18, the intermediate region leftmost vias 44L are provided to extend between the third ground pattern 31 and the fourth ground pattern 36 in a vertical direction. Therefore, the third ground pattern 31 and the fourth ground pattern 36 are electrically connected.
Referring to Fig. 17, the six intermediate region left vias 45L are arranged in one row from the input side to the output side between the signal line 16 in the intermediate region left ground layer 22L and the intermediate region leftmost vias 44L. Further, referring to Fig. 18, the intermediate region left vias 45L are provided to extend between the first ground pattern 20 and the third ground pattern 31 in a vertical direction. Therefore, the first ground pattern 20, the second ground pattern 26 and the third ground pattern 31 are electrically connected.

[Regarding dimensions L6 and L7]

Referring to Fig. 17, in the multilayer substrate 10a according to the embodiment, dimensions L6 and L7 are appropriately set. Accordingly, the high frequency performance of the multilayer substrate 10a can be enhanced. In the multilayer substrate 10a according to the modified example, a value of L6 is set to be a half wavelength of the wavelength of the tertiary harmonic wave (28.2 GHz). Further, a value of L7 is set to be a half wavelength of the wavelength of the secondary harmonic wave (18.8 GHz). In the modified example, L6 and L7 are set to be a half wavelength of the harmonic wave to be cut.
Fig. 19 is an electric field simulation of the fundamental wave in the multilayer substrate 10a according to the modified example. Further, Fig. 20 is an electric field simulation of the secondary harmonic wave in the multilayer substrate 10a according to the modified example. Further, Fig. 21 is an electric field simulation of the tertiary harmonic wave in the multilayer substrate 10a according to the modified example. Also, the electric field simulations illustrated in Figs. 19 to 21 are electric field simulations when the multilayer substrate 10a is seen from the input side, and in the multilayer substrate 10a schematically illustrated in each drawing, illustration of the via 40 is omitted.
Referring to Fig. 19, in the multilayer substrate 10a according to the modified example, for the fundamental wave, the electric field is distributed between the signal line 16 and the second ground pattern 26. That is, according to an electric field simulation result illustrated in Fig. 19, it was confirmed that the fundamental wave is transmitted to the output side via the signal line.
On the other hand, referring to Fig. 20, in the multilayer substrate 10a according to this modified example, for the secondary harmonic wave, the electric field is distributed mainly between the third ground pattern 31 and the fourth ground pattern 36. That is, according to the multilayer substrate 10a, it was confirmed that it is difficult for the secondary harmonic wave to be transmitted to the output side.
Further, referring to Fig. 21, in the multilayer substrate 10a according to the modified example, for the tertiary harmonic wave, the electric field is distributed mainly between the second ground pattern 26 and the third ground pattern 31. That is, according to the multilayer substrate 10a, it was confirmed that it is difficult for the tertiary harmonic wave to be transmitted to the output side.
As described above, according to the multilayer substrate 10a of the modified example, the value of L6 (the distance between the intermediate region right via 45R and the intermediate region left via 45L) is set to be equal to or more than the half wavelength of the tertiary harmonic wave and less than the wavelength of the tertiary harmonic wave (specifically, in the present embodiment, it is set to be the half wavelength of the tertiary harmonic wave). Therefore, as can be understood from the electric field simulation result illustrated in Fig. 21, it is possible to reduce the tertiary harmonic wave transmitted to the output side.
Further, according to the multilayer substrate 10a of the modified example, the value of L7 (the distance between the intermediate region rightmost via 44R and the intermediate region leftmost via 44L) is set to be equal to or more than the half wavelength of the secondary harmonic wave and less than the wavelength of the secondary harmonic wave (specifically, in the present embodiment, it is set to be the half wavelength of the secondary harmonic wave). Therefore, as can be understood from the electric field simulation result illustrated in Fig. 20, it is possible to reduce the secondary harmonic wave transmitted to the output side.
That is, according to the multilayer substrate 10a of the modified example, transmission of multiple harmonic waves (the secondary harmonic wave and tertiary harmonic wave in the embodiment) desired to reduce the transmission to the output side is easily reduced by appropriately adjusting the values of L6 and L7.
(2) Fig. 22 is a view schematically illustrating a cross-sectional shape of the multilayer substrate 10b according to the modified example to correspond to Fig. 18. In the multilayer substrate 10a illustrated in Fig. 18, the intermediate region rightmost via 44R and the intermediate region leftmost via 44L are provided to extend between the third ground pattern 31 and the fourth ground pattern 36 in the vertical direction, but the present disclosure is not limited thereto. Specifically, referring to Fig. 22, the intermediate region rightmost via 46R and the intermediate region leftmost via 46L may be provided to extend between the first ground pattern 20 and the fourth ground pattern 36 in the vertical direction. Even in this case, it is possible to obtain the same effects as those of the multilayer substrate 10a illustrated in Figs. 17 and 18. Further, in Fig. 22, the hatching of the dielectric layers 11, 12 and 13 is omitted to avoid making the drawing complicated.

[Reference Signs List]

1 Radar device
10, 10a, 10b Multilayer substrate
11 First dielectric layer (dielectric layer)
12 Second dielectric layer (dielectric layer)
13 Third dielectric layer (dielectric layer)
16 Signal line
20 First ground pattern (ground layer)
21 Input side region ground layer (input side ground layer)
22 Intermediate region ground layer (intermediate ground layer)
23 Output side region ground layer (output side ground layer)
26 Second ground pattern (ground layer, intermediate ground layer)
31 Third ground pattern (ground layer, intermediate ground layer)
36 Fourth ground pattern (ground layer)
37 Input side region ground layer (input side ground layer)
38 intermediate region ground layer (intermediate ground layer)
39 Output side region ground layer (output side ground layer)
40 Via

Claims

A multilayer substrate (10, 10a, 10b), having an input side region, an intermediate region, and an output side region, and the multilayer substrate comprising:
a plurality of dielectric layers (11, 12, 13);

a plurality of ground layers (20, 26, 31, 36), provided on both surfaces of each of the plurality of dielectric layers, and the plurality of dielectric layers being stacked on each other via the ground layers;

a signal line (16), provided on a surface of one of the plurality of dielectric layers (11, 12, 13) that is provided at a top side of the plurality of dielectric layers (11, 12, 13), and the signal line (16) extending from the input side region through the intermediate region to the output side region; and

a plurality of vias (40), electrically connecting the plurality of ground layers by passing through at least one of the plurality of dielectric layers (11, 12, 13) in a stacking direction of the plurality of dielectric layers (11, 12, 13), wherein

the plurality of ground layers comprises:
a plurality of input side ground layers (21, 37), provided in the input side region where a signal through the signal line (16) is input,

a plurality of output side ground layers (23, 39), provided in the output side region where the signal through the signal line (16) is output, and

a plurality of intermediate ground layers (22, 26,31, 38), provided in the intermediate region, and the intermediate ground layers being disposed between the input side ground layers (21, 37) and the output side ground layers (23, 39), and

the input side ground layers (21, 37) provided in the input side region have fewer layers than the intermediate ground layer (22, 26, 31, 38) provided in the intermediate region, and

the output side ground layers (23, 39) provided in the output side region have fewer layers than the intermediate ground layer (22, 26, 31, 38) provided in the intermediate region;

wherein the plurality of vias (40) have a plurality of first vias (44R, 46R), a plurality of second vias (44L, 46L), a plurality of third vias (45R) and a plurality of fourth vias (45L) provided in the intermediate ground layer,

the plurality of first vias (44R, 46R) is arranged in a direction parallel to the signal line (16) on one side of the signal line (16),

the plurality of second vias (44L, 46L) is arranged in a direction parallel to the signal line (16) on an other side of the signal line (16),

the plurality of third vias (45R) is arranged in a direction parallel to the signal line (16) between the plurality of first vias (44R, 46R) and the signal line (16),

the plurality of fourth vias (45L) is arranged in a direction parallel to the signal line (16) between the plurality of second vias (44L, 46L) and the signal line (16),

a ground layer (20) disposed in the same layer as the signal line (16) among the plurality of ground layers is provided as a reference ground layer,

a ground layer (36) disposed on a side furthest from the reference ground layer among the plurality of ground layers in the stacking direction is provided as a first long distance ground layer,

a ground layer (31) closest to the first long distance ground layer among the plurality of ground layers in the stacking direction is provided as a second long distance ground layer,

each of the first vias (44R, 46R) and each of the second vias (44L, 46L) extend in the stacking direction to electrically connect the first long distance ground layer and the second long distance ground layer, or electrically connect the reference ground layer and the first long distance ground layer, and a distance (L7) between the first vias (44R, 46R) and the second vias (44L, 46L) is set to be equal to or more than a half wavelength of a secondary harmonic wave of the signal transmitted and received through the signal line (16) and less than a wavelength of the secondary harmonic wave, and

each of the third vias (45R) and each of the fourth vias (45L) extend in the stacking direction to electrically connect the reference ground layer and the second long distance ground layer, and a distance (L6) between the third vias (45R) and the fourth vias (45L) is set to be equal to or more than a half wavelength of a tertiary harmonic wave of the signal transmitted and received through the signal line (16) and less than a wavelength of the tertiary harmonic wave.
The multilayer substrate (10, 10a, 10b) according to claim 1, wherein two input side ground layers (21, 37) and two output side ground layers (23, 39) are formed, and three or more intermediate ground layers (22, 26, 31, 38) are formed.
The multilayer substrate (10, 10a, 10b) according to claim 1, wherein a length (L2) of an intermediate region signal line (16) portion formed in the intermediate region of the signal line (16) is set to be an integral multiple of the half wavelength of the secondary harmonic wave.
The multilayer substrate (10, 10a, 10b) according to claim 3, wherein a length (L3) of an input side region signal line (16) portion formed in the input side region of the signal line (16) is set on the basis of an impedance of the secondary harmonic wave.
The multilayer substrate (10, 10a, 10b) according to claim 3, wherein a value obtained by adding a distance (L4) from the intermediate region signal line (16) portion formed in the intermediate region of the signal line (16) to the first vias (44R, 46R) or the second vias (44L, 46L) and a distance (L5) from the ground layer of the plurality of ground layers closest to the reference ground layer to the first long distance ground layer is set to be a quarter of the wavelength of the secondary harmonic wave transmitted and received through the signal line (16).
A radar device (1) comprising the multilayer substrate (10, 10a, 10b) according to any one of claims 1 to 5.