EP3355475B1 - Signalverarbeitungsanordnung für einen hall-sensor und signalverarbeitungsverfahren für einen hall-sensor - Google Patents

Signalverarbeitungsanordnung für einen hall-sensor und signalverarbeitungsverfahren für einen hall-sensor Download PDF

Info

Publication number
EP3355475B1
EP3355475B1 EP17153931.5A EP17153931A EP3355475B1 EP 3355475 B1 EP3355475 B1 EP 3355475B1 EP 17153931 A EP17153931 A EP 17153931A EP 3355475 B1 EP3355475 B1 EP 3355475B1
Authority
EP
European Patent Office
Prior art keywords
signal
compensation
path
current
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP17153931.5A
Other languages
English (en)
French (fr)
Other versions
EP3355475A1 (de
Inventor
Gerhard Oberhoffner
Dominik Ruck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram AG
Original Assignee
Ams AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ams AG filed Critical Ams AG
Priority to EP17153931.5A priority Critical patent/EP3355475B1/de
Priority to US16/481,769 priority patent/US11009563B2/en
Priority to CN201880009294.0A priority patent/CN110249533B/zh
Priority to PCT/EP2018/052428 priority patent/WO2018141806A1/en
Publication of EP3355475A1 publication Critical patent/EP3355475A1/de
Application granted granted Critical
Publication of EP3355475B1 publication Critical patent/EP3355475B1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/1023—Offset correction
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/14—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks
    • G01R15/20—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices, i.e. measuring a magnetic field via the interaction between a current and a magnetic field, e.g. magneto resistive or Hall effect devices
    • G01R15/202—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices, i.e. measuring a magnetic field via the interaction between a current and a magnetic field, e.g. magneto resistive or Hall effect devices using Hall-effect devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/0023—Electronic aspects, e.g. circuits for stimulation, evaluation, control; Treating the measured signals; calibration
    • G01R33/0029—Treating the measured signals, e.g. removing offset or noise
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
    • G01R33/06—Measuring direction or magnitude of magnetic fields or magnetic flux using galvano-magnetic devices
    • G01R33/07—Hall effect devices
    • G01R33/072—Constructional adaptation of the sensor to specific applications
    • G01R33/075—Hall devices configured for spinning current measurements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

Definitions

  • This invention relates to a signal processing arrangement for a Hall sensor and to a signal processing method for a Hall sensor.
  • Figure 7 shows a prior art offset compensation arrangement for a Hall sensor.
  • the arrangement comprises a signal path, a converter path and a feedback path.
  • the signal path includes a series connection of a Hall element and a low noise amplifier as front-end amplifier.
  • the Hall element is connected to a chopping circuit.
  • An output of the front-end amplifier is connected to a first circuit node.
  • the converter path comprises a series connection of an analog-to-digital converter, a first de-chopping circuit and a digital signal processor having an output terminal.
  • a low pass filter is connected between the first circuit node and the analog-to-digital converter.
  • the analog-to-digital converter is connected to the first de-chopping circuit via a second circuit node.
  • the feedback path comprises a series connection of a second de-chopping circuit and a feedback digital-to-analog converter which connects the first circuit node to the second circuit node.
  • the chopping circuit receives a chopping signal fchop which implements a spinning current in the Hall element.
  • the Hall element outputs two output signals S1, S2 which are provided at inputs V+, V- of the front-end amplifier.
  • the front-end amplifier amplifies these signals S1, S2 which are then filtered and provides as output signal of the signal path when input into the converter path.
  • the analog-to-digital converter converts the output signal into digital values.
  • the first de-chopping circuit determines a digital offset corrected output value, e.g. as the difference of the digital values.
  • the digital offset corrected output value may then be further processed by the digital signal processor, e.g. a cordic, to determine linear or angular position information related to the Hall element. If implemented as a cordic, the digital signal processor is arranged to digitally process signals from two or more channels in order to determine position and/or angle information, for example.
  • the second de-chopping circuit determines a digital feedback offset output value, e.g. as the sum of the digital values.
  • the digital feedback offset output value is converted into an analog feedback signal by means of the feedback digital-to-analog converter.
  • the analog feedback signal then is injected into the signal path via the first circuit node and thereby subtracted from the output signal.
  • Figure 8 shows another prior art offset compensation arrangement for a Hall sensor.
  • the arrangement is a further development of the arrangement of Figure 7 .
  • the signal path comprises a series connection of hall element, represented by two consecutive amplifiers, a mixer followed by an adder, the front-end amplifier, another adder and a buffer.
  • the converter path is represented by the analog-to-digital, a first filter, another mixer and a second filter.
  • the feedback path comprises a third filter and the feedback digital-to-analog converter.
  • the implementations shown in Figures 7 and 8 have some disadvantages.
  • the analog-to-digital converters, ADC are designed to cope with a maximum input in order to allow for a small quantization step. But with the offset added to the signal the ADCs may saturate and the signal is masked.
  • the loop implemented by the feedback paths starts to decrease the offset based on the sampling frequency of the system but has also to maintain a stable loop therefore the maximum step the loop can do each step is limited. Until the loop is settled the resulting signal value is not valid because the ADCs may or may not have clipped due to a too high offset value. This fact limits the start-up time in low power applications. In order to create one sample the device first has to go through the complete offset compensation phase before the desired sample can be generated.
  • CMOS 3D Hall probe for magnetic field measurement in MRI scanner presents a 3D Hall probe integrated in a 0.35 m CMOS technology and dedicated to the measurement of the magnetic field gradients in a MRI scanner. It features a 3D Hall device and three instrumentation chains which suppress the MRI main magnetic field and amplify dedicated magnetic field gradients.
  • DRAXELMAYR D ET AL "A Chopped Hall Sensor With Small Jitter and Programmable True Power-On Function ", discloses a chopping technique and self-compensation methods for temperature drift and technology spread, providing a correct output state immediately after power-on even at zero speed of the target wheel.
  • the novel combination of chopping and enhanced digital self-calibration algorithm adjusts the magnetic switching point and improves phase accuracy.
  • US Patent Publication no. US 9 448 288 B2 discloses a system operable to reduce the DC offsets of a plurality of magnetic field sensing elements (e.g., vertical Hall elements of a CVH sensing element).
  • a plurality of magnetic field sensing elements e.g., vertical Hall elements of a CVH sensing element.
  • An improved concept discussed below is based on the idea to compensate an offset of a Hall element directly at the signal front-end, thus taking an analog-to-digital converter, ADC, out of the equation and thereby eliminating the required waiting time.
  • An offset compensation phase can be much quicker and the arrangement can do a wakeup-compensate-measure-power down cycle using less energy than in other solutions decreasing the average power consumption. Since in the improved concept the offset is compensated after the first phase the required startup time is substantially reduced because the first sample already is offset-free.
  • the improved concept can be realized in a much smaller area than the current solution because existing structures of already existing cells can be adapted to form the functionality.
  • the offset loop is wrapped around the hall element and/or a front-end amplifier instead of involving the whole signal chain. Since the ADC offset can be compensated using the chopping and current spinning approaches the remaining target of the improved concept is to reduce the offset to an amount where it fits in the ADC dynamic range already at the first sampling phase.
  • a signal processing arrangement for a whole sensor comprises a signal path, a feedback path and a converter path.
  • the signal path comprises a Hall element and a front-end amplifier connected in series.
  • the signal path is arranged to generate an output signal depending on a magnetic field.
  • the feedback path comprises a compensation circuit and is coupled to the signal path.
  • the converter path comprises an analog-to-digital converter and an offset compensation circuit, and is coupled to the signal path.
  • the switch network is coupled between the signal path, the feedback path and the converter path.
  • the switch network electrically connects the feedback path to the signal path.
  • the compensation circuit By way of the electrical connection the compensation circuit generates a compensation signal which is coupled into the signal path.
  • the switch network electrically connects the signal path to the converter path. By way of the electrical connection the output signal is reduced by the compensation signal and is provided at the converter path.
  • the switch network electrically connects the feedback path to the signal path while the converter path is electrically disconnected from the signal path.
  • the compensation circuit comprises a feedback analog-to-digital converter connected to the switch network. Furthermore, the feedback digital-to-analog converter is coupled to the feedback analog-to-digital converter by means of a feedback adder.
  • the feedback path comprises a negative feedback loop.
  • the feedback path is arranged to adjust the compensation signal such that the output signal reaches a zero signal and/or a predetermined target signal.
  • the feedback path comprises a register to save a digital value indicative of the compensation signal in the compensation phase. Furthermore, the feedback path comprises an auxiliary amplifier which is connected to the signal path by on the switch network. The auxiliary amplifier is arranged to provide the compensation signal to the signal path.
  • the front-end amplifier comprises an adjustable compensation source.
  • the compensation source is arranged to receive the compensation signal and reduce the output signal by the compensation signal.
  • the adjustable compensation source comprises an adjustable bias current source and a compensation resistor which are arranged in a connecting branch of the current mirror between the first and the second transistor branches.
  • the offset compensation circuit comprises a dechopping circuit operating on a chopping clock signal.
  • the compensation phase and the sampling phase comprise at least two compensation sub-phases and two sampling sub-phases which are synchronized to the clock signal.
  • the feedback path is arranged to combine respective compensation signals from the compensation sub-phases into the compensation signal.
  • the control unit is arranged to operate the switching network according to the compensation phase and the sampling phase.
  • a signal processing method for a Hall sensor comprises the following steps.
  • a signal processing arrangement comprises a signal path comprising a Hall element and a front-end amplifier connected in series, a feedback path comprising a compensation circuit and a converter path comprising an analog-to-digital converter and an offset compensation circuit.
  • an output signal is generated.
  • the signal path is electrically connected to the feedback path.
  • the compensation signal is generated by means of the compensation circuit.
  • the compensation signal is coupled into the signal path.
  • the signal path is electrically connected to the converter path.
  • the output signal is reduced by the compensation signal. Finally, the reduced output signal is provided at the converter path.
  • the compensation signal is saved in the compensation phase and applied to the output signal in the sampling phase.
  • the compensation signal is adjusted such that the output signal reaches his zero signal and/or a predetermined target signal during the compensation phase.
  • the compensation signal is generated by means of a negative feedback of the feedback path. Generating the compensation signal involves an analog-to-digital conversion of the output signal followed by a digital-to-analog conversion. For example, the compensation signal is established in an ADC slope process comparable to a successive approximation concept.
  • the output signal in the compensation phase, is the chopped and offset compensated downstream and analog-to-digital conversion by means of the analog-to-digital converter.
  • Figure 1 shows an exemplary embodiment of a signal processing arrangement for a Hall sensor.
  • the signal processing arrangement comprises a signal path 1, a feedback path 3 and a converter path 5.
  • the signal path 1 comprises a series connection with a Hall element 11, 12, a first multiplier 13, a first adder 14, a second adder 15 and a front-end amplifier 16.
  • the Hall element 11, 12 is represented by two consecutive amplifiers 11 and 12.
  • the front-end amplifier 16 is coupled to the feedback path 3 and to the converter path 5 by means of a switching network.
  • the switching network comprises a first switch 21 and a second switch 22 and are connected to a first circuit node N1.
  • An offset terminal 17 is connected to a positive input of the first adder 14.
  • the feedback path 3 spans from the first circuit node N1 via the second switch 22 to the second adder 15.
  • the second switch 22 is connected to a feedback analog-to-digital converter 30 which is connected in series to a third adder 31 and a feedback digital-to-analog converter 32.
  • the feedback analog-to-digital converter 30 is connected to a negative input of the third adder 31.
  • a positive input of the third adder 31 is connected to a target terminal 33.
  • the feedback digital-to-analog converter 32 is connected to a negative input of the second adder 15.
  • the converter path 5 is connected to the first circuit node N1 and comprises a series connection of a buffer 50, an analog-to-digital converter 51, a first filter 52, a second multiplier 53 and a second filter 54. Furthermore, the converter path 5 comprises a de-chopping circuit 55 which is connected to the second multiplier 53 via a second circuit node N2. Additionally, the second circuit node N2 is connected to the first multiplier 13.
  • the Hall element 11, 12 detects a magnetic field B applied at a field input 18.
  • the Hall element 11, 12 is operated in a spinning current configuration and generates corresponding magnetic field signals S1, S2 depending on the flow of current in the Hall element.
  • These signals are amplified by means of the front-end amplifier 16.
  • an offset can be added via the offset terminal 17, e.g. to modulate an offset from the Hall element 11, 12 and the front-end amplifier 16 which typically have the same phase.
  • Both the Hall element 11, 12 and the front-end amplifier 16 are subject to offsets which is added as an additional signal component to an output signal SOUT of the signal path 1. In other words the offset of both Hall elements 11, 12 and front-end amplifier 16 are superimposed on the magnetic field signal.
  • the converter path 5 is arranged to convert the analog output signal SOUT of the signal path 1 into a digital output value DOUT. Basically, the conversion is performed by means of the analog-to-digital converter 51 but is complemented by filtering, e.g. low pass filtering, by means of the first filter 52. The resulting digital value is dechopped using the de-chopping circuit 55 and the second multiplier 53. The dechopped digital value is filtered, e.g. low pass filtered, by means of the second filter 52 and provided as the digital output value DOUT at an output terminal 56.
  • the converter path 5 performs offset correction using chopping and current spinning.
  • the feedback path 3 is designed to generate a compensation signal TARGET which is coupled or fed back into the signal path 1.
  • the feedback path 3 is constructed as a negative feedback loop so the compensation signal SCOR is subtracted from the output signal SOUT.
  • the compensation signal SCOR can be influenced via the target terminal 33, e.g. by applying a target signal TARGET at the target terminal 33.
  • the compensation signal TARGET is largely determined by the implementation of the feedback analog-to-digital converter 30 and the feedback digital-to-analog converter 32 which, considered together, constitute a compensation circuit. Further details will be discussed in Figure 2 .
  • the signal processing arrangement is operated in consecutive phases including a compensation phase ⁇ COMP and a sampling phase ⁇ SAMP.
  • the phases are largely determined by switching states of the first and the second switch 21, 22.
  • the first and second switch electrically connect the feedback path 3 to the signal path 1.
  • the output signal SOUT from the front-end amplifier 16 is fed into the feedback path 3 which generates the compensation signal SCOR.
  • the compensation signal SCOR can be fed into the signal path 1 right away or be saved in a register (see Figure 5 ) and only applied during the sampling phase ⁇ SAMP.
  • the sampling phase ⁇ SAMP is the first and the second switch 21, 22 connect the signal path 1 to the converter path 5 and the output signal SOUT, reduced by the compensation voltage SCOR, is provided at the analog-to-digital converter 51.
  • the output signal SOUT can be reduced to an amount where it better fits to the dynamic range of the analog-to-digital converter 51 during the sampling phase ⁇ SAMP.
  • the compensation signal SCOR can be superimposed with the compensation phase ⁇ COMP and sampling phase ⁇ SAMP running in parallel or the compensation signal SCOR is saved and only presented to the signal path 1 during the sampling phase ⁇ SAMP. In both cases, bandwidth requirements of the analog-to-digital converter 51 can be relaxed and, in turn, startup times can be reduced. This is largely due to the fact that the feedback path 3 is "wrapped" around the front-end amplifier 16 instead of being part of the converter path 5.
  • the feedback path 3 is coupled back to the Hall element 11, 12 instead of the front-end amplifier 16.
  • the compensation signal SCOR can be injected directly into the Hall element 11, 12 which is then detuned by a value determined by the compensation signal SCOR.
  • the compensation signal can be injected downstream the Hall element 11, 12 and before the front-end amplifier 16.
  • the first filter 52 in Figures 1 and 4 may alternatively be arranged in front of the analog-to-digital converter 51. This way the first filter may act as an antialising filter. Furtermore, two filters may also be implemented, one in front and one downstream the the analog-to-digital converter 51.
  • FIG. 2 shows an exemplary embodiment of a feedback path.
  • the drawing represents a very basic representation of one possible compensation scheme to generate a compensation signal TARGET.
  • the front-end amplifier 16 is represented as a low noise amplifier LNA.
  • the front-end amplifier 16 is realized as an operational transconductance amplifier, OTA, with a transconductance gm.
  • the amplifier 16 has two input terminals V+, V- to receive a differential input voltage from the Hall element 11, 12. On its output side the front-end amplifier 16 is connected to a current output terminal 35 via the first switch 21 which can be operated by means of an enable terminal 43.
  • the output side of the front-end amplifier 16 is connected to the input side of an inverting comparator, inverter 36, with hysteresis.
  • the output side of the inverter 36 is connected to a low pass filter 38 comprising a fourth adder 39 and a delay element 40.
  • the low-pass filter is connected to a clock terminal.
  • An auxiliary amplifier 41 connects an output of the low-pass filter 38 to an adjustable compensation source 42 arranged at the negative input side of the front-end amplifier 16.
  • a nominal output signal SOUT is generated by the Hall element 11, 12 which is superimposed with an offset, denoted offset signal hereinafter (see Figure 1 or 4 ).
  • the feedback path 3 essentially is designed as a negative feedback loop so that the offset signal can be regulated by generating a zero signal as output of the front-end amplifier 16.
  • the feedback path 3 essentially is designed to generate, during the compensation phase ⁇ COMP, a zero signal as signal output of the signal path 1.
  • a compensation voltage VCOR is used during the sampling phase ⁇ SAMP to generate an offset reduced output signal SOUT to be provided at the converter path 5 for analog-to-digital conversion and further signal processing.
  • the zero signal can be adjusted by means of a target signal TARGET applied to the target terminal 33 (not shown, see also Figure 1 ).
  • the target signal TARGET can be adjusted to different signal levels.
  • a zero level corresponds to the zero signal mentioned above.
  • any value in between is possible and only restricted by the specific needs of a given application.
  • the output of the front-end amplifier 16 is closed to the current output terminal 35. This is achieved by means of an enable signal EN_COMP applied the enable terminal forcing the first switch 21 to open and electrically disconnect the front-end amplifier 16 to the current output terminal 35. At the same time second switch 22 is closed. This essentially turns the current output of the front-end amplifier 16 into a comparator, i.e. a high ohmic current source. In fact, a gain of the front-end amplifier 16 is high as there is no further resistance on its output side. Depending on the value of the transconductance gm, the amplifier 16 generates an output current IFE. As a consequence the output of the front-end amplifier 16 (operated as comparator) is at a positive supply voltage VDD if the input offset signal is positive in value or at a negative supply voltage VSS if the offset signal is negative in value.
  • the output signal SOUT of the front-end amplifier 16, represented as output current IFE, is injected into the feedback path 3 via the second switch 22.
  • the output signal SOUT is then corrected by the compensation signal SCOR in the digital domain and a corresponding compensation voltage VCOR is generated in the analog domain which is then fed back into the signal path 1.
  • the feedback path 3 essentially constitutes a negative feedback loop which is repeatedly passed through until a stable output signal SOUT is established.
  • the compensation signal SCOR is established in an ADC slope process comparable to a successive approximation concept.
  • the feedback path 3 in this embodiment constitutes an integrating register which can be present during a reset to a mid-code (FSR/2). If the output signal SOUT of the front-end amplifier 16 is 0, i.e. indicating an offset smaller in value than 0, the feedback path 3 by means of the inverter 36 starts adding 1's to the compensation signal SCOR (digital), e.g. by increasing a compensation code at every clock edge of a clock signal CLK applied to the delay element 40 via a clock terminal 44.
  • the low pass filter 38 constitutes a digital-to-analog converter depending on the clock signal CLK applied at the clock terminal 44.
  • the filter or ADC constitutes an up/down counter. The filter could settle within a settling time determined by the filter constant of the first filter 52.
  • a clock frequency fclk can be derived from Tclk ⁇ 1/(2 ⁇ fclk ⁇ N/2) which, given the values above, may result in 3 MHz.
  • the clock could range from 2 to 10 MHz.
  • the auxiliary amplifier 41 amplifies the (analog) compensation signal SCOR.
  • the adjustable compensation source 42 is adjusted such that the compensation voltage VCOR is injected in the negative input V- of the front-end amplifier 16.
  • the output signal SOUT of the front-end amplifier 16 flips to 1 and the integrator decreases its code again in the following clock edge of the clock signal CLK.
  • the feedback path 3 toggles with ⁇ 1 LSB, least significant bits, around 0 V.
  • FIG 3 shows an exemplary embodiment of a front-end amplifier.
  • the front-end amplifier 16 is divided into two transistor branches 100, 120 which are connected as a current mirror. Furthermore, the two transistor branches 100, 120 are connected via a compensation resistor R1 which is connected to VDDA (positive supply voltage VDD analog) via an adjustable bias current source I1.
  • VDDA positive supply voltage VDD analog
  • the first transistor branch 100 comprises first current path 101 comprising transistors M5 and M7 connected between VDDA and VSSA (negative supply voltage VSS analog).
  • a second current path 102 comprises transistor M1 which is connected between the compensation resistor R1 and VSSA via a first current source 104.
  • a control side of transistor M1 is connected to the negative input terminal V-.
  • a third current path 103 is connected between both the compensation resistor R1 and the second current path 102 and VSSA.
  • the three current paths 101, 102, 103 are interconnected via respective control sides of transistors M5 and M3 and circuit node N3.
  • the second transistor branch 120 comprises first current path 121 comprising transistors M6 and M8 connected between VDDA and VSSA (negative supply voltage VSS analog).
  • a second current path 122 comprises transistor M2 which is connected between the compensation resistor R1 and VSSA via a first current source 124.
  • a control side of transistor M2 is connected to the positive input terminal V+.
  • a third current path 123 is connected between both the compensation resistor R1 and the second current path 122 and VSSA.
  • the three current paths 121, 122, 123 are interconnected via respective control sides of transistors M4 and M6 and circuit node N4. Circuit node N5 located between the transistors M6 and M8 is connected to the current output terminal 35.
  • the two transistors M1 and M2 copy the input voltage, i.e. the output signal of the Hall element 11, 12, onto the compensation resistor R1.
  • the resulting current flow through R1 is modulating a current through transistors M3 and M4 and the difference in current is copied to the current output terminal 35 using transistors M5, M6 and M7, M8 respectively.
  • the compensation source is implemented by moving the injection point of the current source I1 within the compensation resistor R1, e.g. the more left or right the injection point moves the more differential voltage is generated artificially on R1 thus changing the current in M3 and M4 and therefore the output.
  • This asymmetry on the compensation resistor R1 is a measure of the offset contribution in the output signal of the signal path 1.
  • the front-end amplifier 16 is used as a comparator and the feedback path 3 is used to adjust a zero signal as the output of the front-end amplifier during compensation phase ⁇ COMP, Using the clock signal CLK with high frequencies a high number of taps is possible.
  • the front-end amplifier can be used with a higher bandwidth which is one reason why the start-up time of the proposed signal processing arrangement can be improved.
  • the feedback path may reuse a structure already in place in the front-end.
  • the switches may be added in addition to the existing structure.
  • BW bandwidth
  • 3 ⁇ can be considered setting the conversion time needed for one step to around 5 ns.
  • a 128 steps DAC can be evaluated in less than 20 ⁇ s compared to 3 conversions at 20kHz sampling rate (150 ⁇ s) using a conventional approach.
  • One limiting factor for the proposed concept is the noise generated within such a high bandwidth, e.g. by means of the adjustable current source, but this only limits the resolution of the offset DAC which typically is not a critical parameter for the system.
  • the noise generated within such a high bandwidth e.g. by means of the adjustable current source, but this only limits the resolution of the offset DAC which typically is not a critical parameter for the system.
  • an 8 bit DAC would give a LSB size of 39 ⁇ V.
  • the estimated input related RMS noise would be around 34 ⁇ VRMS yielding a maximum error of around 100 ⁇ V after the compensation is done.
  • Figure 4 shows another exemplary embodiment of a signal processing arrangement for a Hall sensor. This embodiment is a further development of the one depicted in Figure 1 .
  • the feedback path 3 comprises a low-pass filter after the feedback digital-to-analog converter. This filter may be implemented around the principles discussed in Figure 2 .
  • Figure 5 shows a signal processing arrangement for a Hall sensor. It implements two compensation phases ⁇ COMP1, ⁇ COMP2.
  • the converter path 5 is similar to the one shown in Figure 7 .
  • the signal path 1 comprises a modified front-end amplifier 16 which comprises a compensation resistor as suggested in Figure 3 .
  • the feedback path 3 is connected to the signal path 1 via the compensation resistor R1.
  • the feedback path 3 comprises the second switch, the inverter which is connected to an up/down counter 45. Furthermore, the up/down counter 45 is connected to a clock 49. As an example, clock values could range from 2 to 10 MHz as discussed above.
  • An output of the up/down counter 45 is connected to a sixth circuit node N6 and splits into three circuit branches.
  • the first circuit branch connects the sixth circuit node N6 via a third switch 23 and sixth circuit node N6 to the front-end amplifier 16, in particular, to the compensation resistor R1.
  • the second and third circuit branches each comprise a register 46, 47 which at their respective output sides are connected to positive inputs of an adder 48.
  • An output of the adder 48 connects to the auxiliary amplifier 41.
  • the auxiliary amplifier 41 at its output side, is connected to the sixth circuit node N6 via a fourth switch 24.
  • FIG. 6 shows exemplary timing diagram for a signal processing arrangement for a Hall sensor. The drawing is based on the embodiment of Figure 5 .
  • the timing diagram shows several characteristic signals as a function of time t.
  • the signal processing arrangement is operated in two consecutive operation phases, i.e. a compensation phase ⁇ COMP followed by a sampling phase ⁇ SAMP.
  • the compensation phase ⁇ COMP is divided into two consecutive compensation phases ⁇ COMP1, ⁇ COMP2 which are defined by the chopping signal FCHOP of chopping circuit 55.
  • the sampling phase ⁇ SAMP is divided into two consecutive sampling phases ⁇ SAMP1, ⁇ SAMP2 which are defined by the chopping signal FCHOP of chopping circuit 55.
  • the consecutive compensation phases ⁇ COMP1, ⁇ COMP2 and consecutive sampling phases ⁇ SAMP1, ⁇ SAMP2 are synchronized to the chopping of the Hall element 11, 12 in a spinning current process.
  • the timing diagram shows a first and second register signal ⁇ 1, ⁇ 2, an output signal of the up/down converter SCOUNT, output signals of the first and second register OFF_PH1, OFF_PH2, an output signal of the auxiliary amplifier GFB as well as the output signal SOUT of the signal path 1 represented as the output voltage VOUT_LNA with respect to analog ground AGND.
  • the Hall element has a first current orientation.
  • the feedback path 3 by means of the up/down counter creates a first value for OFFSET + SIGNAL (denoted nominal code - offset 1 in the drawing) which is saved in the first register 46 as register signal OFF_PH1.
  • the Hall element has a second current orientation.
  • the feedback path 3 by means of the up/down counter 45 creates a second value for OFFSET - SIGNAL (denoted nominal code - offset 2 in the drawing) which is saved in the second register 47 as register signal OFF_PH2.
  • the first and second registers 46, 47 are activated by the first and second register signal ⁇ 1, ⁇ 2, respectively, and provided their saved register signals OFF_PH1, OFF_PH2 to the auxiliary amplifier 41 after adding them with the adder 48.
  • the adder 48 sums the register signals OFF_PH1, OFF_PH2 and divides them by two (by scaling factor 0.5 of the auxiliary amplifier 41 in the drawing) to get the real offset value and feeds this information back into the signal path 1 via the compensation resistor R1 as seen in Figure 5 .

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Measuring Magnetic Variables (AREA)
  • Hall/Mr Elements (AREA)
  • Analogue/Digital Conversion (AREA)
  • Amplifiers (AREA)

Claims (9)

  1. Signalverarbeitungsanordnung für einen Hall-Sensor mit:
    - einen Signalpfad (1) mit einem Hall-Element (11, 12) und einem in Reihe geschalteten Front-End-Verstärker (16), der so beschaffen ist, dass er ein Ausgangssignal (SOUT) in Abhängigkeit von einem Magnetfeld (B) erzeugt,
    - einen Rückkopplungspfad (3) mit einer Kompensationsschaltung, der mit dem Signalpfad (1) gekoppelt ist,
    - einen Wandlerpfad (5) mit einem Analog-Digital-Wandler (51) und einer Offset-Kompensationsschaltung, die in Reihe geschaltet sind, wobei der Analog-Digital-Wandler (51) mit dem Signalpfad (1) gekoppelt ist,
    - ein Schaltnetzwerk (21, 22, 23, 24), das zwischen dem Signalpfad (1), dem Rückkopplungspfad (3) und dem Wandlerpfad (5) gekoppelt ist; und wobei die Signalverarbeitungsanordnung in aufeinanderfolgenden Phasen betrieben wird, die eine Kompensationsphase (COMP) und eine Abtastphase (SAMP) umfassen:
    - in der Kompensationsphase (COMP) verbindet das Schaltnetzwerk (21, 22, 23, 24) den Rückkopplungspfad (3) elektrisch mit dem Signalpfad (1), so dass die Kompensationsschaltung ein Kompensationssignal (SCOR) erzeugt, das in den Signalpfad (1) eingekoppelt wird, und
    - in der Abtastphase (SAMP) das Schaltnetzwerk (21, 22, 23, 24) den Signalpfad (1) mit dem Wandlerpfad (5) verbindet, so dass das um das Kompensationssignal (SCOR) reduzierte Ausgangssignal (SOUT) am Wandlerpfad (5) bereitgestellt wird; ferner umfassend
    - einen ersten Schaltungsknoten (N1), der den Signalpfad (1) mit dem Wandlerpfad (5) verbindet und mit dem Rückkopplungspfad (3) verbunden ist, wobei sich der Rückkopplungspfad (3) erstreckt:
    - von dem ersten Schaltungsknoten (N1) über das Schaltnetzwerk zu einer Eingangsseite des Front-End-Verstärkers (16), wobei:
    - der Front-End-Verstärker (16) eine einstellbare Kompensationsquelle (42) umfasst, die so angeordnet ist, dass sie das Kompensationssignal (SCOR) empfängt und das Ausgangssignal (SOUT) um das Kompensationssignal (SCOR) reduziert,
    - die einstellbare Kompensationsquelle (42) eine einstellbare Vorspannungsstromquelle (I1) und einen Kompensationswiderstand (R1) umfasst, der über die einstellbare Vorspannungsstromquelle (I1) mit einer Spannungsversorgung (VDDA) verbunden ist, wobei die Kompensationsquelle (42) durch Bewegen eines Injektionspunktes der Stromquelle (I1) innerhalb des Kompensationswiderstandes (R1) implementiert ist; und wobei:
    - in der Kompensationsphase (COMP) das Schaltnetzwerk (21, 22, 23, 24) den Rückkopplungspfad (3) mit dem Signalpfad (1) elektrisch verbindet, während der Wandlerpfad (5) vom Signalpfad (1) elektrisch getrennt ist,
    - wobei der Rückkopplungspfad (3) ein erstes Register (46) und ein zweites Register (47) umfasst, die jeweils angeordnet sind, um digitale Werte zu speichern, die das Kompensationssignal (SCOR) in der Kompensationsphase (COMP) anzeigen, und ferner einen Hilfsverstärker (41) umfasst, der mit dem Signalpfad (1) über das Schaltnetzwerk (21, 22, 23, 24) verbunden ist, um das Kompensationssignal (SCOR) an die einstellbare Kompensationsquelle (42) zu liefern, und wobei
    - die Offset-Kompensationsschaltung eine De-Chopping-Schaltung (55) umfasst, die mit einem Chopping-Taktsignal (fchop) arbeitet,
    - die Kompensationsphase (COMP) und die Abtastphase (SAMP) mindestens zwei Kompensationsphasen (COMP1, COMP2) und zwei Abtastphasen (SAMP1, SAMP2) umfassen, so dass die aufeinanderfolgenden Kompensationsphasen (COMP1, COMP2) und die aufeinanderfolgenden Abtastphasen (SAMP1, SAMP2) mit dem Taktsignal (fchop) synchronisiert sind, das das Hall-Element (11, 12) in einem Spinningstromprozess choppt, und
    - der Rückkopplungspfad (3) angeordnet ist, um die digitalen Werte von zwei Kompensationsphasen (COMP1, COMP2) zu dem Kompensationssignal (SCOR) zu kombinieren, wobei:
    - der Rückkopplungspfad (3) einen Schalter (22) des Schaltnetzes und einen Wechselrichter umfasst, der mit dem Schalter (22) und mit einem Vorwärts-/Rückwärtszähler (45) verbunden ist,
    - der Vorwärts-/Rückwärtszähler (45) mit einem Taktgeber (49) verbunden ist,
    - ein Ausgang des Vorwärts-/Rückwärtszählers (45) mit einem Schaltungsknoten (N6) verbunden ist und sich in drei Schaltungszweige aufteilt,
    - ein erster Schaltungszweig verbindet den Schaltungsknoten (N6) über einen weiteren dritten Schalter (23) des Schaltnetzwerks und den Schaltungsknoten (N6) mit der einstellbaren Kompensationsquelle des Front-End-Verstärkers (16),
    - einen zweiten Schaltungszweig, der das erste Register (46) umfasst, und einen dritten Schaltungszweig, der das zweite Register (47) umfasst, die an ihren jeweiligen Ausgangsseiten mit positiven Eingängen eines Addierers (48) verbunden sind,
    - ein Ausgang des Addierers (48) mit dem Hilfsverstärker (41) verbunden ist,
    - der Hilfsverstärker (41) ausgangsseitig über einen weiteren Schalter (24) des Schaltnetzes mit dem Schaltungsknoten (N6) verbunden ist, wobei:
    - während der ersten Kompensationsphase (COMP1) das Hall-Element eine erste Stromorientierung aufweist,
    - der Rückkopplungspfad (3) mit Hilfe des Vorwärts-/Rückwärtszählers einen ersten Wert OFFSET + SIGNAL erzeugt, der im ersten Register (46) als erstes Registersignal (OFF_PH1) gespeichert wird,
    - während der zweiten Kompensationsphase (COMP2) das Hall-Element eine zweite Stromorientierung aufweist,
    - der Rückkopplungspfad (3) mit Hilfe des Vorwärts-/Rückwärtszählers (45) einen zweiten Wert OFFSET - SIGNAL erzeugt, der im zweiten Register (47) als zweites Registersignal (OFF_PH2) gespeichert wird,
    - das erste und das zweite Register (46, 47) durch erste bzw. zweite Registeraktivierungssignale (1, 2) aktiviert werden und ihre gespeicherten Registersignale (OFF_PH1, OFF_PH2) dem Hilfsverstärker (41) zur Verfügung stellen, nachdem sie mit dem Addierer (48) addiert wurden, so dass der Addierer (48) nach den beiden Kompensationsphasen (COMP1, COMP2) die ersten und zweiten Registerwerte OFFSET + SIGNAL, OFFSET - SIGNAL summiert und mittels eines Skalierungsfaktors 0.5 des Hilfsverstärkers (41) durch zwei dividiert, um einen realen Offset-Wert zu erhalten, und den realen Offset-Wert über die einstellbare Kompensationsquelle in den Signalpfad (1) einspeist, wobei
    - in der Kompensationsphase (COMP) der Rückkopplungspfad (3) angeordnet ist, um das Kompensationssignal (SCOR) so einzustellen, dass das Ausgangssignal (SOUT) ein Nullsignal und/oder ein vorbestimmtes Zielsignal erreicht.
  2. Signalverarbeitungsanordnung nach Anspruch 1, wobei eine Ausgangsseite des Front-End-Verstärkers (16) über den ersten Schaltungsknoten (N1) mit einer Eingangsseite des Analog-Digital-Wandlers (51) verbunden ist.
  3. Signalverarbeitungsanordnung nach einem der Ansprüche 1 bis 2, wobei der Rückkopplungspfad (3) eine Gegenkopplungsschleife umfasst.
  4. Signalverarbeitungsanordnung nach einem der Ansprüche 1 bis 3, wobei
    - der Front-End-Verstärker (16) acht Transistoren M1 bis M8 umfasst,
    - ein erster Transistorzweig (100) einen ersten Strompfad (101) mit Transistor M5 und Transistor M7 umfasst, der zwischen die Spannungsversorgungsklemmen (VDDA, VSSA,
    - ein zweiter Strompfad (102) einen Transistor M1 umfasst, der über eine erste Stromquelle (104) zwischen den Kompensationswiderstand (R1) und den Spannungsversorgungsanschluss (VSSA) geschaltet ist, wobei eine Steuerseite des Transistors M1 mit einem negativen Eingangsanschluss (V-) verbunden ist,
    - ein dritter Strompfad (103) sowohl zwischen dem Kompensationswiderstand (R1) als auch dem zweiten Strompfad (102) und dem Versorgungsanschluss (VSSA) angeschlossen ist,
    - die drei Strompfade (101, 102, 103) über jeweilige Steuerseiten des Transistors M5 und des Transistors M3 und einen Schaltungsknoten (N3) miteinander verbunden sind, und wobei:
    - ein zweiter Transistorzweig (120) einen ersten Strompfad (121) umfasst, der einen Transistor M6 und einen Transistor M8 umfasst, die zwischen den Spannungsversorgungsanschlüssen (VDDA, VSSA,
    - ein zweiter Strompfad (122) einen Transistor M2 umfasst, der über eine erste Stromquelle (124) zwischen den Kompensationswiderstand (R1) und den Spannungsversorgungsanschluss (VSSA) geschaltet ist, wobei eine Steuerseite des Transistors M2 mit einem positiven Eingangsanschluss (V+) verbunden ist,
    - ein dritter Strompfad (123) sowohl zwischen dem Kompensationswiderstand (R1) als auch dem zweiten Strompfad (122) und dem Versorgungsanschluss (VSSA) angeschlossen ist
    - die drei Strompfade (121, 122, 123) über jeweilige Steuerseiten des Transistors M4 und des Transistors M6 und einen Schaltungsknoten (N4) miteinander verbunden sind, und
    - ein Schaltungsknoten (N5) befindet sich zwischen Transistor M6 und Transistor M8 und ist mit einer Stromausgangsklemme (35) verbunden.
  5. Signalverarbeitungsanordnung nach Anspruch 4, bei der die beiden Transistoren M1 und M2 so betreibbar sind, dass sie eine Eingangsspannung, d.h. ein Ausgangssignal des Hall-Elements (11, 12), auf den Kompensationswiderstand (R1) kopieren, so dass ein resultierender Stromfluss durch den Kompensationswiderstand (R1) einen Strom durch die Transistoren M3 und M4 moduliert und die Stromdifferenz unter Verwendung der Transistoren M5, M6 bzw. M7, M8 an den Stromausgangsanschluss (35) kopiert wird.
  6. Signalverarbeitungsanordnung nach einem der Ansprüche 1 bis 5, ferner mit einer Steuereinheit, die das Schaltnetz in der Kompensationsphase (COMP) und der Abtastphase (SAMP) betreibt.
  7. Signalverarbeitungsverfahren für eine Signalverarbeitungsanordnung nach einem der Ansprüche 1 bis 6 wobei das Verfahren die folgenden Schritte umfasst:
    Aufeinanderfolgende Phasen mit einer Kompensationsphase (COMP) und einer Abtastphase (SAMP):
    - Erzeugen eines Ausgangssignals (SOUT) des Signalpfads (1);
    - in der Kompensationsphase (COMP), elektrisches Verbinden des Rückkopplungspfades (3) mit dem Signalpfad (1), wobei in der Kompensationsphase (COMP) das Schaltnetzwerk (21, 22, 23, 24) den Rückkopplungspfad (3) mit dem Signalpfad (1) elektrisch verbindet, während der Wandlerpfad (5) elektrisch von dem Signalpfad (1) getrennt ist,
    - Speichern von digitalen Werten, die das
    Kompensationssignal (SCOR) in der Kompensationsphase (COMP) anzeigen;
    - Erzeugen des Kompensationssignals (SCOMP) mit Hilfe der Kompensationsschaltung;
    - Einkoppeln des Kompensationssignals (SCOMP) in den Signalpfad (1) durch Bewegen eines Injektionspunktes der Stromquelle (I1) innerhalb des Kompensationswiderstandes (R1); und
    - in der Abtastphase (SAMP), elektrisches Verbinden des Signalpfades (SP) mit dem Wandlerpfad (5),
    - Reduzieren des Ausgangssignals (SOUT) um das Kompensationssignal (SCOMP),
    - Bereitstellen des reduzierten Ausgangssignals an den Wandlerpfad (5), und wobei:
    - die Kompensationsphase (COMP) und die Abtastphase (SAMP) mindestens zwei Kompensationsphasen (COMP1, COMP2) und zwei Abtastphasen (SAMP1, SAMP2) umfassen, so dass die aufeinanderfolgenden Kompensationsphasen (COMP1, COMP2) und die aufeinanderfolgenden Abtastphasen (SAMP1, SAMP2) mit dem Taktsignal (fchop) synchronisiert sind, das das Hall-Element (11, 12) in einem Spinningstromprozess choppt, und
    - der Rückkopplungspfad (3) angeordnet ist, um die digitalen Werte von zwei Kompensationsphasen (COMP1, COMP2) zu dem Kompensationssignal (SCOR) zu kombinieren, und wobei:
    - der Rückkopplungspfad (3) mittels des Vorwärts-/Rückwärtszählers einen ersten Wert OFFSET + SIGNAL erzeugt, der in dem ersten Register (46) als erstes Registersignal (OFF_PH1) gespeichert wird,
    - während der zweiten Kompensationsphase (COMP2) das Hall-Element eine zweite Stromorientierung aufweist,
    - der Rückkopplungspfad (3) mit Hilfe des Vorwärts-/Rückwärtszählers (45) einen zweiten Wert OFFSET - SIGNAL erzeugt, der im zweiten Register (47) als zweites Registersignal (OFF_PH2) gespeichert wird,
    - das erste und zweite Register (46, 47) durch das erste bzw. zweite Registeraktivierungssignal (1, 2) aktiviert werden und ihre gespeicherten Registersignale (OFF_PH1, OFF_PH2) nach Addition mit dem Addierer (48) dem Hilfsverstärker (41) zur Verfügung stellen, so dass der Addierer (48) nach den beiden Kompensationsphasen (COMP1, COMP2) den ersten und zweiten Registerwert OFFSET + SIGNAL, OFFSET - SIGNAL summiert und mittels eines Skalierungsfaktors 0 des Hilfsverstärkers (41) durch zwei dividiert, um einen realen Offsetwert zu erhalten, und den realen Offsetwert über die einstellbare Kompensationsquelle in den Signalweg (1) einspeist, wobei
    - das Kompensationssignal (SCOR) so eingestellt wird, dass das Ausgangssignal (SOUT) während der Kompensationsphase (COMP) ein Nullsignal und/oder ein vorgegebenes Zielsignal erreicht.
  8. Verfahren nach Anspruch 7, wobei das Kompensationssignal (SCOR) in der Kompensationsphase (COMP) gespeichert und in der Abtastphase (SAMP) an das Ausgangssignal (SOUT) angelegt wird.
  9. Verfahren nach einem der Ansprüche 7 bis 8, wobei das Ausgangssignal (SOUT) nach einer Analog-Digital-Wandlung mittels des Analog-Digital-Wandlers (51) entchoppt und offsetkompensiert wird.
EP17153931.5A 2017-01-31 2017-01-31 Signalverarbeitungsanordnung für einen hall-sensor und signalverarbeitungsverfahren für einen hall-sensor Active EP3355475B1 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP17153931.5A EP3355475B1 (de) 2017-01-31 2017-01-31 Signalverarbeitungsanordnung für einen hall-sensor und signalverarbeitungsverfahren für einen hall-sensor
US16/481,769 US11009563B2 (en) 2017-01-31 2018-01-31 Signal processing arrangement for a hall sensor and signal processing method for a hall sensor
CN201880009294.0A CN110249533B (zh) 2017-01-31 2018-01-31 用于霍尔传感器的信号处理装置以及信号处理方法
PCT/EP2018/052428 WO2018141806A1 (en) 2017-01-31 2018-01-31 Signal processing arrangement for a hall sensor and signal processing method for a hall sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP17153931.5A EP3355475B1 (de) 2017-01-31 2017-01-31 Signalverarbeitungsanordnung für einen hall-sensor und signalverarbeitungsverfahren für einen hall-sensor

Publications (2)

Publication Number Publication Date
EP3355475A1 EP3355475A1 (de) 2018-08-01
EP3355475B1 true EP3355475B1 (de) 2022-09-07

Family

ID=57960279

Family Applications (1)

Application Number Title Priority Date Filing Date
EP17153931.5A Active EP3355475B1 (de) 2017-01-31 2017-01-31 Signalverarbeitungsanordnung für einen hall-sensor und signalverarbeitungsverfahren für einen hall-sensor

Country Status (4)

Country Link
US (1) US11009563B2 (de)
EP (1) EP3355475B1 (de)
CN (1) CN110249533B (de)
WO (1) WO2018141806A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018128469B4 (de) * 2018-11-14 2020-11-12 Senis Ag Magnetfeldsensor mit geringem Rauschen und hoher Bandbreite
CN110638156A (zh) * 2019-09-25 2020-01-03 歌尔股份有限公司 一种磁滞补偿方法、存储介质及智能穿戴设备
DE102019134077B4 (de) * 2019-12-12 2021-07-22 Infineon Technologies Ag Signalverarbeitungsschaltung für einen Hall-Sensor und Signalverarbeitungsverfahren
JP7361648B2 (ja) * 2020-03-27 2023-10-16 エイブリック株式会社 磁気センサ装置
IT202000007021A1 (it) * 2020-04-02 2021-10-02 St Microelectronics Srl Circuito convertitore, dispositivo e procedimento di compensazione dell'offset corrispondenti

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10032530C2 (de) * 2000-07-05 2002-10-24 Infineon Technologies Ag Verstärkerschaltung mit Offsetkompensation
KR100564866B1 (ko) * 2002-03-22 2006-03-28 아사히 가세이 일렉트로닉스 가부시끼가이샤 각도 검출 장치 및 각도 검출 시스템
GB2457699B (en) * 2008-02-22 2011-12-21 Red Lion 49 Ltd Differential audio amplifier
US7923996B2 (en) * 2008-02-26 2011-04-12 Allegro Microsystems, Inc. Magnetic field sensor with automatic sensitivity adjustment
JP5764340B2 (ja) * 2010-03-25 2015-08-19 ローム株式会社 モータ駆動回路およびそれを用いた冷却装置、電子機器
US9094015B2 (en) * 2011-01-14 2015-07-28 Infineon Technologies Ag Low-power activation circuit with magnetic motion sensor
US9448288B2 (en) * 2014-05-20 2016-09-20 Allegro Microsystems, Llc Magnetic field sensor with improved accuracy resulting from a digital potentiometer

Non-Patent Citations (9)

* Cited by examiner, † Cited by third party
Title
CALVO B ET AL: "Low-voltage Low-power CMOS IF Programmable Gain Amplifier", CIRCUITS AND SYSTEMS, 2006. MWSCAS '06. 49TH IEEE INTERNATIONAL MIDWES T SYMPOSIUM ON, IEEE, PI, 1 August 2006 (2006-08-01), pages 276 - 280, XP031113601, ISBN: 978-1-4244-0172-7 *
CHENG-CHUNG HSU ET AL: "A highly linear 125-mhz cmos switched-resistor programmable-gain amplifier", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 38, no. 10, 1 October 2003 (2003-10-01), pages 1663 - 1670, XP011101731, ISSN: 0018-9200, DOI: 10.1109/JSSC.2003.817665 *
DAI SHANSHAN ET AL: "1-V Low-Power Programmable Rail-to-Rail Operational Amplifier With Improved Transconductance Feedback Technique", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 21, no. 10, 1 October 2013 (2013-10-01), pages 1928 - 1935, XP011526441, ISSN: 1063-8210, [retrieved on 20130909], DOI: 10.1109/TVLSI.2012.2220387 *
KUMAR THANGARASU BHARATHA ET AL: "Temperature-Compensated dB-linear Digitally Controlled Variable Gain Amplifier With DC Offset Cancellation", IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, vol. 61, no. 7, 1 July 2013 (2013-07-01), USA, pages 2648 - 2661, XP055823759, ISSN: 0018-9480, Retrieved from the Internet <URL:https://ieeexplore.ieee.org/stampPDF/getPDF.jsp?tp=&arnumber=6517304&ref=aHR0cHM6Ly9pZWVleHBsb3JlLmllZWUub3JnL2RvY3VtZW50LzY1MTczMDQ=> DOI: 10.1109/TMTT.2013.2261086 *
LUJAÂ N-MARTIÂ NEZ C I ET AL: "CMOS linear programmable transconductor suitable for adjustable Gm-C filters", ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 44, no. 8, 10 April 2008 (2008-04-10), pages 505 - 506, XP006030916, ISSN: 0013-5194, DOI: 10.1049/EL:20080301 *
MAYA-HERNÁNDEZ PAULINA ET AL: "An Integrated Low-Power Lock-In Amplifier and Its Application to Gas Detection", SENSORS, vol. 14, no. 9, 27 August 2014 (2014-08-27), pages 15880 - 15899, XP055823887, DOI: 10.3390/s140915880 *
MOBIELDIN A N ET AL: "A dual-mode low-pass filter for 802.11b/bluetooth receiver", SOLID-STATE CIRCUITS CONFERENCE, 2004. ESSCIRC 2004. PROCEEDING OF THE 30TH EUROPEAN, IEEE, PISCATAWAY, NJ, USA, 21 September 2004 (2004-09-21), pages 423 - 426, XP010740130, ISBN: 978-0-7803-8480-4, DOI: 10.1109/ESSCIR.2004.1356708 *
PYLARINOS L ET AL: "Low-Voltage Programmable g<inf>m</inf>-C Filter for Hearing Aids using Dynamic Gate Biasing", CONFERENCE PROCEEDINGS / IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) : MAY 23 - 26, 2005, INTERNATIONAL CONFERENCE CENTER, KOBE, JAPAN, IEEE SERVICE CENTER, PISCATAWAY, NJ, 23 May 2005 (2005-05-23), pages 1984 - 1987, XP010815900, ISBN: 978-0-7803-8834-5, DOI: 10.1109/ISCAS.2005.1465004 *
YUNBIN DENG ET AL: "Three-decade programmable fully differential linear OTA", PROCEEDINGS / 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS : MAY 23 - 26, 2004, SHERATON VANCOUVER WALL CENTRE HOTEL, VANCOUVER, BRITISH COLUMBIA, CANADA, IEEE OPERATIONS CENTER, PISCATAWAY, NJ, 23 May 2004 (2004-05-23), pages I - 697, XP010719211, ISBN: 978-0-7803-8251-0 *

Also Published As

Publication number Publication date
US20190369168A1 (en) 2019-12-05
WO2018141806A1 (en) 2018-08-09
CN110249533A (zh) 2019-09-17
US11009563B2 (en) 2021-05-18
CN110249533B (zh) 2023-08-18
EP3355475A1 (de) 2018-08-01

Similar Documents

Publication Publication Date Title
EP3355475B1 (de) Signalverarbeitungsanordnung für einen hall-sensor und signalverarbeitungsverfahren für einen hall-sensor
US7235983B2 (en) One terminal capacitor interface circuit
US7405682B2 (en) Delta-sigma analog digital converter with offset compensation
EP3110007B1 (de) Rampenspannungsgenerator und verfahren zur prüfung eines analog-digital-wandlers
CN106716149B (zh) 霍尔电动势信号检测电路以及电流传感器
KR101832018B1 (ko) Ｄｃ 오프셋 보상
US20050190089A1 (en) Circuit arrangement for the delay adjustment of analog-to-digital converters operating in a temporally offset manner
US9897635B2 (en) Sensor circuit
US9685967B1 (en) Chopper stabilized sigma delta ADC
Dyer et al. Calibration and dynamic matching in data converters: Part 2: Time-interleaved analog-to-digital converters and background-calibration challenges
JP2023502420A (ja) スイッチトキャパシタ増幅器、及びそれを含むパイプライン型アナログ－デジタル変換器
WO2012091788A1 (en) Calibration of time constants in a continuous-time delta-sigma converter
US11500039B2 (en) Digitally-controlled output amplitude of analog sensor signal
WO2018059796A1 (en) Integration circuit and method for providing an output signal
US8432192B2 (en) 2-phase threshold detector based circuits
JP7135097B2 (ja) 電流積分器における増幅器の負荷電流キャンセル方法、及び、増幅器の負荷電流がキャンセルされた電流積分器
US9401725B2 (en) Suppressing offset, offset drift, and 1/f noise during analog/digital conversion
US11637554B2 (en) Device and method for enhancing voltage regulation performance
CN112986873B (zh) 用于霍尔传感器的信号处理电路以及信号处理方法
CN112015223B (zh) 用于半导体集成电路的基准电流源
CN111034034B (zh) 电路装置和操作电路装置的方法
US10317482B2 (en) Resistive sensor frontend system having a resistive sensor circuit with an offset voltage source
CN111034034A (zh) 电路装置和操作电路装置的方法

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN PUBLISHED

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: AMS AG

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20190201

RBV Designated contracting states (corrected)

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20200414

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

RIC1 Information provided on ipc code assigned before grant

Ipc: H03M 1/12 20060101ALN20211229BHEP

Ipc: G01R 33/00 20060101ALI20211229BHEP

Ipc: H03M 1/10 20060101AFI20211229BHEP

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

RIC1 Information provided on ipc code assigned before grant

Ipc: H03M 1/12 20060101ALN20220102BHEP

Ipc: G01R 33/00 20060101ALI20220102BHEP

Ipc: H03M 1/10 20060101AFI20220102BHEP

RIC1 Information provided on ipc code assigned before grant

Ipc: H03M 1/12 20060101ALN20220117BHEP

Ipc: G01R 33/00 20060101ALI20220117BHEP

Ipc: H03M 1/10 20060101AFI20220117BHEP

INTG Intention to grant announced

Effective date: 20220204

RIC1 Information provided on ipc code assigned before grant

Ipc: H03M 1/12 20060101ALN20220126BHEP

Ipc: G01R 33/00 20060101ALI20220126BHEP

Ipc: H03M 1/10 20060101AFI20220126BHEP

GRAJ Information related to disapproval of communication of intention to grant by the applicant or resumption of examination proceedings by the epo deleted

Free format text: ORIGINAL CODE: EPIDOSDIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

INTC Intention to grant announced (deleted)
GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RIC1 Information provided on ipc code assigned before grant

Ipc: H03M 1/12 20060101ALN20220608BHEP

Ipc: G01R 33/00 20060101ALI20220608BHEP

Ipc: H03M 1/10 20060101AFI20220608BHEP

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

INTG Intention to grant announced

Effective date: 20220711

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

Ref country code: AT

Ref legal event code: REF

Ref document number: 1517898

Country of ref document: AT

Kind code of ref document: T

Effective date: 20220915

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602017061416

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG9D

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20220907

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221207

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1517898

Country of ref document: AT

Kind code of ref document: T

Effective date: 20220907

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20221208

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230109

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230107

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602017061416

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

26N No opposition filed

Effective date: 20230608

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220907

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20230131

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230822

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230131

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20230131

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230131

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230131

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230131

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230131

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230131

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230131

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240119

Year of fee payment: 8