Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
  • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
  • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
  • H01L31/0687—Multiple junction or tandem solar cells
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/02—Details
  • H01L31/0224—Electrodes
  • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
  • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
  • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
  • H01L31/02245—Electrode arrangements specially adapted for back-contact solar cells for metallisation wrap-through [MWT] type solar cells
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
  • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
  • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
  • H01L31/0687—Multiple junction or tandem solar cells
  • H01L31/06875—Multiple junction or tandem solar cells inverted grown metamorphic [IMM] multiple junction solar cells, e.g. III-V compounds inverted metamorphic multi-junction cells
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/544—Solar cells from Group III-V materials
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• the present invention relates to a method of manufacturing structures for multi-junction cell and a structure obtained by this method.
• Concentrated photovoltaic (CPV) systems use multi-junction cells based on materials from columns III and V of the periodic table, typically InP and GaAs alloys vertically stacked by epitaxy. Each cell is optimized to convert a certain range of wavelength, the stack thus covering the entire solar spectrum. These cells can achieve much higher yields than conventional silicon solar cells, thanks to both the electro-optical properties of the III-V materials used and the use of an optical system to focus sunlight on cells. Thus, the best photovoltaic conversion yield published to date for CPV is 44.7%, while it is 25% on Si cells.
• a new generation of CPV cell has recently been proposed, which is based on the mechanical stacking of several layers of materials III-V, so as to form a vertical assembly of several junctions.
• mechanical stacking is meant the transfer of layers involving a molecular bonding step.
• Dimroth et al. in the document Prog. Photovolt: Res. Appli (2014) pip.2475 used the mechanical stacking of layers of semiconductor materials to form a new CPV cell architecture.
• the structure of the final device has not been modified: the authors use in particular a contact grid on the front panel which is a shading factor for the cell.
• solder bonding is known, it requires to spread SnPbAg or SnAgCu alloys on the surfaces to stick then to apply a controlled thermal treatment of the layers put in contact.
• areas without solder under the cell may appear due to poor spreading thereof an unsuitable implementation temperature profile.
• These gaps in the solder are called 'voids' and are a known failure mode.
• the voids (or unglued parts) can represent from 1 to 60% of the surface of the cell.
• These cavities can reach large dimensions, up to several millimeters, and are not compatible with the transfer of thin films less than 20 micrometers thick such as the active layers of the junctions. Thin films may deform or even break during bonding.
• document WO 2013/152104 discloses a multi-junction solar cell making it possible to reduce the shading effects on the front face by providing through contacts: a large part of the metallization on the front face is eliminated by means of metal vias which electrically connect the front face by the rear face of the cell.
• the contact grid can be reduced to simple points of collection punctual front, because they are connected on the back thanks to through vias.
• the carriers of the rear face are collected laterally by the doped layer and the contact is taken by a metal pad on a front face.
• this structure makes it possible to limit the shading of the front face for the collection of carriers of the front face, on the other hand there remains a shading area at the metal stud for the collection of carriers of the rear face.
• the document W0 2013/152104 also proposes to structure the rear face of the structure so as to be able to resume all the contacts on the rear face and limit the shading of the front face.
• this structuring is very complex to implement (additional photolithography steps, etching, deposit, ...) and represents a significant cost.
• the substrate which only serves to support the active layers is an expensive and fragile semiconductor material and it is necessary to stick it via a solder on a receiving substrate.
• the present invention proposes a method for manufacturing structures for a photovoltaic multi-junction cell comprising successively the steps of:
• a multi-junction structure for a photovoltaic cell comprising at least a first doped layer comprising a semiconductor material with a dopant concentration greater than 5 E 18 and delimiting a front face of the multi-junctions oriented towards the support substrate, the multi-junctions junctions, and a second doped layer comprising a semiconductor material with a dopant concentration greater than 5 E 18 and delimiting a rear face of the multijunctions, the rear face being opposite to the front face, and a rear metal layer s' extending on the second doped layer on the rear face of the multi-junctions,
• step i) forming metal studs directly above the vias and in the continuity of the metal layer before so as to partially cover the first doped layer on the front face of the multi-junctions, and j) Remove exposed portions of the first doped layer front face so as to form doped patterns covered by the metal pads formed in step i).
• the support substrate is removed from the final structure, which allows a significant saving of material, the support substrate having a thickness of about 400-700 micrometers for a multi-junction thickness of about 1 to 20 microns.
• the absence of the support substrate in the structure limits the bulk of the final cell. And depending on the removal method used, the support substrate can be recycled for further use.
• first conductive bonding layer and the second conductive bonding layer are not melted, that the conductive bonding is solder-free, and that the electrical connections are free of solder.
• the "exposed portions of the first doped layer on the front face" of step j) are free portions of the covering by the metal studs formed in step i).
• this bonding directly made on the receiving substrate, without the intermediary of the support substrate, and from the rear face of the multi-junctions, also allows the production of through metal vias, reducing the metallization in the front face and thus the shading the cell, deporting the contacts on the back, which also become easier to connect.
• the metal pads of the front metal layer allow conduction and collection carriers of the layer or pads of the front face to the first metal track rear face.
• the electrical insulation between the metal layer and the front metal layer also offers the possibility of deporting and collecting the rear carriers and the front carriers by the rear face.
• the resumptions of all the contacts are thus facilitated so that the choice of the receiving substrate is dictated only by its electrical, mechanical, thermal or its cost. All this is impossible to obtain when the rear face of the multi-junctions rests on the support substrate soldered to the receiving substrate.
• the multi-junctions for a cell comprise a stack of a number of junctions, or active layers, greater than one and preferably between two and six.
• multi-junctions is meant in this document active layers in III-V material and also the tunnel diodes between the junctions, a back surface field, buffer layers, a front surface passivation, a first doped layer and a second doped layer, etc.
• the multi-junctions result from the epitaxy of active layers in III-V material on the support substrate.
• the multi-junctions are mechanical stacks of several junctions of III-V materials, some of which are obtained by the technique of mechanical transfer or transfer of layers using a molecular bonding bonding.
• the junctions concerned will have been previously epitaxied on a seed substrate.
• the 'front metal layer' and the 'rear metal layer' are intended to form an ohmic contact in association with the first doped layer and the second doped layer, respectively, to collect the carriers of the front face of the multi -junctions and a contact layer to collect the carriers of the rear face of multi-junctions.
• the rear metal layer and the front metal layer are electrically conductive. They are in particular formed of a metal commonly used in the field of CPV cells and preferably they consist of Cu, Au, Ag, Ti, Pt, Ni, Pd, Ge, etc. alone or in combination.
• the first doped layer and the second doped layer may be p-type or n-type and are composed of doped semiconductor materials, such as In, P, Ga, As alloys comprising a concentration of dopants preferably between 5 E 18 and 5 E 19, the doping species can be Si, S, Zn, Sn, Te, ... depending on the alloy and the type of doping n or p desired.
• doped semiconductor materials such as In, P, Ga, As alloys comprising a concentration of dopants preferably between 5 E 18 and 5 E 19, the doping species can be Si, S, Zn, Sn, Te, ... depending on the alloy and the type of doping n or p desired.
• each via may take the form of, for example, an opening or a trench extending at least in the rear metal layer and in the active layers, in the first doped layer, or even partially in the support substrate until at a depth ranging from a few nanometers to several, even tens of micrometers, or hundreds of micrometers.
• the step b) of etching the plurality of vias comprises a photolithography step followed by a chemical etching and / or ion etching step (Ion Beam Etching) and / or by RIE (Reactive Ion Etching) plasma, especially in ICP (Inductively Coupled Plasma) mode.
• the section of the plurality of vias may be square, round or hexagonal, linear or in the form of a grid.
• the geometry of the section is adapted according to the operation of the cell, the type of junctions, the use in CPV.
• the lateral dimension of their section is of the order of a hundred nanometers up to several micrometers, even a few hundred micrometers.
• step c) of forming the electrically insulating layer is carried out by depositing at least one layer of an insulating material such as Si0 2 and / or SiN with a thickness of a few hundred nanometers. at several micrometers.
• the deposit is made according to the topology of the structured surface, so as to cover the flanks of the vias, their bottom, as well as a part of the surface of the rear metal layer.
• step d) of forming the front metal layer is carried out by depositing on the electrically insulating layer and so as to cover the flanks of the vias.
• the electrically insulating layer electrically isolates the metal layer before multi-junctions and the rear metal layer.
• the deposition of the front metal layer comprises the metallization filling all the vias, so ensure the vias good mechanical rigidity.
• the receiving substrate provided in step e) is formed of an electrically insulating material, such as alumina, a glass or a polymer, and has a thickness of between about 100 micrometers and a few millimeters. Its thickness is related to its mechanical properties to enable the transfer and ensure the mechanical strength of multi-junctions and heat treatments. It is also chosen to be inexpensive.
• the first metal track and the second metal track are glued or deposited on a surface of the receiving substrate intended to receive the multi-junctions.
• the first metal track and the second metal track are metal selected from Au, Cu, Ag, Ti, Pt or a combination of these metals.
• the electrical connections of step f) are obtained by conductive bonding of the surfaces to be connected to the front metal layer and the first metal track, the conductive bonding comprising at least the deposition of a first conductive bonding layer on at least one of the surfaces to be connected, followed by contacting said surfaces to be connected and the application of a heat treatment.
• the heat treatment is performed without reaching the melting, even partial, of the first conductive bonding layer.
• the electrical connections of step g) are obtained by conductive bonding of the surfaces to be connected of the exposed portion of the rear metal layer and the second metal track, the conductive bonding comprising at least the deposition of a second conductive bonding layer on at least one of the surfaces to be connected, followed by contacting said surfaces and the application of a heat treatment The heat treatment is performed without reaching the melting, even partial, of the first conductive bonding layer.
• step f) and the electrical connections of step g) are free of solder.
• the first conductive bonding layer and the second conductive bonding layer are formed of a conductive material selected from Cu, Au, their combination, or conductive polymers, such as charged epoxy resins, for example Ag.
• the first conductive bonding layer and the second conductive bonding layer consist of a conductive polymer and deposited respectively on one of the surfaces to be connected with a thickness greater than 2 microns and in which the heat treatment is carried out in a temperature range between 100 and 400 ° C.
• the use of a conductive polymer is advantageous in that the polymer is easy to deposit and remains inexpensive.
• the first conductive bonding layer and the second conductive bonding layer are made of copper and deposited with a thickness greater than 2 microns on the surfaces to be connected.
• the conductive Cu bonding layers are then polished by chemical mechanical polishing so as to obtain a surface roughness of less than 0.3 nm RMS. They are then bonded by molecular adhesion and the bonding consolidation heat treatment is carried out in a temperature range between 200 and 400 ° C.
• Copper conductive bonding layers are typically deposited by ECD (Electro Chemical Deposition) over a substantial thickness, about 5 micrometers, so that it is not necessary to planarize the underlying metal tracks. before deposit.
• the topology of the underlying surface is homogenized by the consequent thickness of the deposit.
• the surfaces of the first conductive bonding layer and the second conductive bonding layer are then planarized by CMP (chemical English acronym Chemical Mecanichal Polishing) until a roughness of the order of one nanometer and then cleaned to favor obtaining a good bonding energy.
• CMP chemical English acronym Chemical Mecanichal Polishing
• the first conductive bonding layer and the second conductive bonding layer consist of copper and deposited on the surfaces to be connected with a thickness of less than 2 micrometers and in which the heat treatment is carried out by a rise in temperature from room temperature to about 300 ° C, associated with the application of pressure up to about 30kN.
• the layers of copper conductive bonding are thinner so as to reduce the costs of materials used, the surfaces of the metal tracks are planarized by CMP before deposition and it is necessary to apply pressure on the formed assembly. the stack and the receiving substrate contacted to achieve high bonding energy.
• the first conductive bonding layer and the second conductive bonding layer are made of Au and deposited on the surfaces to be bonded with a thickness of less than 1 micrometer and in which the heat treatment is carried out by a rise in temperature from the ambient temperature at about 300 ° C, associated with the application of pressure up to about 30kN.
• the conductive bonding layers are very expensive because formed of gold, the layers are very thin and the same planarization steps before deposition and application of pressure are performed.
• step c) is carried out by a step c1) of deposition of an electrically insulating layer on the entire rear metal layer, the flanks of the vias and a step c2) of localized removal of the electrically insulating layer of so as to expose a portion of the rear metal layer, and wherein step d) is carried out by a step d1) depositing a front metal layer on the entire electrically insulating layer, and a step d2) withdrawal located of the front metal layer to expose a portion of the electrically insulating layer.
• step c2) and step d2) are carried out by photolithography, such as a deposit of a resin removed after etching, or by selective etching in a dilute HF bath.
• the two removal steps c2) and d2) can be performed concomitantly.
• the exposed portion of the rear metal layer has surface dimensions to be connected ranging from a few hundred micrometers to one centimeter and preferably dimensions of the order of a few millimeters.
• the surface to be connected to the front metal layer has dimensions ranging from a few hundred microns to one centimeter and preferably dimensions of the order of a few millimeters or even a few centimeters.
• the exposed portion of the electrically insulating layer has similar dimensions. According to the integration requirements, the exposed portion of the electrically insulating layer is zero.
• the first metal track and the second metal track are electrically isolated by a first insulation track defined on the receiving substrate and in which the first conductive bonding layer and the second conductive bonding layer are electrically isolated by a second Isolation track defined on the stack.
• the first insulating track and the second insulating track are formed by a deposit of an insulating material, such as silicon oxide, an insulating epoxy resin, a BCB-type polymer (acronym for BenzoCycloButene), or by temporary masking, respectively.
• an insulating material such as silicon oxide, an insulating epoxy resin, a BCB-type polymer (acronym for BenzoCycloButene), or by temporary masking, respectively.
• a surface of the receiving substrate and a surface of the stack for example made by a rigid frame which is removed after the formation for example of the first metal track 6 and the second metal track 6 '.
• the insulating tracks on either side of the surfaces to be connected are aligned during contacting so that they provide a mark for the alignment of the receiving substrate and the multi-junctions, promoting the quality of the electrical connections. .
• the first insulating track and the second insulating track can be removed depending on future applications. According to one possibility, they are advantageously replaced by vacuum.
• the stack comprises an etching stop layer disposed between the support substrate and the multi-junctions and the step of removing the support substrate comprises a step of breaking-in of the support substrate and the layer. etching stop or selective etching step of the support substrate so as to remove a portion at the bottom of the vias of the electrically insulating layer and expose the front metal layer.
• the etching of the plurality of vias in the stack is stopped by the etch stop layer.
• the support substrate is GaAs and the junctions are formed of alloys of III-V materials such as GaAs, and GalnP, by epitaxy on the support substrate.
• the support substrate is a demountable composite substrate comprising a sacrificial layer disposed between a seed layer and a mechanical substrate, such as a demountable composite substrate comprising a GaAs seed layer carried on a sapphire substrate, between which a sacrificial layer of SiNx is provided, and step h) comprises the removal of the mechanical substrate by irradiation at the absorption wavelength of the sacrificial layer through the transparent mechanical substrate at said wavelength.
• the irradiation is performed by laser in the case of a sacrificial layer of SiNx, the wavelength used is 273 nm to which the mechanical sapphire substrate is transparent.
• the epitaxial junctions on the seed layer chosen for its crystalline quality and its adapted mesh parameter, it is possible to disassemble the mechanical substrate without destroying it for recycling.
• the present invention proposes a multi-junction photovoltaic cell structure comprising:
• Multi-junctions for a photovoltaic cell comprising a first doped layer, formed by doped patterns, delimiting a front face of the multi-junctions, and a second doped layer delimiting a rear face of the multi-junctions, the rear face being opposite to the face before, and
• a receiver substrate on which are disposed a first metal track and a second electrically insulated metal track of the first metal track
• the front metal layer being electrically connected to the first metal track via a first conductive bonding layer
• the exposed portion of the rear metal layer being electrically connected to the second metal track via a second conductive bonding layer, electrically insulated from the first conductive bonding layer.
• the electrical connection between the front metal layer and the first metal track is free of solder, and the electrical connection between the exposed portion of the rear metal layer and the second metal track is also free of solder.
• the electrically insulating layer is configured to isolate the front metal layer of the rear metal layer, making it possible to postpone all the contacts on the rear face of the multi-junctions.
• the front panel is thus less prone to shadowing effects.
• the first conductive bonding layer and the second conductive bonding layer are not melted so that the conductive bonding without brazing between the receiving substrate and the multi-junctions ensures good bonding without damaging the thin layers forming the multi-junctions.
• the first metal track and the second metal track are isolated by a first insulation track defined on the receiving substrate and the first conductive bonding layer is isolated from the second conductive bonding layer by a second defined insulation track on the multijunctions and aligned to the first isolation track.
• the front metal layer is connected to the first metal track being isolated by the multi-junction layer and the rear metal layer itself connected to the second metal track, and the carriers of the front and rear faces are collected by two Isolated independent contacts but both deported to the back.
• the first conductive bonding layer and the second conductive bonding layer are formed of a metal, such as copper or gold, or a conductive polymer such as an epoxy resin loaded with metal elements.
• the conductive bonding makes it possible to use a technique other than brazing and a very good electrical connection between the electrical contacts and the metal tracks of the receiving substrate.
• the present invention provides an alternative to soldering the multi-junctions on a receiving substrate to form a photovoltaic cell, while allowing to recycle the support substrate and to postpone the collection of carriers of the front face and the rear face on the back of multijunctions, limiting the shading effect.
• FIG. 1 to 8 show structures at different process steps according to a first embodiment of the invention.
• FIGS. 9 and 10 are sectional views of a structure obtained at different stages of the method according to a second embodiment of the invention.
• FIG. 1 (step a) illustrates a stack comprising a support substrate 1 of GaAs with a diameter of 100 mm on which epitaxial layers of materials III-V are formed so as to form multi-junctions 2 for photovoltaic cells comprising two junctions, for example GalnP and GaAs.
• the multi-junctions 2 also include tunnel diodes between the junctions, a rear surface field, buffer layers, a front surface passivation, an ohmic contact layer ... but the complete stack representing several tens of layers, only the important layers for the invention are shown in the figures.
• the multi-junctions 2 comprise in particular a second doped layer 3 delimiting a rear face of the multi-junctions 2 on which a rear metal layer 4 extends.
• the second doped layer 3 is made of a highly doped semiconductor material so as to provide the conduction with the rear metal layer 4 made of a metal.
• the multijunctions 2 also comprise a first doped layer 7 of highly doped semiconductor material delimiting the front face of the multi-junctions 2, oriented towards the support substrate 1 (on the opposite side to the second doped layer 3).
• the typical thickness of such a stack is of the order of a few micrometers.
• an etch stop layer 10 is interposed between the support substrate 1 and the first doped layer 7, so as to facilitate the subsequent removal of the support substrate 1.
• a plurality of vias is etched in the stack through the rear metal layer 4 and extends to the first doped layer 7.
• This etching is performed in particular by a conventional step of photolithography followed by a chemical etching.
• the etching is carried out by ion etching (Ion Beam Etching) and / or plasma (Reactive Ion Etching), especially in 'Inductively Coupled Plasma' mode.
• the engraving of the vias is stopped by the etch stop layer 10 located between the first doped layer 7 and above the GaAs support substrate 1 as illustrated.
• the geometry of the vias is adapted according to the functioning of the cell (type of junctions, concentration).
• an electrically insulating layer 9 is deposited on the entire surface of the stack, in accordance with the topology of the structured surface; on the flanks and the bottom of the plurality of vias (step c).
• the electrically insulating layer 9 typically consists of Si0 2 or SiN (or both), and has a thickness ranging from a few hundred nanometers to several micrometers.
• a metal metal front layer 8 is deposited on the electrically insulating layer 9, so as to cover the flanks of the vias, their bottom, as well as the surface of the rear face of the multi-junctions 2 (step dl). It is preferable that this deposit or metallization completely fills the vias so as to ensure good mechanical rigidity.
• a localized removal step of the electrically insulating layer 9 and a localized step of removing the metal layer before 8 to expose a portion of the electrically insulating layer 9 are undertaken (step c2 and d2).
• These local withdrawals can be performed simultaneously using conventional photolithography techniques (especially the deposit of a resin and lift-off). According to another arrangement, it is also possible to use a local chemical etching technique in a dilute HF dip bath.
• the exposed portion of the rear metal layer 4 in order to form the electrical contacts of the rear face, has a size of the order of a few hundred micrometers to a few millimeters or even a few centimeters.
• the exposed portion of the electrically insulating layer 9 is of the same order of magnitude as the residual portion of the front metal layer 8. According to a non-illustrated alternative, this exposed portion of the electrically insulating layer 9 may be zero for integration purposes .
• a receiving substrate 200 for multi-junctions 2 of insulating material comprises on its surface intended for bonding with the multijunctions 2, a first metal track 6 and a second metal track 6 ', made of copper for example, intended to be electrically connected respectively with the front metal layer 8 and the exposed portion of the rear metal layer 4.
• the two metal tracks 6, 6 ' are electrically insulated by a first insulation track 11 (FIG. 4) deposited in an insulating material and easy to remove. remove such as Scotch, a Kapton (R) type polymer or wax.
• a first conductive bonding layer 5 is deposited on two surfaces to be electrically connected, namely the first metal track 6 and the front metal layer 8.
• the first copper metal strip 6 is planarized by CMP until reaching a roughness of the order of one nanometer RMS (acronym for Root Mean Square).
• the first gold conductive bonding layer 5 is deposited by PECVD (acronym for Plasma Enhanced Chemical Vapor Deposition) with a thickness of 200 nm on both surfaces to be connected (step f).
• the same planarization step on the second metal track 6 ' is performed as well as the deposition of a second conductive bonding layer 5' of gold on the surfaces to be connected, namely on the exposed portion of the metal layer rear 4 and on the second metal track 6 '.
• the first conductive bonding layer 5 and the second conductive bonding layer 5 ' are electrically insulated by a separation provided by a second insulation track 11' deposited in the same way as the first insulation track 11.
• the surfaces of the first conductive bonding layers 5 and the second conductive bonding layers 5 ' are aligned by virtue of the alignment of the insulation tracks (FIG. 7) and are then brought into contact before the application of a thermal treatment in the form of a temperature ramp from room temperature to approximately 300 ° C., associated with the application of a pressure of about 30kN.
• the solderless electrical connection between the front metal layer 8 and the first metal track 6 is then obtained (step f) as well as the electrical connection between the rear metal layer 4 and the second metal track 6 '(step g).
• the bonding energy achieved by these steps is then sufficient to effect the removal of the support substrate 1.
• the GaAs support substrate 1 and the etch stop layer 10 are then eliminated by lapping and / or by selective chemical etching (step h).
• the portions of the electrically insulating layer 9 directly above the vias are removed by chemical etching or by dry etching, and metal studs 12 directly above the vias are deposited by photolithography in the continuity of the vias.
• front metal layer 8 with a dimension slightly greater than that of the vias section (typically from a few hundred nm to a few ⁇ ) so as to partially cover the first doped layer 7 underlying (step i).
• a chemical etching or ionic or plasma makes it possible to eliminate exposed portions of the first doped layer 7 (portions not covered by the metal studs 12) in order to form doped patterns allowing the collection of the carriers of the front face and their transmission.
• the carriers of the rear face are collected by the second metal track 6 'via the second conductive bonding layer 5' electrically connected to the rear metal layer 4 (to right on the structure 100 of Figure 8).
• a second embodiment illustrated in FIGS. 9 and 10 differs from the first embodiment described above, in particular in that the support substrate 1 of the stack is a removable composite substrate and in that the first and second tracks insulation 11, 11 'are formed by a temporary mask.
• the multi-junctions 2 are formed on a composite support substrate comprising a sapphire mechanical substrate 13 and a seed layer 14 for epitaxial junctions, for example GaAs, between which a sacrificial layer 15 of SiNx is arranged.
• the materials of the mechanical substrate 13 and the sacrificial layer 15 are chosen so that the sacrificial layer 15 absorbs a wavelength, here 273 nm, at which the mechanical substrate 13 is transparent.
• a receiving substrate 200 is then provided for conductive bonding with the multi-junctions 2. It comprises a first metal track 6 and a second metal track 6 'electrically insulated by the provision of a rigid frame 11 on the surfaces temporarily.
• the thickness of this layer avoids the step of planarization of the metal tracks 6,6 'on the receiving substrate 200 beforehand.
• planarization of the conductive bonding layers 5, 5 ', followed by a cleaning step are necessary before contacting.
• a second temporary insulation track 11 'intended to isolate the conductive bonding layers 5, 5', such as a mask, has been arranged beforehand.
• the contacting is carried out under vacuum, so as to limit the aging of the tracks by oxidation of Cu, it is followed by the application of a heat treatment carried out at 200 ° C for about 1 hour (FIG. does not cause the copper to melt so as to avoid any solder.
• step h) of the removal of the support substrate 1 is carried out by the technique commonly known as laser lift off comprising the laser irradiation of the sacrificial layer 15 through the mechanical substrate 13 transparent to the wavelength used.
• the mechanical sapphire substrate 13 can thus be recycled.
• the deposition of the metal pads 12 and the formation of the doped units are then carried out according to the same method as that previously described.
• the conductive bonding layers 5, 5 ' are formed by depositing, on only one of the surfaces to be connected, a conductive polymer, then after contacting, the bonding is annealed by a treatment thermal applied between 100 and 400 ° C.
• the conductive bonding layers 5, 5 ' are formed by the deposition on the surfaces to be connected of a copper thin layer, less than 2 microns, for example, after planarization of metal tracks 6,6 '.
• the contacting of the surfaces to be connected is followed by a heat treatment in the form of a temperature ramp from room temperature to about 300 ° C, associated with the application of a pressure at about 30kN.
• the present invention proposes a process for manufacturing structures 100 for multi-junction photovoltaic cells 2 by an improved conductive bonding compared to solder bonding to prevent damage to the transferred active layers.
• this method makes it possible to remove the bulky initial support substrate 1 and to limit the shading on the front face of the cell by collecting the carriers of the front face and of the rear face on the rear face of the multi-junctions 2.

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• 2015
  • 2015-09-23 FR FR1558975A patent/FR3041475B1/fr not_active Expired - Fee Related
• 2016
  • 2016-09-23 EP EP16770757.9A patent/EP3353815A1/de not_active Withdrawn
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