Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
  • G06N3/00—Computing arrangements based on biological models
  • G06N3/02—Neural networks
  • G06N3/04—Architecture, e.g. interconnection topology
  • G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
  • G06F17/10—Complex mathematical operations
  • G06F17/11—Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
  • G06F17/13—Differential equations
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
  • G06N3/00—Computing arrangements based on biological models
  • G06N3/02—Neural networks
  • G06N3/04—Architecture, e.g. interconnection topology
  • G06N3/048—Activation functions

Definitions

• the present invention relates to data processing techniques.
• Embodiments implement a new way of performing calculations in machines, particularly in programmable machines.
• Neurogrid (Ben V. Benjamin, et al .: “Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations", Proceedings of the IEEE, Vol.102, No. 5, pages 699-716, May 2014) ;
• a data processing device comprising a set of processing nodes and connections between the nodes.
• Each connection has a transmitting node and a receiving node among the set of processing nodes and is configured to transmit events delivered by the transmitting node to the receiving node.
• Each node is arranged to vary a respective potential value according to events it receives and to deliver an event when the potential value reaches a predefined threshold.
• At least one input quantity of the data processing device is represented by a time interval between two events received by at least one node, and at least one output quantity of the data processing device is represented by a time interval between two events delivered by at least one node.
• the processing nodes constitute neuron-type calculation units. However, we are not particularly interested here in imitating the functioning of the brain.
• the term "neuron” is used in the memory for convenience of language, but does not necessarily signify a strong resemblance to the mode of functioning of the neurons of the cortex.
• each processing node is arranged to reset its potential value when it issues an event.
• the reset may especially be at a zero potential value.
• Many embodiments of the data processing device include, among the connections between the nodes, one or more potential variation connections each having a respective weight.
• the receiving node of such a connection is arranged to react to an event received on this connection by adding the weight of the connection to its potential value.
• Potential variation connections may include connections excitatory, positive weight, and inhibitory connections, negative weight.
• the set of processing nodes may comprise at least a first node forming the receiving node of a first potential variation connection having a positive first weight at least equal to the predefined threshold. for the potential value, and at least one second node forming the receiving node of a second weight potential variation connection at least equal to half of the predefined threshold for the potential value and less than the predefined threshold for the value of the potential value. potential.
• the aforementioned first node further forms the transmitting node and the receiving node of a third weight potential variation connection equal to the opposite of the first weight, as well as the transmitting node of a fourth connection, while the second node further forms the transmitting node of a fifth connection.
• the first and second potential variation connections are then configured to receive each two events separated by a first time interval representing an input quantity so that the fourth and fifth connections carry respective events having a second time interval between them. in relation to the first time interval.
• an example of a data processing device comprises at least one minimum calculation circuit, which comprises itself:
• first, second, third, fourth, fifth and sixth potential variation connections each having a first positive weight at least equal to half of the predefined threshold for the potential value and less than the predefined threshold for the potential value;
• the first input node forms the transmitting node of the first and third connections and the receiving node of the tenth connection
• the second input node forms the transmitting node of the second and fourth connections.
• the receiving node of the ninth connection the first selection node forms the transmitting node of the fifth, seventh and ninth connections and the receiving node of the first and eighth connections
• the second selection node forms the transmitting node of the sixth, eighth and tenth connections and the receiving node of the second and seventh connections
• the output node forms the receiving node of the third, fourth, fifth and sixth connections.
• Another example of a data processing device comprises at least one maximum calculation circuit, which itself comprises:
• first, second, third and fourth potential variation connections each having a first positive weight at least equal to half of the predefined threshold for the potential value and less than the predefined threshold for the potential value;
• the first input node forms the transmitting node of the first and third connections
• the second input node forms the transmitting node of the second and fourth connections
• the first selection node forms the sending node of the fifth connection and the receiving node of the first and sixth connections
• the second selection node forms the sending node of the sixth connection and the receiving node of the second and fifth connections
• the output node forms the receiving node of the third and fourth connections.
• Another example of a data processing device comprises at least one subtracter circuit, which comprises itself:
• first and second output nodes each having a first positive weight at least equal to the predefined threshold for the potential value;
• the first synchronization node forms the transmitting node of the first, second, third and ninth connections
• the second synchronization node forms the transmitting node of the fourth, fifth, sixth and tenth connections, the first node of the first node.
• Inhibition forms the sending node of the eleventh connection and the receiving node of the third, eighth and tenth connections
• the second muting node forms the transmitting node of the twelfth connection and the receiving node of the sixth, seventh and ninth connections
• the first The output node forms the sending node of the seventh connection and the receiving node of the first, fifth, and eleventh connections
• the second output node forms the transmitting node of the eighth connection and the receiving node of the second, fourth, and twelfth connections.
• the first synchronization node is configured to receive, on at least one potential variation connection having the second weight, a first pair of events having between them a first time interval representing a first operand.
• the second synchronization node is configured to receive, on at least one potential variation connection having the second weight, a second pair of events having between them a second time interval representing a second operand, so that a third pair of events having between them a third time interval is delivered by the first output node if the first time interval is longer than the second time interval and by the second output node if the first time interval is shorter the second time interval, the third time interval representing the absolute value of the difference between the first and second operands.
• the subtracter circuit may further comprise a zero detection logic including at least one detection node associated with detection connections and with the first and second synchronization nodes, one of the first and second inhibition nodes and one of the first and second output nodes. Detection and muting connections are faster than the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth connections, to inhibit the production of events by any of the first and second output nodes when the first and second time intervals are substantially equal.
• the set of processing nodes comprises at least one node arranged to vary a current value as a function of events received on at least one current setting connection, and to varying its potential value over time with a rate of change proportional to said current value
• a processing node may in particular be arranged to reset its current value when it delivers an event.
• the current value in at least some of the nodes has a constant component between two events received on at least one constant current component setting connection having a respective weight.
• the receiving node of a constant current component tuning connection is arranged to respond to an event received on that connection by adding the weight of the connection to the constant component of its current value.
• Another example of a data processing device comprises at least one inverting memory circuit, which comprises itself:
• first, second and third current constant component control connections having the same positive weight and the second connection having a weight opposite the weight of the first and third connections;
• the accumulator node forms the receiving node of the first, second and third connections and the sending node of the fourth connection, and the first and second connections are configured to respectively address the accumulator node of the first and second connections.
• second event having between them a first time interval in relation to a time interval representing a quantity to be stored, so that the accumulator node then reacts to a third an event received on the third connection by increasing its potential value until delivery of a fourth event on the fourth connection, the third and fourth events having between them a second time slot in relation to the first time slot.
• Another example of a data processing device comprises at least one memory circuit, which itself comprises:
• first, second, third and fourth current constant component control connections each having a first positive weight and the third connection having a second weight opposite the first weight
• the first storage node forms the receiving node of the first connection and the transmitting node of the third connection
• the second storage node forms the receiving node of the second, third and fourth and fifth connections and the transmitting node.
• the first and second connections are configured to respectively address to the first and second accumulator nodes first and second events having between them a first time interval in relation to a time interval representing a quantity to be stored, so that the second storage node then responds to a third event received on the fourth connection by increasing its potential value until delivery of a fourth event on the fifth connection, the third and fourth events having a second time slot between them; relationship with the first interval of t ime.
• the memory circuit may further comprise a sixth connection having the first storage node as the transmitting node, the sixth connection providing an event to signal read availability of the memory circuit.
• a data processing device comprises at least one synchronization circuit, which includes a number N> 1 of memory circuits, of the type just mentioned, and a synchronization node.
• the synchronization node is sensitive to each event delivered on the sixth connection of one of the N circuits of memory via a respective potential variation connection of weight equal to the first weight divided by N.
• the synchronization node is arranged to cause simultaneous reception of the third events via the fourth respective connections of the N memory circuits.
• Another example of a data processing device comprises at least one accumulation circuit, which itself comprises:
• N entries each having a respective weighting coefficient, N being an integer greater than 1;
• the accumulator node forms the receiving node of the first, second and third connections
• the synchronization node forms the transmitting node of the third connection
• the first and second connections are configured to respectively address to the accumulator node first and second events having between them a first time slot representing a respective operand provided on said input.
• the synchronization node is configured to deliver a third event once the first and second events have addressed for each of the N inputs, so that the accumulator node increases its potential value until a fourth event is delivered
• the third and fourth events have between them a second time interval in relation to a time interval representing a weighted sum of the operands provided on the N inputs.
• the Cumulative circuitry is part of a weighted summation circuit further comprising:
• the accumulator circuit synchronization node forms the transmitting node of the fourth connection
• the accumulator circuit accumulator node forms the transmitting node of the fifth connection
• the second accumulator node forms the node. receiver of the fourth connection and the transmitting node of the sixth connection.
• the accumulator circuit accumulator node increases its potential value until the fourth event is delivered on the fifth connection
• the second storage node increases its potential value.
• the fourth and fifth events having between them a third time interval in relation to a time interval representing a weighted sum of the operands provided on the N entries of the accumulation circuit.
• a data processing device comprises at least one linear combination circuit including two accumulation circuits, which share their synchronization node, and a subtractor circuit configured to react to the third event delivered by the shared synchronization node. and the fourth events respectively delivered by the accumulator nodes of the two accumulation circuits by delivering a pair of events having between them a third time interval representative of the difference between the weighted sum for one of the two accumulation circuits and the sum weighted for the other of the two accumulation circuits.
• the set of processing nodes comprises at least one node whose current value has an exponential decay component between two events received on at least one current component setting connection. with exponential decay having a respective weight.
• the receiving node of an exponential decay current component tuning connection is arranged to respond to an event received on that connection by adding the weight of the connection to the exponentially decreasing component of its current value.
• Another example of a data processing device comprises at least one log computation circuit, which itself comprises:
• first and second constant current component control connections the first connection having a positive weight
• second connection having a weight opposite to the weight of the first connection
• the accumulator node forms the receiving node of the first, second and third connections and the transmitting node of the fourth connection.
• the first and second connections are configured to address to the accumulator node first and second respective events having between them a first time slot in relation to a time interval representing an input quantity of the log computation circuit.
• the third connection is configured to address to the accumulator node a third event simultaneous or subsequent to the second event, so that the accumulator node increases its potential value until a fourth event is delivered on the fourth, third, and fourth connection. events having between them a second time interval in relation to a time interval representing a logarithm of the input quantity.
• At least one deactivation connection whose receiving node is a node capable of canceling its exponential decay current component in response to an event received on the deactivation connection.
• Another example of a data processing device comprises at least one exponential calculating circuit, which itself comprises:
• the accumulator node forms the receiving node of the first, second and third connections and the transmitting node of the fourth connection.
• the first and second connections are configured to address to the accumulator node first and second respective events having between them a first time interval in relation to a time interval representing an input quantity of the exponential calculating circuit.
• the third connection is configured to address to the accumulator node a third event simultaneous or subsequent to the second event, so that the accumulator node increases its potential value until a fourth event is delivered on the fourth, third, and fourth connection. events having between them a second time interval in relation to a time interval representing an exponential of the input quantity.
• Another example of a data processing device comprises at least one multiplier circuit, which itself comprises:
• first, second, third, fourth and fifth current constant component control connections the first, third and fifth connections having a positive weight, and the second and fourth connections having a weight opposite to the weight of the first, second and fifth connections.
• the first storage node forms the receiving node of the first, second and sixth connections and the sending node of the seventh connection
• the second storage node forms the receiving node of the third, fourth and seventh connections and the node.
• Transmitting the fifth and ninth connections the third storage node forms the receiving node of the fifth, eighth and ninth connections and the sending node of the tenth connection
• the synchronization node forms the sending node of the sixth and eighth connections.
• the first and second Connections are configured to address to the first accumulator node respective first and second events having between them a first time interval in relation to a time interval representing a first operand of the multiplier circuit.
• the third and fourth connections are configured to address to the second storage node respective third and fourth events having between them a second time slot in relation to a time slot representing a second operand of the multiplier circuit.
• the synchronization node is configured to deliver a fifth event on the sixth and eighth connections once the first, second, third, and fourth events have been received.
• the first storage node increases its potential value until a sixth event is delivered on the seventh connection and then, in response to the sixth event, the second storage node increases its potential value until delivery is completed. a seventh event on the fifth and ninth connections.
• the third accumulator node increases its potential value until an eighth event is delivered on the tenth connection, with the seventh and eighth events having a third time interval in relation to an interval of time between them. time representing the product of the first and second operands.
• Sign detection logic may be associated with the multiplier circuit for detecting the respective signs of the first and second operands and cause two events to be delivered having between them the time interval representing the product of the first and second operands on one of the first and second operands. either of two outputs of the multiplier circuit according to the detected signs.
• each connection is associated with a delay parameter, to signal to the receiving node of this connection to perform a change of state with, compared to the reception of an event on the connection, a delay indicated by said parameter.
• the quantities represented by time intervals have, for example, absolute values x ranging between 0 and 1.
• a logarithmic rather than a linear scale of At as a function of x can also suitable for certain applications.
• Other scales can be used.
• the processing device may have special arrangements for manipulating signed quantities. He can thus understand, for an input quantity:
• a first input having a node or two nodes among the set of processing nodes, the first input being arranged to receive two events having between them a time interval representing a positive value of the input quantity;
• a second input having a node or two nodes among the set of processing nodes, the second input being arranged to receive two events having between them a time interval representing a negative value of the input quantity.
• the processing device may comprise:
• a first output having a node or two nodes among the set of processing nodes, the first output being arranged to output two events having between them a time interval representing a positive value of said output quantity; and a second output having a node or two nodes among the set of processing nodes, the second output being arranged to output two events having between them a time interval representing a negative value of said output quantity.
• the set of processing nodes is in the form of at least one programmable network, the nodes of the network having a common behavior model as a function of the received events.
• This device further comprises programming logic for setting weights and delay parameters of the connections between the nodes of the network according to a calculation program, and a control unit for providing input quantities to the network and recovering output quantities calculated in accordance with the program.
• FIG. 1 is a diagram of a processing circuit producing the representation of a constant value on demand, according to one embodiment of the invention
• FIG. 2 is a diagram of an inverting memory device according to one embodiment of the invention
• Fig. 3 is a diagram showing the time course of potential values and the generation of events in an inverter memory device according to Fig. 2;
• Figure 4 is a diagram of a memory device according to one embodiment of the invention.
• Fig. 5 is a diagram showing the time course of potential values and the generation of events in a memory device according to Fig. 4;
• Figure 6 is a diagram of a signed memory device according to an embodiment of the invention.
• FIGS. 7 (a) and 7 (b) are diagrams showing the evolution in time of potential values and the production of events in a signed memory device according to FIG. 6 when it is presented with different values of 'Entrance ;
• Figure 8 is a diagram of a synchronization device according to one embodiment of the invention.
• Fig. 9 is a diagram showing the time course of potential values and the generation of events in a timing device according to Fig. 8;
• Fig. 10 is a diagram of a synchronization device according to another embodiment of the invention.
• Figure 11 is a diagram of a minimum computing device according to one embodiment of the invention.
• Fig. 12 is a diagram showing the time course of potential values and the generation of events in a minimum computing device according to Fig. 11;
• Figure 13 is a diagram of a maximum computing device according to one embodiment of the invention.
• Fig. 14 is a diagram showing the time course of potential values and the generation of events in a maximum computing device according to Fig. 13;
• Fig. 15 is a diagram of a subtractor device according to one embodiment of the invention.
• Fig. 16 is a diagram showing the time course of potential values and the generation of events in a subtractor device according to Fig. 15;
• Fig. 17 is a diagram of a variant of the subtractor device in which a difference equal to zero is taken into account
• Fig. 18 is a diagram of an accumulation circuit according to an embodiment of the invention.
• Fig. 19 is a diagram of a weighted summation device according to an embodiment of the invention.
• Fig. 20 is a diagram of a linear combination calculating device according to an embodiment of the invention.
• Fig. 21 is a diagram of a log computing device according to one embodiment of the invention.
• Fig. 22 is a diagram showing the time course of potential values and the generation of events in a log calculator according to Fig. 21;
• Fig. 23 is a diagram of an exponential calculator according to one embodiment of the invention.
• Fig. 24 is a diagram showing the time course of potential values and the generation of events in an exponential calculator according to Fig. 23;
• Fig. 25 is a diagram of a multiplier device according to one embodiment of the invention.
• Fig. 26 is a diagram showing the time course of potential values and the generation of events in a multiplier device according to Fig. 25;
• FIG. 27 is a diagram of a signed multiplier device according to an embodiment of the invention
• FIG. 28 is a diagram of an integrating device according to one embodiment of the invention
• FIG. 29 is a diagram of a device adapted to solving a first-order differential equation in an exemplary embodiment of the invention.
• FIGS. 30A and 30B are graphs showing simulation results of the device of FIG. 29;
• FIG. 31 is a diagram of a device adapted to solving a second-order differential equation in an exemplary embodiment of the invention.
• FIGS. 32A and 32B are graphs showing simulation results of the device of FIG. 31;
• FIG. 33 is a diagram of a device adapted to the resolution of a system of nonlinear differential equations with three variables in an exemplary embodiment of the invention.
• Fig. 34 is a graph showing simulation results of the device of Fig. 33;
• FIG. 35 is a diagram of a programmable processing device according to one embodiment of the invention.
• a data processing apparatus as proposed herein proceeds by representing the quantities processed not as amplitudes of electrical signals or as binary coded numbers processed by logic circuits, but as time intervals between events. occurring within a set of processing nodes having connections to each other.
• an embodiment of the data processing device is presented according to an architecture similar to that of artificial neural networks.
• the data processing device does not necessarily have an architecture strictly in accordance with what people agree to call “neural networks”
• the following description uses the terms “node” and “neuron” interchangeably, as it uses the term “synapse” to designate connections between two nodes or neurons within the device.
• the synapses are oriented, i.e. each connection has a transmitting node and a receiving node, and transmitting to the receiving node events generated by the transmitting node. An event typically manifests itself as a peak ("spike") on a voltage or current signal delivered to the transmitting node and influencing the receiving node.
• each connection or synapse has a weight parameter w which measures the influence that the transmitting node exerts on the receiving node during an event.
• a description of the behavior of each node can be given by referring to a potential value V corresponding to the potential of membrane V in the paradigm of artificial neural networks.
• the potential value V of a node varies over time depending on the events that the node receives on its incoming connections. When this potential value V reaches or exceeds a threshold V t , the node transmits an event ("spike") which is transmitted to the node (s) located (s) downstream.
• the component g e is a component that remains constant, or substantially constant, between two events that the node receives on a particular synapse, referred to herein as a constant current component control connection.
• the component gf is an exponentially dynamic component, that is to say that it varies exponentially between two events that the node receives on a particular synapse which is called a current component adjustment connection. with exponential decay.
• a node that takes into account an exponentially decreasing gf current component may further receive activation and deactivation events of the gf component on a particular synapse referred to herein as an activation connection.
• t denotes time
• the component g e reflects a constant input current that can only be changed by synaptic events
• the component g / translates an exponential dynamic input current
• each synapse being associated with a weight parameter indicating a synaptic weight w, positive or negative:
• V-synapses which directly modify the value of the membrane potential of the neuron: V ⁇ - V + w.
• the receiving node responds to an event received on a V-synapse by adding to its potential value V the weight w indicated by the weight parameter;
• the receiving node responds to an event received on a g e- synapse by adding to the constant component of its current value the weight w indicated by the weight parameter; • exponential decay current component tuning connections, or ⁇ -synapses, which directly modify the exponential dynamic input current of the neuron: g / - g / + w.
• the receiving node responds to an event received on a ⁇ -synapse by adding to the exponential decay component of its current value the weight w indicated by the weight parameter;
• Each synaptic connection is further associated with a delay parameter which gives the delay of propagation between the emitting neuron and the receiving neuron.
• a neuron triggers an event, when its potential value V reaches a threshold V t , that is:
• the notation T syn designates the delay of propagation along a standard synapse
• the notation T neu designates the time that a neuron puts in transmitting the event by producing its spike after having been triggered by an input synaptic event T neu may for example reflect the time step of a neural simulator.
• Wi - W e (8)
• the quantities processed by the device are represented by time intervals between events. Two events of a pair of events are separated by a time interval At which is a function of the quantity x encoded by this pair:
• At f (x) (9) where / is a coding function chosen for the representation of the data in the device.
• the two events of the pair encoding this magnitude x can be delivered by the same n neuron or two different neurons.
• the encoding function /; I ⁇ . ⁇ H can be chosen taking into account the signals processed in a particular system, and adapted to the required accuracy.
• the / function calculates the interval between spikes associated with a particular value. In the remainder of the present description, embodiments of the processing device using a linear coding function are illustrated:
• the value of T min may be zero. However, it is advantageous that it be non-zero. Indeed, if two events representing a value come from the same neuron or are received by the same neuron, the minimum interval T m i n > 0 gives this neuron time to reset. On the other hand, a choice T m j n > 0 allows certain neural arrangements to react to the first input event and propagate a change of state before receiving a second event.
• the form (11) for the coding function / is not the only one possible. Another sensible choice is to take a logarithmic function, allowing to code an extended range of values with a dynamic suitability for certain applications, in this case with a lower accuracy for large values.
• [0) 78 To represent signed values, two different paths can be used, one for each sign. Positive values will then be encoded using a particular neuron, and negative values by means of another neuron. In an arbitrary manner, the zero can be represented as a positive value or a negative value. In the following, it is represented as a positive value.
• the choice (9) or (11) for the coding function leads to defining two standard weights for the g e- synapses.
• the weight w acc is further defined as being the value of g e necessary to trigger a neuron, from its reset state, at the end of the time ⁇ d , namely:
• the connections between nodes of the device may further each be associated with a respective delay parameter.
• This parameter indicates a delay with which the The receiving node of the connection performs a state change, relative to the transmission of an event on the connection.
• the indication of delay values by these delay parameters associated with the synapses makes it possible to ensure an adequate sequencing of the operations in the processing device.
• Various technologies can be used to implement the processing nodes and their interconnections to behave in the manner described by equations (I) - (6), including commonly used technologies in the well-known domain of artificial neural networks.
• Each node can for example be realized using an analog technology, with resistive and capacitive elements to keep and vary a voltage level and transistor elements to deliver events when the voltage level exceeds the threshold V t .
• connections are oriented with a symbol on the side of their receiving nodes. This symbol is an open square for an exciter connection, that is to say a positive one, and a solid square for an inhibitory connection, that is to say of negative weight;
• nodes or neurons represented in these figures are named in order to evoke the functions resulting from their arrangement within the circuit: 'input' for an input neuron, 'input +' for the input of a positive value, 'input -' for ⁇ input of a negative value, 'output' for an output neuron, 'output +' for the output of a positive value, 'output -' for the output of a negative value, 'recall' for a neuron serving to retrieve a value, 'acc' for an accumulator neuron, 'ready' for a neuron indicating the availability of a result or a value, etc.
• Figure 1 shows a very simple circuit 10 usable for producing the representation of a constant value x on demand.
• the two V-synapses 11, 12 of weight equal to or greater than w e (in the example shown, the weights are equal to w e ) each have a recall neuron 15 as the sending node and an output neuron 16 as the receiving node.
• the synapse 11 is configured with a delay parameter T syn
• the synapse 12 is configured with a delay parameter T syn + f (x).
• the activation of the recall neuron 15 causes the output neuron 16 to be triggered at the times T syn and T syn + f (x), so that the circuit 10 delivers two time-separated events of the value f (x) representing the constant x.
• Figure 2 shows a processing circuit 18 constituting an inverting memory.
• This group includes a 'first' neuron 23 and a 'last' neuron 25.
• Two excitatory V-synapses 22, 24 of delay T syn depart from the input neuron 21 to respectively to neuron first 23 and neuron last 25.
• V-synapse 22 has a weight w e
• V-synapse 24 has a weight equal to wJ2.
• the first neuron 23 self-inhibits by a V-synapse 28 of weight wi and delay T syn .
• the excitatory e- synapse 26 goes from the first neuron 23 to the accone neuron 30, and has the weight w acc and a delay T syn + T m i n .
• E g the inhibitory -synapse 27 will last the neuron 25 neuron acc 30, and presents the -w acc weight and delay T syn.
• An excitable V-synapse 32 goes from the recall neuron 31 to the output neuron 33, and has the weight w e and a delay 2T syn + T neu .
• An excitable V-synapse 34 goes from the recall neuron 31 to the accone neuron 30, and has the weight w aC c and a delay T syn .
• an excitatory V-synapse 35 goes from the neuron acc 30 to the output neuron 33, and has the weight w e and a delay T syn .
• the processing circuit 18 of the figure 2 functions similarly if certain weights are chosen as follows: the V-synapse 22 has a weight w equal to or greater than w e , the V-synapse 24 has a weight at least equal to w e 12 and smaller than V t , the first neuron 23 self-inhibits by a V-synapse 28 of weight -w, the excitatory V-synapse 32 has a weight equal to or greater than w e and the excitatory V-synapse 35 has a weight equal to or greater than w e .
• This remark extends to the following processing circuits.
• Figure 4 shows a processing circuit 40 constituting a memory.
• the memory circuit 40 has an input neuron 21 to receive the value to be stored, a read command input constituted by a recall neuron 48, a ready neuron 47 indicating from when a read command can be presented neuron recall 48, and a neuron output 50 to restore the stored value. All synapses of this memory circuit have the delay T syn .
• a ⁇ -synapse 41 goes from the first neuron 25 to the first acc 42 neuron, and has the weight 1 ⁇ 4v c .
• a ⁇ -synapse 43 goes from the neuron last 25 to the second neuron acc 44, and has the weight w acc .
• the memory circuit 40 operates for any encoding of the magnitude x by a time interval between T min and ⁇ , without being limited to the form (11) above.
• the signed memory circuit 60 is based on a memory circuit 40 of the type shown in Figures 4A-B.
• the input + and input-61 neurons are respectively connected to the input neuron 21 of the circuit 40 by excitatory V-synapses 63, 64 of weight w e .
• that of the two neurons 61, 62 which receives the two spikes representing ⁇ x ⁇ activates twice the input neuron 21 of the circuit 40, so that the time interval / (bel) will be restored on the output neuron 50 of the circuit 40.
• neurons 61, 62 are respectively connected to ready + and ready-65 neurons 66 by excitatory V-synapses 67, 68 of weight w e / 4.
• the signed memory circuit has a recall neuron 70 connected to the ready + and ready-65 neurons 66 by respective excitatory V-synapses 71, 72 of weight w e 12.
• Each of the ready + and ready-65 neurons 66 is connected to the recall neuron 48 of the circuit 40 by respective excitatory V-synapses 73, 74 of weight w e .
• An inhibitory V-synapse 75 of weight w, / 2 goes from the ready neuron + 65 to the ready-66 neuron, and conversely a 76-weight w / 2 inhibitory V-synapse goes from the ready-66 neuron to the ready neuron + 65.
• the neuron ready + 65 is connected to the neuron output- 82 of the memory circuit signed by a weight inhibitory V-synapse 77 wi.
• the ready-66 neuron is connected to the output neuron 81 of the memory circuit signed by an inhibitory V-synapse 78 of weight 2wi.
• the output neuron 50 of the circuit 40 is connected to the neurons output + and output-81, 82 by respective excitatory V-synapses 79, 80 of weight w e .
• the output of the signed memory circuit 60 comprises a ready neuron 84 which is the receiving node of an excitatory V-synapse 85 of weight w e from the ready neuron 47 of the memory circuit 40.
• FIG. 7 shows the behavior of the neurons of the signed memory circuit 60 (a) in the case of a positive input and (b) in the case of a negative input.
• the activation of the recall neuron 70 triggers the ready + 65 or ready-66 neuron via the V-synapse 70 or 71, and this trigger causes the other ready-66 or ready + 65 neuron to zero via the V-synapse. 75 or 76.
• the event delivered by the ready + 65 or ready-66 neuron inhibits the output-82 or output + 81 neuron via V-synapse 77 or 78, bringing its potential to -2V t .
• the event delivered by the ready + 65 or ready-66 neuron at the time t ign is supplied to via the V-synapse 73 or 74.
• This causes the emission of a pair of spikes separated by an interval of time equal to (
• This pair of spikes communicated to the neurons output + and output- 81, 82 via the V-synapses 79, 80 triggers twice, at times + (
• the signed memory circuit 60 shown in FIG. 6 is not optimized in terms of the number of neurons, since one can:
• FIG. 8 shows a processing circuit 90 for synchronizing the received signals to an N number of inputs (N> 2). All the synapses of this synchronization circuit have the delay T syn .
• the circuit 90 shown in FIG. 8 comprises N input neurons 91 0 ,..., 9Ly-i and N output neurons 92 0 , 92JV-I.
• Each input neuron 9 is the transmitting node of a V-synapse 93 k of weight w e whose receiving node is the input neuron 21 3 ⁇ 4 of a respective memory circuit 40 3 ⁇ 4 .
• the output neuron 50 ⁇ of each memory circuit 40 3 ⁇ 4 is the node emitter of a V-synapse 9 k of weight w e whose receiving node is the output neuron 92 k of the synchronization circuit 90.
• the synchronization circuit 90 comprises a sync neuron 95 which is the receiving node of N V-synapses excitatory 96o, 96JV-I of weight w N whose transmitting nodes are respectively the ready 47o, 47JV-I neurons of the circuits. memory 40o, 40jv-i.
• the circuit 90 further comprises excitatory V-synapses 97o, 97JV-I of weight w e having the sync neuron 95 for transmitter node and, respectively, the recall 48o, ..., 48JV-I neuron memory circuits 40o, .. ., 40JV-I for receiving nodes.
• the sync neuron 95 receives the events produced by the ready 47 0 , 47JV-I neurons as the N input signals are loaded into the memory circuits 40o, 40JV-I, ie at the times t dy0 ⁇ , t ⁇ dyl in Figure 9.
• the sync neuron 95 outputs an event T syn later, that is to say at the time 9.
• each memory circuit 40k produces its respective second spike at time t gUtk.
• the input neurons 91o, 91JV-I and output 92 0 , 92JV-I are optional, since the inputs can be provided directly by the input neurons 21o, 21JV-I of the memory circuits 40o, 40JV-I and the outputs directly by the neurons output 50o, 50JV-I memory circuits 40o, 40JV-I.
• the V-synapses 46 of the 40o, 40JV-I memory circuits can go directly to the sync neuron 95, without passing through a ready 47 0 , 47JV-I neuron.
• the synapses 97 0 , 97JV-I can directly attack the output 50o, 50JV-I neurons of the memory circuits (thus replacing their synapses 49), and the sync neuron 95 can also constitute the transmitting node of the synopses 51 memory 40o, 40JV-I to control the restart of accumulation in acc 44 neurons (FIGS. 4 and 5).
• the sync neuron 95 is excited by two V-synapses 46 of weight wJ2 coming directly from the neurons acc 42 of the two memory circuits, and it is the emitting node of the g e- synapses 51 to restart the accumulation in the neurons.
• a specific neuron 99 denoted Output ref
• the role of this neuron output ref 99 could, alternatively, be held by one of the two output neurons 92 0 , 92 ⁇ .
• the two events encoding the value of an output quantity of the circuit 98 are produced by two different neurons (for example the neurons 99 and 92 ⁇ for the magnitude x ⁇ ).
• the two events of a pair representing the value of a quantity it is not necessary for the two events of a pair representing the value of a quantity to come from a single node (in the case of a magnitude of output) or be received by a single node (in the case of an input quantity).
• FIG. 11 shows a processing circuit 100 which calculates the minimum between two values received synchronously on two input nodes 101, 102 and delivers this minimum on an output node 103.
• this circuit 100 comprises two 'smaller' neurons 104, 105.
• An excitatory V-synapse 106 of weight w 2, ranging from neuron input 101 to smaller neuron 104.
• An excitatory V-synapse 107, weight wJ2 ranges from neuron input 102 to neuron smaller 105.
• An excitatory V-synapse 108, weight w 2 goes from neuron input 101 to neuron output 103.
• An excitable V-synapse 109, of weight w 2 ranges from the input neuron 102 to the output neuron 103.
• An excitatory V-synapse 110 ranges from the smaller neuron 104 to the output neuron 103.
• a V-synapse exciter 111, of weight wJ2 goes from neuron smaller 105 to neuron output 103.
• An inhibitory V-synapse 112, of weight Wi / 2 goes from neuron smaller 104 to neuron smaller 105.
• An inhibitory V-synapse 114, of weight w goes from the smaller neuron 104 to the input neuron 102.
• An inhibitory V-synapse 115, of weight w goes from the neuron smaller 105 to the neuron input 101. All synapses 106-115 shown in Fig. 11 are associated with a delay T syn , except for synapses 108, 109 for which the delay is 2.T syn + T neu .
• FIG. 13 shows a processing circuit 120 which calculates the maximum between two values received synchronously on two input nodes 121, 122 and delivers this maximum on an output node 123.
• this circuit 120 comprises two 'larger' neurons 124, 125.
• An excitable V-synapse 126, weight w e / 2 goes from the input neuron 121 to the neuron larger 124.
• An excitatory V-synapse 127, weight w e / 2 goes from the input neuron 122 to the neuron larger 125.
• the emission of the second spike on the neuron input neuron with the smallest value, namely the neuron 121 at the time tf nl tf nl + At x in the example of FIG.
• Fig. 15 shows a subtraction circuit 140 which calculates the difference between two values xj, X2 received synchronously on two input nodes 141, 142 and outputs the result xi - 3 ⁇ 4 on an output node 143 if it is positive and on another output node 144 if it is negative.
• the subtraction circuit 140 comprises two sync neurons 145, 146 and two 'inb' neurons 147, 148.
• An excitatory V-synapse 150 goes from the input neuron 141 to the sync neuron 145.
• An excitatory V-synapse 151, weight wJ2 goes from the input neuron 142 to the sync neuron 146.
• Three excitatory V-synapses 152, 153, 154, each weight w e range from neuron sync 145 to output neuron + 143, neuron output-144 and neuron inb 147, respectively.
• Three excitatory V-synapses 155, 156, 157, each weight w e range from sync neuron 146 to output-144 neuron, output neuron + 143 and neuron 148, respectively.
• An inhibitory V-synapse 158 ranges from neuron sync 145 to neuron 148.
• Inhibitory V-synapse 159, weight w goes from neuron sync 146 to neuron 147.
• Excitatory V-synapse 160 goes from the neuron output + 143 to the neuron inb 148.
• An excitatory V-synapse 161, of weight wJ2, goes from the neuron output-144 to the neuron inb 147.
• An inhibitory V-synapse 162, of weight 2w goes from the neuron inb 147 to the neuron output + 143.
• An inhibitory V-synapse 163, weight 2w goes from the neuron inb 163 to the neuron output-144.
• the synapses 150, 151, 154 and 157-163 are associated with a delay of T syn .
• Synapses 152 and 155 are associated with a delay of T min + 3.T syn + 2.T neu .
• Synapses 153 and 156 are associated with a delay of 3.T syn + 2.T neu -
• FIG. 16 The operation of the subtraction circuit 140 according to FIG. 15 is illustrated by FIG. 16 in the case where the result xi - x 2 is positive. Things happen symmetrically if the result is negative.
• the synapse 159 inhibits the inb 147 neuron whose potential passes to the value -V t at time t S y nc2 + T syn -ti n2 + 2.
• T syn + T neu
• the synapse 155 then re-excites the output-144 neuron whose potential passes to the value -V, at time tf n2 + T min + 4. T syn + 3. T neu ;
• the synapse 154 excites the inb 147 neuron which resets its membrane potential
• the synapse 152 excites the neuron output + 143 which delivers an event at time all ⁇ t synci + m i n + 3. T syn + 3. T neu- ti ni + T m i n + 4. T syn + 4. T neu , which one This event in turn excites the neuron 148 whose potential is reset to zero at the time t + T S y n + T neu- ti ni + T m i n + 5. T S y n + 5. T neu .
• the neuron output + 143 delivers two events having between them a time interval At out between the events of the two pairs produced by the input neurons 141, 142, with: any ⁇ (-in T min 4- Tsyn 4- T neu ) - (tj n2 + 4. T S y n + 4. T neu )
• Zero neuron 171 is the receiving node of two excitatory V-synapses 172, 173 of weight wJ2 and of delay T neu , one from the neuron sync 145 and the other from the sync neuron 146. It is on the other hand the receptor node of two inhibitory V-synapses 174, 175 of weight wJ2 and of delay 2.T neu , one coming from the sync neuron 145 and the other of the sync neuron 146.
• the zero neuron 171 is self-excited by a V-synapse 176 of weight w e and delay T neu .
• it is the transmitting node of two inhibitory V-synapses of delay T neu , one 177 of weight Wi directed towards the neuron inb 148 and the other 178 of weight directed to the neuron output- 144.
• the zero neuron 171 acts as a coincidence detector between the events delivered by the sync neurons 145, 146. Since these two neurons only deliver events at the time of the second coding spike of their associated input, detecting this temporal coincidence is equivalent to detecting the equality of the two input values, provided that they are correctly synchronized.
• the zero neuron 171 produces an event only if it receives two events separated by a time interval less than T neu from the sync neurons 145, 146. In this case, it directly inhibits the output-144 neuron via the synapse 178 , and disables the inb 148 neuron via the synapse 177.
• two equal input values supplied to the subtractor circuit of FIG. 17 give rise to two events separated by a time interval equal to T min , that is to say coding a zero difference, at the output neuron output + 143, and no event on the output-144 neuron. If the input values are not equal, the zero neuron 171 is not activated and the subtractor operates in the same manner as that of FIG. 15 .
• the circuit 180 For each input value 3 ⁇ 4 (0 ⁇ k ⁇ N), the circuit 180 comprises an input neuron 181 k and input-182 k each forming part of a respective group of neurons arranged in the same way as in group 20 described above with reference to FIG.
• the neuron first connected to the input neuron 18 (0 ⁇ k ⁇ N) is the emitter node of a stimulating e- synapse 182 ⁇ of weight ⁇ 3 ⁇ 4.1 ⁇ 4v c and delay T min + T syn .
• the last neuron connected to the input neuron 18 is the node emitting an inhibitory ⁇ -synapse 183 of weight - Xk Wa ⁇ and of delay T syn .
• the neuron acc 184 accumulates the terms ⁇ 3 ⁇ 4.3 ⁇ 4.
• the accelerator neuron 187 is the receptor node of the excitatory ⁇ -synapse 182 and the inhibitory ⁇ -synapse 183.
• the circuit 180 further comprises a sync neuron 185 which is the receiving node of N V-synapses, each wJN weight and delay T syn , respectively from the last neurons connected to N input neuron 18 (0 ⁇ k ⁇ NOT).
• the sync neuron 185 is the emitting node of an excitatory e- synapse 186 of weight w acc and delay T syn , whose receiving node is the accession neuron 184.
• the acc echon neuron 184 integrates the quantity CCk-V t IT max over a period of time.
• the sync neuron 185 is triggered and excites the accelerated neuron via the ⁇ -synapse 186.
• the weighted sum is made available by the circuit 180 in its inverted form (1 - s).
• a weighted summation circuit 190 may have the structure shown in FIG. 19.
• a weighted cumulative circuit 180 of the type described with reference to FIG. 18 is associated with another acc 188 neuron and a neuron output 189.
• the accelerator neuron 188 is the receiving node of an excitatory ⁇ -synapse 191 of weight Waoe and delay T syn , and the emitter node of an excitatory V-synapse 192 of weight w e and delay T min + T syn .
• the output neuron 189 is also the receiving node of an excitatory V-synapse 193 of weight w e and of delay T syn .
• the linear dynamic accumulation starts on the accelerated neuron 188 at the same time as it restarts on the acceleration neuron 184 of the circuit 180, the two acceleration neurons 184, 188 being excited on the nonsynapses 186, 191 by the same event coming from the sync neuron 185.
• the expected weighted sum is well represented at the output of the circuit 190.
• the linear combination calculation circuit 200 shown in FIG. 20 comprises two accumulation circuits 180A, 180B of the type of that described with reference to FIG. 18.
• the input neurons 18 of the cumulative circuit 180A are respectively associated with the coefficients ⁇ 3 ⁇ 4 for 0 ⁇ k ⁇ M and with the inverted coefficients - ⁇ 3 ⁇ 4 for M ⁇ k ⁇ N. These input neurons 18 for 0 ⁇ k ⁇ M receive a pair of spikes representing 3 ⁇ 4 when 3 ⁇ 4> 0 and therefore form input + neurons for these quantities x 0 , XM- ⁇ - The input 18 neurons of the circuit 180A for M ⁇ k ⁇ N receive a pair of spikes representing 3 ⁇ 4 when 3 ⁇ 4 ⁇ 0 and therefore form input-type neurons for these XM variables, ⁇ ⁇ ⁇ , XN-I -
• the input 18 neurons of the weighted cumulative circuit 180B are respectively associated with the inverted coefficients - ⁇ 3 ⁇ 4 for 0 ⁇ k ⁇ M and with the coefficients ⁇ 3 ⁇ 4 for M ⁇ k ⁇ N. These input neurons 18 for 0 ⁇ k ⁇ M receive a pair of spikes representing 3 ⁇ 4 when 3 ⁇ 4 ⁇ 0 and thus form input-type neurons for these magnitudes x 0 , XM- ⁇ - The input 18 neurons of the circuit 180B for M ⁇ k ⁇ N receive a pair of spikes representing 3 ⁇ 4 when 3 ⁇ 4> 0 and therefore form input + neurons for these XM variables, ⁇ ⁇ ⁇ , XN-I -
• the two aggregation circuits 180A, 180B share their sync neuron 185 which is thus the receiving node of 2N V-synapses, each of weights w e IN and of delay T syn , from the neurons last coupled to the 2N neurons input 18.
• the sync neuron 185 of the linear combination calculating circuit 200 is therefore triggered once the N input variables x 0 ,..., 3 ⁇ 4 ⁇ - ⁇ , positive or negative, have been received on the neurons l & lk.
• the linear combination calculation circuit 200 of FIG. 20 comprises for this purpose two excitatory V-synapses 198, 199, of weight w e and of delay T min + T syn , directed towards the input neurons 141, 142 of the subtraction circuit 170.
• an excitatory V-synapse 201 of weight w e and delay T syn goes from the neuron acc 184 of the circuit 180A to the input neuron 141 of the subtractor circuit 170.
• An excitatory V-synapse 202 of weight w e and delay T syn goes from the neuron acc 184 of the circuit 180B to the other neuron input 142 of the subtractor circuit 170.
• the output-144 and output + 143 neurons of the subtractor circuit 170 are respectively connected, via exciter V-synapses 205, 206 of weight w e and of delay T syn , to two other neurons output + 203 and output-204 which constitute the outputs of the linear combination calculation circuit 200.
• a 'start' 207 neuron receiving two excitatory V-synapses 208, 209, of weight w e and of delay T syn , from the neurons output + 143 and output-144 of the subtractor circuit 170.
• the start neuron 207 self-inhibits by means of a V-synapse 210, weight Wi and delay T syn .
• the start 204 neuron delivers a spike simultaneously to the first spike of the output + 203 or output-204 neuron activated.
• linear combination calculation 200 operates as described above.
• the normalization factor must be taken into account in the result.
• the input neuron 211 belongs to a group of nodes 20 similar to that described with reference to FIG. 2.
• the first neuron 213 of this group 20 is the emitting node of a stimulating e- synapse 212 of weight w acc and delay T m i n + T syn
• the neuron last 215 is the node emitting an inhibitory ⁇ -synapse 214 of weight-w acc and delay T syn
• Both ⁇ -synapses 212, 214 have the same access neuron 216 as the receiving node.
• From neuron last 215 to neuron acc 216, there is also a ⁇ / - synapse 217 of weight 9mu.it V f ⁇ and of delay T syn , and a gay-synapse 218 of weight 1 and of delay T syn .
• the circuit 210 further comprises a neuron output 220 which is the receiving node of an excitatory V-synapse 221 of weight w e and of delay 2.T syn from the neuron last 215, and a V-synapse exciter 222 of weight w e and delay T m i n + T syn from the neuron acc 216.
• a neuron output 220 which is the receiving node of an excitatory V-synapse 221 of weight w e and of delay 2.T syn from the neuron last 215, and a V-synapse exciter 222 of weight w e and delay T m i n + T syn from the neuron acc 216.
• FIG. 22 The operation of the log computation circuit 210 according to FIG. 21 is illustrated by FIG. 22.
• the last neuron 215 also activates the exponential dynamics on the neuron acc 216 at the same time.
• the circuit 210 of FIG. 21 delivers the representation of log A c) when it receives the representation of a real number x such that A ⁇ x ⁇ 1, where log A (.) Denotes the basic logarithmic operation A. Assuming that, in the form (11), the time interval between the two events delivered by the output neuron 220 may exceed, the circuit 210 delivers the representation of ⁇ ⁇ ( ⁇ ) for any number x such that 0 ⁇ x ⁇ 1.
• the input neuron 231 belongs to a group of nodes 20 similar to that described with reference to FIG. 2.
• the first neuron 233 of this group 20 is the node emitting a n -synapse 232 of weight g mu i t and of delay T min + T syn , as well as of an excitatory gay-synapse 234 of weight 1 and of delay T m i n + T syn .
• the group 235 neuron last 235 is the node emitting an inhibitory gay-synapse 236 of weight -1 and delay T syn , as well as an excitatory e- synapse 237 of weight w acc and of delay T syn . Synapses have the same acc 238 neuron for receiving node.
• the circuit 230 further comprises a neuron output 240 which is the receiving node of an excitatory V-synapse 241 of weight w e and of delay 2.T syn from the neuron last 235, and a V-synapse exciter 242 weight w e and delay T min + T syn from the neuron acc 238.
• a neuron output 240 which is the receiving node of an excitatory V-synapse 241 of weight w e and of delay 2.T syn from the neuron last 235, and a V-synapse exciter 242 weight w e and delay T min + T syn from the neuron acc 238.
• the membrane potential of neuron 238 then evolves according to:
• V (t) V t . (l - A x + - t ⁇ (21)
• the second event triggered by synapse 242 occurs at time t ut acc + T min + T syn +
• the circuit 230 of FIG. 23 thus delivers the representation of A x when it receives the representation of a number x between 0 and 1.
• This circuit can admit input values x greater than 1 (At> ⁇ ⁇ ) and still deliver the representation of A x on its output neuron 240.
• the circuit 230 of FIG. 23 performs the inversion of the operation performed by the circuit 210 of FIG. 21. [00208] It is possible to take advantage of this to implement various non-linear calculations using simple operations between log computation and exponential computation circuits. For example, the sum of two logarithms allows to implement a multiplication, their subtraction allows to implement a division, the sum of n times the logarithm allows to raise a number x to an integer power n, and so on.
• the first neuron 253 k of this group 20 3 ⁇ 4 is the transmitting node of a g e k -synapse exciter 252 weight w acc and delay T min + T syn, while the last neuron k 255 is the source node of a g e inhibitory -synapse 254 3 ⁇ 4 weight- w acc and delay T syn .
• the two g e -synapses 252 3 ⁇ 4 , 254 3 ⁇ 4 from the node group 20 3 ⁇ 4 have as receiving node the same acc 256 k neuron which plays a role similar to the accelerator neuron 216 of FIG. 21.
• a sync neuron 260 which is the receiver of two V-excitatory synapses node 261 l5 261 2 WJ2 weight and delay T syn respectively from the neurones last 255 ⁇ , 255 2.
• a synapse 262 of weight g ⁇ u and of delay T syn and an excitatory gay-synapse 264 of weight 1 and of delay T syn go from neuron sync 260 to neuron acc 256 ⁇ .
• a ⁇ / - synapse 265 of weight g mu i t and of delay T syn and an excitatory gay-synapse 266 of weight 1 and of delay T syn go from the neuron acc 256 ⁇ to the neuron acc 256 2 .
• the circuit 250 comprises another acc 268 neuron which plays a role similar to the accelerator neuron 238 of FIG. 23.
• the accelerator neuron 268 is the receptor node of a 269 ⁇ / synapse of weight g mu i t and 3T syn , and a 270 excitatory gay synapse, weight 1 and 3T syn syn , both from the sync neuron 260.
• the acc 268 neuron is the receiving node of an inhibitory gay synapse 271, weight -1 and delay T syn , and excitatory e- synapse 272, weight w acc and delay T syn , both from the neuron acc 256 2 .
• the circuit 250 finally has a neuron output 274 which is the receiving node an excitatory V-synapse 275, of weight w e and 2T syn late, from the acceler 256 neuron 2 and an excitatory V-synapse 276, weight w e and delay T syn + T syn , from the neuron acc 268.
• a neuron output 274 which is the receiving node an excitatory V-synapse 275, of weight w e and 2T syn late, from the acceler 256 neuron 2 and an excitatory V-synapse 276, weight w e and delay T syn + T syn , from the neuron acc 268.
• Each of the two neurons acc 256 1; 256 2 behaves initially like the neuron acc 216 of Figure 21, with a linear progression 278 1; 278 2 of weight w acc over a first period of respective duration xi.T cod , X2-T cod , leading to store the potential values V t .x ⁇ and V t .X2 in acc 2561, 256 2 neurons.
• V-synapse 275 causes the emission of a first spike on the neuron output 274 at the time + 2T syn + T neu .
• the acc 268 neuron reaches the threshold V t and causes an event on the
• the emission of a second spike at time t% ut + T min + T syn + T neu .
• Figure 27 shows a multiplier circuit 290 which calculates the product of two signed values x ⁇ , JC 2 . All the synapses shown in Figure 27 show the delay T
• the multiplier circuit 290 For each input value 3 ⁇ 4 (1 ⁇ k ⁇ 2), the multiplier circuit 290 comprises an input neuron + 29 and an input-292 k neuron which are the transmitting nodes of two respective V-synapses 293 3 ⁇ 4 and 294 ⁇ weight e .
• the y-synapses 293i and 294i are directed towards a neuron input 25 ⁇ ⁇ of a multiplier circuit 250 of the kind shown in Figure 25, while the V-synapses 293 and 29-i are directed to the other input neuron 251 2 of the circuit 250.
• the multiplier circuit 290 has a + 295 output neuron and an output-296 neuron which are the receptor nodes of two respective excitatory V-synapses 297 and 298 of weight w e from the output neuron 274 of the circuit 250.
• the multiplier circuit 290 further comprises four sign 300-303 neurons connected to form a selection logic of the sign of the result of the multiplication.
• Each signaling neuron 300-303 is the receiving node of two respective excitatory V-synapses of weight w e / 4 from two of the four input neurons 291 3 ⁇ 4 , 292 ⁇ .
• the sign 300 neuron connected to input + 291 1 neurons ; 291 2 detects the reception of two positive x X2 inputs. It forms the emitting node of an inhibitory V-synapse 305 of weight 2wi going to the neuron output- 296.
• the sign 303 neuron connected to the input-292 1 neurons ; 292 2 detects the reception of two x ⁇ , x 2 negative inputs. It forms the transmitting node of a 308 inhibitory V-synapse of weight to neuron output- 296.
• the signal neuron 301 connected to the input- 292 ⁇ neurons and input + 292 ⁇ detects the reception of a negative input x ⁇ and a positive input JC 2 . It forms the emitter node of an inhibitory synapse V-306 2wi weight from the neuron 295.
• the neuron output + sign 302 connected to input neurons + 29 ⁇ ⁇ input- and 292 2 detects the reception of an input x ⁇ positive and a negative x 2 input. It forms the transmitting node of an inhibitory V-synapse 307 of weight 2wi going to the neuron output + 295.
• Inhibitory V-synapses are arranged between the 300-303 sign neurons to ensure that only one of them intervenes to inhibit one of the output 295 and output 296 neurons.
• Each neuron sign 300-303 corresponding to a sign (+ or -) of the product is thus the node emitting two inhibitory V-synapses of weight wJ2 going respectively to the two sign neurons corresponding to the opposite sign.
• the circuit 290 of FIG. 27 delivers two events separated from the time interval. on one of its outputs 295, 296, according to the sign of X1.X2, when the two numbers x ⁇ , JC 2 are presented with their respective signs on the inputs 29, 2923 ⁇ 4.
• Zero detection logic can be added to one of the inputs, as in Figure 17, to ensure that zero input will produce the time T min between two events produced on the neuron output + 295 and not the neuron output- 296.
• Figure 28 shows a circuit 310 that reconstructs a signal from its derivatives provided in signed form on a neuron of a pair of input + 311 and input-312 neurons. The integrated signal is presented, based on of its sign, by a neuron of a pair of output + 313 and output-314 neurons.
• the 321-332 synapses shown in FIG. 28 are excitatory V-synapses of weight w e . They have all the delay T syn except the synapse 329 whose delay is T m i n + T syn .
• the other input neurons + and input- 181 ⁇ circuit 200, associated with the coefficient ao 1, are respectively connected by two V-synapses 323, 324 to two output neurons + 315 and output- 316 of a circuit 217 whose role is to provide an initialization value xc, for the integration process.
• the circuit 317 essentially consists of the pair of output + 315 and output-316 neurons connected to the same recall neuron 15 as shown in FIG.
• Another initiating neuron 318 of the integration circuit 310 is the transmitting node of a synapse 325 whose receiving node is the recall neuron 15 of the circuit 317.
• the initiating neuron 318 loads the integrator with its initial value x 0. stored in circuit 317.
• Synapses 326, 327 are arranged to retroact, respectively, the neuron output + 143 of the linear combination circuit 200 on its input neuron + 18 lo and the output-144 neuron of the integration circuit 200 on its neuron input-18.
• a start neuron 319 is the transmitting node of two synapses 328, 329 which have a zero value in the form of two events separated from the time interval T m in on the input neuron + 18 of the integration circuit 180.
• the neurons output + 143 and output-144 of the linear combination circuit 200 are the respective transmitting nodes of two synapses 330, 331 whose receiving nodes are respectively the output 313 and output 314 neurons of the integration circuit 310.
• the integration circuit 310 finally has a new input neuron 320 which is the receiving node of a synapse 332 coming from the start neuron 207 of the linear combination circuit 200.
• the initial value xc is, according to its sign, delivered on the neuron output + 313 or output- 314 once the neuron init 318 and then the neuron start 319 have been activated.
• the synapses shown in Figure 29 are all excitatory V-synapses of weight w e and delay T
• a circuit 317 for supplying the constant X ⁇ similar to the circuit 317 described with reference to FIG. 28, in the form of the time interval f ( ⁇ XJ) between two spikes delivered either by its output neuron + 315, or by its output-316 neuron, according to the sign of X ⁇ .
• Two synapses 341, 342 retroact the output + 313 of the integrator circuit 310 on the other input input + 18 lo of the linear combination circuit 200 and, respectively, the output output 314 of the circuit 310 on the other input-18 input of the circuit 200.
• Two synapses 343, 344 go from the output output + 203 of the linear combination circuit 200 at input input + 311 of integrator circuit 310 and, respectively, of output output 204 of circuit 200 at input input 312 of circuit 310.
• the device of FIG. 29 has a pair of output + 346 and output-347 neurons which are the receiving nodes of two synapses resulting from the output + 313 and output-314 neurons of the integrator circuit 310.
• the init 348 and start 349 neurons are used to initialize and start the integration process.
• the init neuron 348 must be triggered before the integration process to load the initial value in the integrator circuit 310.
• the start neuron 349 is triggered to deliver the first value from the circuit 310.
• the device of Fig. 29 is carried out using 118 neurons if the components as described with reference to the preceding figures are used. This number of neurons can be reduced by optimization.
• Figure 31 shows a processing device that implements the resolution of the differential equation? O "dt ⁇ . U $ 2 dt ⁇ * ⁇ , where ⁇ and &> o are parameters that can take different values
• the synapses shown in Fig. 31 are all excitatory V-synapses of weight w e and delay T syn, since the quantities manipulated in this example are all positive. necessary to provide two separate paths for positive and negative values. Only the path relative to the positive values is therefore included.
• the device of FIG. 31 uses:
• Two integrating circuits 310A, 310B such as that shown in FIG. 28, with an integration step dt;
• a circuit 317 for supplying the constant X ⁇ similar to the circuit described with reference to FIG. 1, in the form of the time interval flX ⁇ ) between two spikes delivered by its output neuron 16 (X ⁇ > 0).
• a synapse 353 goes from the output output 203 of the linear combination circuit 200 to the input input 311 of the first integrator circuit 310A.
• a synapse 354 goes from the output output 313 of the first integrator circuit 310A to the input input 311 of the second integrator circuit 310B.
• the device of FIG. 31 has a output neuron 356 which is the receiving node of a synapse originating from the output neuron 313 of the second integrating circuit 310B.
• the init 358 and start 359 neurons make it possible to initialize and start the integration process.
• the init neuron 358 must be triggered prior to the integration process to load the initial values into the integrator circuits 310A, 310B.
• the start neuron 359 is triggered to deliver the first value from the second integrator circuit 310B.
• the device of FIG. 31 is made using 187 neurons if the components as described with reference to the preceding figures are used. This number of neurons can be reduced by optimization.
• the synapses shown in Fig. 33 are all excitatory V-synapses of weight w e and delay T syn . To simplify the drawing, only one path is represented, but it must be understood that each time there is a path for the positive values of the variables and, in parallel, a path for their negative values.
• the device of FIG. 33 uses: Two signed multiplication circuits 290A, 290B such as that shown in FIG. 27 to calculate the nonlinearities contained in the derivatives of X, Y and Z;
• Three linear combination circuits 200A, 200B, 200C such as that shown in FIG. 20 to calculate the derivatives of X, Y and Z;
• N 3 to wait until the three derivatives are calculated before changing the state of the system
• Three integrating circuits 310A, 310B, 310C of steps dt such as that represented in FIG. 28 to calculate the new state from the derivatives of X, Y and Z.
• Its input neuron 181Ao is excited from the output neuron 313A of the integrator circuit 310A, and its input neuron 181Ai from the output neuron 313B of the integrator circuit 310B.
• Its output neuron 203A is the transmitting node of a synapse going to the input neuron 91 0 of the synchronizing circuit 90.
• Three synapses are respectively the neuron output 92 0 Circuit synchronizer 90 to the input neuron 311A of 310A integrator circuit, the neuron output 92 ⁇ circuit 90 at input neuron 311B from 310B integrator circuit, and the output neuron 92 2 Circuit 90 to the input neuron 311C of the integrator circuit 310C.
• the input neuron 291 Ai of the multiplier circuit 290A is excited from the output neuron 313A of the integrator circuit 310A, and its input neuron 291A 2 from the output neuron 313C of the integrator circuit 31C0.
• the input neuron 291Bi of the multiplier circuit 290B is excited from the output neuron 313A of the integrator circuit 310A, and its input neuron 291B 2 from the output neuron 313B of the integrator circuit 310B.
• the device of FIG. 33 has three output neurons 361, 362 and 363 which are the receiving nodes of three respective excitatory V-synapses from the output neurons 313A, 313B and 313C of the integrator circuits 310A, 310B, 310C. These three output neurons 361-363 deliver event pairs whose intervals represent values of the solution ⁇ X (t), Y (t), Z (t) ⁇ calculated for the system (26).
• the device of FIG. 33 is made using 549 neurons if the components as described with reference to the preceding figures are used. This number of neurons can be significantly reduced by optimization.
• the points in FIG. 34 each correspond to a triplet ⁇ X (t), Y (t), Z (t) ⁇ of output values encoded by three pairs of spikes respectively delivered by the three output neurons 361-363 , in a three-dimensional graph illustrating a simulation of the device shown in FIG. 33.
• the point P represents the initialization values X (0), Y (0), Z (0) of the simulation.
• the other points represent triplets calculated by the device of Figure 33. [0) 272]
• the system behaves in the expected manner, in accordance with the strange attractor described by Lorenz.
• a programmable network 400 constituting the set of processing nodes, or a part thereof, in an exemplary implementation of the processing device is illustrated schematically in FIG. 35.
• the network 400 consists of multiple neurons. all having the same pattern of behavior based on events received on their connections.
• the behavior can be modeled by the equations (1) indicated above, with identical parameters T m and Tf for the different nodes of the network.
• a programming or configuration logic 420 is associated with the network 400 for adjusting the synaptic weights and the delay parameters of the connections between the nodes of the network 400.
• This configuration is operated in a manner analogous to that which is commonly practiced in the network. field of artificial neural networks.
• the configuration of the parameters of the connections is carried out according to the calculation program which it is necessary to execute and taking into account the relation employed between the intervals of time and the quantities which they represent, by example the relation (11). If the program is broken down into elementary operations, the configuration may result from a circuit assembly of the kind described above. This configuration is performed under the control of a control unit 410 provided with a man-machine interface.
• control unit 410 Another role of the control unit 410 and to provide the input quantities to the programmable network 400 as events separated by time intervals appropriate, for the network processing nodes 400 to execute the calculation and to deliver the results. These results are quickly retrieved by the control unit 410 to be presented to a user or an application that uses them.

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• 2015
  • 2015-07-13 FR FR1556659A patent/FR3038997A1/fr active Pending
• 2016
  • 2016-07-06 US US15/743,642 patent/US20180357527A1/en not_active Abandoned
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