EP3323090A1

EP3323090A1 - Data-processing device with representation of values by time intervals between events

Info

Publication number: EP3323090A1
Application number: EP16750928.0A
Authority: EP
Inventors: Ryad Benosman; Xavier LAGORCE
Original assignee: Centre National de la Recherche Scientifique CNRS; Institut National de la Sante et de la Recherche Medicale INSERM; Sorbonne Universite
Current assignee: Centre National de la Recherche Scientifique CNRS; Institut National de la Sante et de la Recherche Medicale INSERM; Sorbonne Universite
Priority date: 2015-07-13
Filing date: 2016-07-06
Publication date: 2018-05-23
Also published as: CN108369660A; KR20180077148A; JP2018529143A; US20180357527A1; IL256813A; CA2992036A1; FR3038997A1; WO2017009543A1; JP6732880B2

Abstract

The invention relates to a data-processing device including a set of processing nodes (21, 23, 25, 42, 44, 47, 48, 50) and connections between said nodes. Each connection (22, 24, 41, 43, 45, 46, 49, 51) is configured to transmit events sent by a transmitting node to a receiving node. Each node is arranged to vary a respective potential value as a function of events received thereby and to output an event when the potential value reaches a predetermined threshold. At least one input quantity of the data-processing device is represented by a time interval between two events received by at least one node, and at least one output quantity of the data-processing device is represented by a time interval between two events output by at least one node.

Description

The present invention relates to data processing techniques. Embodiments implement a new way of performing calculations in machines, particularly in programmable machines.

The vast majority of current computers are based on Von Neumann architecture. The data and program instructions are stored in a memory to which an arithmetic logic unit accesses sequentially to execute the program on the data. This sequential architecture is relatively inefficient, especially because of the requirement for many access to memory, reading and writing.

[0Θ 3] The search for energetically more effective alternatives has led to the proposal of non-clocked processing architectures that attempt to mimic the functioning of the brain. Recent projects, such as the SyNAPSE DARPA program, have led to the development of silicon-based neuromorphic card technologies, which make it possible to build a new type of calculator inspired by the shape, function and architecture of the brain. The main advantages of these systems without clock are their energy efficiency and the fact that the performance is related to the amount of neurons and synapses used. Several platforms that have been developed in this context, in particular:

• IBM TrueNorth (Paul A. Merolla, et al .: "A Million Spiking-Neuron Integrated Circuit with a Scalable Communication Network and Interface", Science, Vol 345, No. 6197, pages 668-673, August 2014);

• Neurogrid (Ben V. Benjamin, et al .: "Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations", Proceedings of the IEEE, Vol.102, No. 5, pages 699-716, May 2014) ;

• Spinnaker (Steve B. Furber, et al .: "The Spinnaker Project," Proceedings of the IEEE, Vol 102, No. 5, pages 652-665, May 2014).

[0Θ04] These machines essentially aim to simulate biology. Their main applications are in the field of learning, in particular to execute deep learning architectures such as neural networks or belief networks ("deep belief networks"). They are effective in several areas such as artificial vision, speech recognition and language processing. [1] 8 (15) There are other options, such as NEF ("Neural Engineering Framework"), which can simulate certain functionalities of the brain, including performing visual, cognitive and motor tasks (Chris Eliasmith, et al .: "A Large-Scale Model of the Functioning Brain ", Science, Vol 338, No. 6111, pages 1202-1205, November 2012).

[0006] These different approaches do not offer a general methodology for performing calculations in a programmable machine.

[1) 807] The purpose of this Convention is to propose a new approach for data representation and calculation. It is desirable that this approach lends itself to implementation with moderate energy consumption and massive parallelism. There is provided a data processing device, comprising a set of processing nodes and connections between the nodes. Each connection has a transmitting node and a receiving node among the set of processing nodes and is configured to transmit events delivered by the transmitting node to the receiving node. Each node is arranged to vary a respective potential value according to events it receives and to deliver an event when the potential value reaches a predefined threshold. At least one input quantity of the data processing device is represented by a time interval between two events received by at least one node, and at least one output quantity of the data processing device is represented by a time interval between two events delivered by at least one node.

The processing nodes constitute neuron-type calculation units. However, we are not particularly interested here in imitating the functioning of the brain. The term "neuron" is used in the memory for convenience of language, but does not necessarily signify a strong resemblance to the mode of functioning of the neurons of the cortex. [8810] By using a precise temporal organization of the events within the processing device, as well as various properties of the connections (synapses), one can obtain a general computing framework, able to calculate the elementary mathematical functions. We can then implement all existing mathematical operators, whether linear or not, without necessarily resorting to a Von Neumann architecture. From there, it becomes possible for the device to function as a conventional computer, but without the need for incessant round trips in memory and without relying on floating-point precision. It is the temporal concordances of synaptic events, or their temporal offsets, that form the basis of the representation of the data. [OOIï] The proposed methodology is in line with neuromorphic architectures that make no distinction between memory and calculation. Each connection of each processing node stores information and simultaneously uses this information for calculation. This is very different from the conventional computer organization that makes a distinction between memory and processing and causes Von Neumann's bottleneck, where much of the computation time is spent moving information between the two. Memory and the Central Processing Unit (John Backus: "Can Programming Be Liberated from the Neumann Style ?: A Functional Style and Its Algebra of Programs," Communications of the ACM, Vol 21, No. 8, pages 613- 641, August 1978). The operation is based on event-driven communication as in biological neurons, and thus allows execution with massive parallelism.

In one embodiment of the device, each processing node is arranged to reset its potential value when it issues an event. The reset may especially be at a zero potential value.

Many embodiments of the data processing device include, among the connections between the nodes, one or more potential variation connections each having a respective weight. The receiving node of such a connection is arranged to react to an event received on this connection by adding the weight of the connection to its potential value.

Potential variation connections may include connections excitatory, positive weight, and inhibitory connections, negative weight.

To manipulate a quantity within the device, the set of processing nodes may comprise at least a first node forming the receiving node of a first potential variation connection having a positive first weight at least equal to the predefined threshold. for the potential value, and at least one second node forming the receiving node of a second weight potential variation connection at least equal to half of the predefined threshold for the potential value and less than the predefined threshold for the value of the potential value. potential. The aforementioned first node further forms the transmitting node and the receiving node of a third weight potential variation connection equal to the opposite of the first weight, as well as the transmitting node of a fourth connection, while the second node further forms the transmitting node of a fifth connection. The first and second potential variation connections are then configured to receive each two events separated by a first time interval representing an input quantity so that the fourth and fifth connections carry respective events having a second time interval between them. in relation to the first time interval.

[001.7] Various operations can be performed using a device according to the invention.

In particular, an example of a data processing device comprises at least one minimum calculation circuit, which comprises itself:

first and second input nodes;

an output node;

first and second selection nodes;

first, second, third, fourth, fifth and sixth potential variation connections each having a first positive weight at least equal to half of the predefined threshold for the potential value and less than the predefined threshold for the potential value;

seventh and eighth potential variation connections each having a second weight opposite the first weight; and

ninth and tenth potential variation connections each having a third double weight of the second weight. [8819] In this minimum computation circuit, the first input node forms the transmitting node of the first and third connections and the receiving node of the tenth connection, the second input node forms the transmitting node of the second and fourth connections. and the receiving node of the ninth connection, the first selection node forms the transmitting node of the fifth, seventh and ninth connections and the receiving node of the first and eighth connections, the second selection node forms the transmitting node of the sixth, eighth and tenth connections and the receiving node of the second and seventh connections, and the output node forms the receiving node of the third, fourth, fifth and sixth connections. [8) Another example of a data processing device comprises at least one maximum calculation circuit, which itself comprises:

first and second input nodes;

an output node;

first and second selection nodes;

first, second, third and fourth potential variation connections each having a first positive weight at least equal to half of the predefined threshold for the potential value and less than the predefined threshold for the potential value; and

fifth and sixth potential variation connections each having a second weight equal to twice the opposite of the first weight. [8821] In this maximum computation circuit, the first input node forms the transmitting node of the first and third connections, the second input node forms the transmitting node of the second and fourth connections, the first selection node forms the sending node of the fifth connection and the receiving node of the first and sixth connections, the second selection node forms the sending node of the sixth connection and the receiving node of the second and fifth connections, and the output node forms the receiving node of the third and fourth connections.

Another example of a data processing device comprises at least one subtracter circuit, which comprises itself:

first and second synchronization nodes;

first and second inhibition nodes;

first and second output nodes; first, second, third, fourth, fifth and sixth potential variation connections each having a first positive weight at least equal to the predefined threshold for the potential value;

seventh and eighth potential variation connections each having a second weight equal to half the first weight;

ninth and tenth potential variation connections each having a third weight opposite the first weight; and

eleventh and twelfth potential variation connections each having a fourth double weight of the third weight. In this subtractor circuit, the first synchronization node forms the transmitting node of the first, second, third and ninth connections, the second synchronization node forms the transmitting node of the fourth, fifth, sixth and tenth connections, the first node of the first node. Inhibition forms the sending node of the eleventh connection and the receiving node of the third, eighth and tenth connections, the second muting node forms the transmitting node of the twelfth connection and the receiving node of the sixth, seventh and ninth connections, the first The output node forms the sending node of the seventh connection and the receiving node of the first, fifth, and eleventh connections, and the second output node forms the transmitting node of the eighth connection and the receiving node of the second, fourth, and twelfth connections. The first synchronization node is configured to receive, on at least one potential variation connection having the second weight, a first pair of events having between them a first time interval representing a first operand. The second synchronization node is configured to receive, on at least one potential variation connection having the second weight, a second pair of events having between them a second time interval representing a second operand, so that a third pair of events having between them a third time interval is delivered by the first output node if the first time interval is longer than the second time interval and by the second output node if the first time interval is shorter the second time interval, the third time interval representing the absolute value of the difference between the first and second operands.

The subtracter circuit may further comprise a zero detection logic including at least one detection node associated with detection connections and with the first and second synchronization nodes, one of the first and second inhibition nodes and one of the first and second output nodes. Detection and muting connections are faster than the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth connections, to inhibit the production of events by any of the first and second output nodes when the first and second time intervals are substantially equal.

[8 (125) In various embodiments of the device, the set of processing nodes comprises at least one node arranged to vary a current value as a function of events received on at least one current setting connection, and to varying its potential value over time with a rate of change proportional to said current value Such a processing node may in particular be arranged to reset its current value when it delivers an event.

[8) 26] The current value in at least some of the nodes has a constant component between two events received on at least one constant current component setting connection having a respective weight. The receiving node of a constant current component tuning connection is arranged to respond to an event received on that connection by adding the weight of the connection to the constant component of its current value.

Another example of a data processing device comprises at least one inverting memory circuit, which comprises itself:

an accumulator node;

first, second and third current constant component control connections, the first and third connections having the same positive weight and the second connection having a weight opposite the weight of the first and third connections; and

at least one fourth connection,

[8828] In this inverting memory circuit, the accumulator node forms the receiving node of the first, second and third connections and the sending node of the fourth connection, and the first and second connections are configured to respectively address the accumulator node of the first and second connections. second event having between them a first time interval in relation to a time interval representing a quantity to be stored, so that the accumulator node then reacts to a third an event received on the third connection by increasing its potential value until delivery of a fourth event on the fourth connection, the third and fourth events having between them a second time slot in relation to the first time slot. [1) 829] Another example of a data processing device comprises at least one memory circuit, which itself comprises:

first and second accumulator nodes;

first, second, third and fourth current constant component control connections, the first, second and fourth connections each having a first positive weight and the third connection having a second weight opposite the first weight; and

at least one fifth connection.

In this memory circuit, the first storage node forms the receiving node of the first connection and the transmitting node of the third connection, the second storage node forms the receiving node of the second, third and fourth and fifth connections and the transmitting node. of the fifth connection, the first and second connections are configured to respectively address to the first and second accumulator nodes first and second events having between them a first time interval in relation to a time interval representing a quantity to be stored, so that the second storage node then responds to a third event received on the fourth connection by increasing its potential value until delivery of a fourth event on the fifth connection, the third and fourth events having a second time slot between them; relationship with the first interval of t ime. The memory circuit may further comprise a sixth connection having the first storage node as the transmitting node, the sixth connection providing an event to signal read availability of the memory circuit.

Another example of a data processing device comprises at least one synchronization circuit, which includes a number N> 1 of memory circuits, of the type just mentioned, and a synchronization node. The synchronization node is sensitive to each event delivered on the sixth connection of one of the N circuits of memory via a respective potential variation connection of weight equal to the first weight divided by N. The synchronization node is arranged to cause simultaneous reception of the third events via the fourth respective connections of the N memory circuits.

[0Θ33] Another example of a data processing device comprises at least one accumulation circuit, which itself comprises:

N entries each having a respective weighting coefficient, N being an integer greater than 1;

an accumulator node;

a synchronization node;

for each of the N entries of the accumulation circuit:

a first constant current component setting connection having a first positive weight proportional to the respective weighting coefficient of said input; and

a second constant current component setting connection having a second weight opposite the first weight;

a third constant current component setting connection having a third positive weight.

[8 (134) In this accumulation circuit, the accumulator node forms the receiving node of the first, second and third connections, the synchronization node forms the transmitting node of the third connection For each of the N inputs, the first and second connections are configured to respectively address to the accumulator node first and second events having between them a first time slot representing a respective operand provided on said input.The synchronization node is configured to deliver a third event once the first and second events have addressed for each of the N inputs, so that the accumulator node increases its potential value until a fourth event is delivered The third and fourth events have between them a second time interval in relation to a time interval representing a weighted sum of the operands provided on the N inputs.

[0 (135) In an exemplary data processing device according to the invention, the Cumulative circuitry is part of a weighted summation circuit further comprising:

a second accumulator node;

a fourth constant current component setting connection having the third weight; and

fifth and sixth connections.

In this weighted summation circuit, the accumulator circuit synchronization node forms the transmitting node of the fourth connection, the accumulator circuit accumulator node forms the transmitting node of the fifth connection, and the second accumulator node forms the node. receiver of the fourth connection and the transmitting node of the sixth connection. In response to the delivery of the third event by the synchronization node, the accumulator circuit accumulator node increases its potential value until the fourth event is delivered on the fifth connection, and the second storage node increases its potential value. until a fifth event is delivered on the sixth connection, the fourth and fifth events having between them a third time interval in relation to a time interval representing a weighted sum of the operands provided on the N entries of the accumulation circuit.

Another example of a data processing device comprises at least one linear combination circuit including two accumulation circuits, which share their synchronization node, and a subtractor circuit configured to react to the third event delivered by the shared synchronization node. and the fourth events respectively delivered by the accumulator nodes of the two accumulation circuits by delivering a pair of events having between them a third time interval representative of the difference between the weighted sum for one of the two accumulation circuits and the sum weighted for the other of the two accumulation circuits. In a number of embodiments of the device, the set of processing nodes comprises at least one node whose current value has an exponential decay component between two events received on at least one current component setting connection. with exponential decay having a respective weight. The receiving node of an exponential decay current component tuning connection is arranged to respond to an event received on that connection by adding the weight of the connection to the exponentially decreasing component of its current value. [8839] Another example of a data processing device comprises at least one log computation circuit, which itself comprises:

an accumulator node;

first and second constant current component control connections, the first connection having a positive weight, and the second connection having a weight opposite to the weight of the first connection;

a third exponential decay current component setting connection; and

at least one fourth connection. [8840] In this logarithmic circuit, the accumulator node forms the receiving node of the first, second and third connections and the transmitting node of the fourth connection. The first and second connections are configured to address to the accumulator node first and second respective events having between them a first time slot in relation to a time interval representing an input quantity of the log computation circuit. The third connection is configured to address to the accumulator node a third event simultaneous or subsequent to the second event, so that the accumulator node increases its potential value until a fourth event is delivered on the fourth, third, and fourth connection. events having between them a second time interval in relation to a time interval representing a logarithm of the input quantity.

[0841] There may further be in the processing device at least one deactivation connection whose receiving node is a node capable of canceling its exponential decay current component in response to an event received on the deactivation connection. [8842] Another example of a data processing device comprises at least one exponential calculating circuit, which itself comprises:

an accumulator node;

a first exponential decay current component tuning connection;

a second deactivation connection;

a third constant current component setting connection; and at least one fourth connection.

In this exponential calculating circuit, the accumulator node forms the receiving node of the first, second and third connections and the transmitting node of the fourth connection. The first and second connections are configured to address to the accumulator node first and second respective events having between them a first time interval in relation to a time interval representing an input quantity of the exponential calculating circuit. The third connection is configured to address to the accumulator node a third event simultaneous or subsequent to the second event, so that the accumulator node increases its potential value until a fourth event is delivered on the fourth, third, and fourth connection. events having between them a second time interval in relation to a time interval representing an exponential of the input quantity.

[8) 44] Another example of a data processing device comprises at least one multiplier circuit, which itself comprises:

first, second and third accumulator nodes;

a synchronization node;

first, second, third, fourth and fifth current constant component control connections, the first, third and fifth connections having a positive weight, and the second and fourth connections having a weight opposite to the weight of the first, second and fifth connections. ;

sixth, seventh, and eighth exponential decay current component tuning connections;

a ninth deactivation connection; and

at least one tenth connection. In this multiplier circuit, the first storage node forms the receiving node of the first, second and sixth connections and the sending node of the seventh connection, the second storage node forms the receiving node of the third, fourth and seventh connections and the node. Transmitting the fifth and ninth connections, the third storage node forms the receiving node of the fifth, eighth and ninth connections and the sending node of the tenth connection, and the synchronization node forms the sending node of the sixth and eighth connections. The first and second Connections are configured to address to the first accumulator node respective first and second events having between them a first time interval in relation to a time interval representing a first operand of the multiplier circuit. The third and fourth connections are configured to address to the second storage node respective third and fourth events having between them a second time slot in relation to a time slot representing a second operand of the multiplier circuit. The synchronization node is configured to deliver a fifth event on the sixth and eighth connections once the first, second, third, and fourth events have been received. As a result, the first storage node increases its potential value until a sixth event is delivered on the seventh connection and then, in response to the sixth event, the second storage node increases its potential value until delivery is completed. a seventh event on the fifth and ninth connections. In response to this seventh event, the third accumulator node increases its potential value until an eighth event is delivered on the tenth connection, with the seventh and eighth events having a third time interval in relation to an interval of time between them. time representing the product of the first and second operands.

[8846] Sign detection logic may be associated with the multiplier circuit for detecting the respective signs of the first and second operands and cause two events to be delivered having between them the time interval representing the product of the first and second operands on one of the first and second operands. either of two outputs of the multiplier circuit according to the detected signs.

[8847] In a typical embodiment of the processing device, each connection is associated with a delay parameter, to signal to the receiving node of this connection to perform a change of state with, compared to the reception of an event on the connection, a delay indicated by said parameter.

[8) 48] The time interval Δt between two events representing a magnitude of absolute value x can be, in particular, of the form At = T _min + xT _cod , where T _min and T _co are predefined temporal parameters. The quantities represented by time intervals have, for example, absolute values x ranging between 0 and 1.

[8849] A logarithmic rather than a linear scale of At as a function of x can also suitable for certain applications. Other scales can be used.

The processing device may have special arrangements for manipulating signed quantities. He can thus understand, for an input quantity:

a first input having a node or two nodes among the set of processing nodes, the first input being arranged to receive two events having between them a time interval representing a positive value of the input quantity; and

a second input having a node or two nodes among the set of processing nodes, the second input being arranged to receive two events having between them a time interval representing a negative value of the input quantity.

For an output quantity, the processing device may comprise:

a first output having a node or two nodes among the set of processing nodes, the first output being arranged to output two events having between them a time interval representing a positive value of said output quantity; and a second output having a node or two nodes among the set of processing nodes, the second output being arranged to output two events having between them a time interval representing a negative value of said output quantity.

[1) 852] In an implementation of the processing device, the set of processing nodes is in the form of at least one programmable network, the nodes of the network having a common behavior model as a function of the received events. This device further comprises programming logic for setting weights and delay parameters of the connections between the nodes of the network according to a calculation program, and a control unit for providing input quantities to the network and recovering output quantities calculated in accordance with the program.

[8] 53] Other features and advantages of the present invention will appear in the description below, with reference to the accompanying drawings, in which:

- Figure 1 is a diagram of a processing circuit producing the representation of a constant value on demand, according to one embodiment of the invention;

FIG. 2 is a diagram of an inverting memory device according to one embodiment of the invention; Fig. 3 is a diagram showing the time course of potential values and the generation of events in an inverter memory device according to Fig. 2;

Figure 4 is a diagram of a memory device according to one embodiment of the invention;

Fig. 5 is a diagram showing the time course of potential values and the generation of events in a memory device according to Fig. 4;

Figure 6 is a diagram of a signed memory device according to an embodiment of the invention;

FIGS. 7 (a) and 7 (b) are diagrams showing the evolution in time of potential values and the production of events in a signed memory device according to FIG. 6 when it is presented with different values of 'Entrance ;

Figure 8 is a diagram of a synchronization device according to one embodiment of the invention;

Fig. 9 is a diagram showing the time course of potential values and the generation of events in a timing device according to Fig. 8;

Fig. 10 is a diagram of a synchronization device according to another embodiment of the invention;

Figure 11 is a diagram of a minimum computing device according to one embodiment of the invention;

Fig. 12 is a diagram showing the time course of potential values and the generation of events in a minimum computing device according to Fig. 11;

Figure 13 is a diagram of a maximum computing device according to one embodiment of the invention;

Fig. 14 is a diagram showing the time course of potential values and the generation of events in a maximum computing device according to Fig. 13; Fig. 15 is a diagram of a subtractor device according to one embodiment of the invention;

Fig. 16 is a diagram showing the time course of potential values and the generation of events in a subtractor device according to Fig. 15;

Fig. 17 is a diagram of a variant of the subtractor device in which a difference equal to zero is taken into account;

Fig. 18 is a diagram of an accumulation circuit according to an embodiment of the invention;

Fig. 19 is a diagram of a weighted summation device according to an embodiment of the invention;

Fig. 20 is a diagram of a linear combination calculating device according to an embodiment of the invention;

Fig. 21 is a diagram of a log computing device according to one embodiment of the invention;

Fig. 22 is a diagram showing the time course of potential values and the generation of events in a log calculator according to Fig. 21;

Fig. 23 is a diagram of an exponential calculator according to one embodiment of the invention;

Fig. 24 is a diagram showing the time course of potential values and the generation of events in an exponential calculator according to Fig. 23;

Fig. 25 is a diagram of a multiplier device according to one embodiment of the invention;

Fig. 26 is a diagram showing the time course of potential values and the generation of events in a multiplier device according to Fig. 25;

Fig. 27 is a diagram of a signed multiplier device according to an embodiment of the invention; FIG. 28 is a diagram of an integrating device according to one embodiment of the invention;

FIG. 29 is a diagram of a device adapted to solving a first-order differential equation in an exemplary embodiment of the invention;

FIGS. 30A and 30B are graphs showing simulation results of the device of FIG. 29;

FIG. 31 is a diagram of a device adapted to solving a second-order differential equation in an exemplary embodiment of the invention;

FIGS. 32A and 32B are graphs showing simulation results of the device of FIG. 31;

FIG. 33 is a diagram of a device adapted to the resolution of a system of nonlinear differential equations with three variables in an exemplary embodiment of the invention;

Fig. 34 is a graph showing simulation results of the device of Fig. 33;

FIG. 35 is a diagram of a programmable processing device according to one embodiment of the invention.

[8) 54] A data processing apparatus as proposed herein proceeds by representing the quantities processed not as amplitudes of electrical signals or as binary coded numbers processed by logic circuits, but as time intervals between events. occurring within a set of processing nodes having connections to each other.

In the context of this presentation, an embodiment of the data processing device is presented according to an architecture similar to that of artificial neural networks. Although the data processing device does not necessarily have an architecture strictly in accordance with what people agree to call "neural networks", the following description uses the terms "node" and "neuron" interchangeably, as it uses the term "synapse" to designate connections between two nodes or neurons within the device. [8856] The synapses are oriented, i.e. each connection has a transmitting node and a receiving node, and transmitting to the receiving node events generated by the transmitting node. An event typically manifests itself as a peak ("spike") on a voltage or current signal delivered to the transmitting node and influencing the receiving node. [0857] As is customary in the context of artificial neural networks, each connection or synapse has a weight parameter w which measures the influence that the transmitting node exerts on the receiving node during an event.

[0858] A description of the behavior of each node can be given by referring to a potential value V corresponding to the potential of membrane V in the paradigm of artificial neural networks. The potential value V of a node varies over time depending on the events that the node receives on its incoming connections. When this potential value V reaches or exceeds a threshold V _t , the node transmits an event ("spike") which is transmitted to the node (s) located (s) downstream.

[01) 59] To describe the behavior of a node, or neuron, in an exemplary embodiment of the invention, reference may be made to a current value g having a component g _e and possibly a component gf.

[01) 60] The component g _e is a component that remains constant, or substantially constant, between two events that the node receives on a particular synapse, referred to herein as a constant current component control connection. [01) 61] The component gf is an exponentially dynamic component, that is to say that it varies exponentially between two events that the node receives on a particular synapse which is called a current component adjustment connection. with exponential decay.

[0862] A node that takes into account an exponentially decreasing gf current component may further receive activation and deactivation events of the gf component on a particular synapse referred to herein as an activation connection.

[0863] In the example considered, it is thus possible to express the behavior of a processing node generically by a set of differential equations: dV

= 9th + gate dt (1)

t denotes time;

the component g _e reflects a constant input current that can only be changed by synaptic events;

the component g / translates an exponential dynamic input current;

is a binary activation (gate = 1) or deactivation (gate = 0) signal of the gf exponential decay component;

T _m is a time constant controlling the linear variation of the potential value V as a function of the current value g = g _e + gate. boy Wut/;

and if is a time constant controlling the exponential dynamics of the decay of the gf component.

In the system (1), it is considered that there is no leakage of the membrane potential V, or that the dynamics of this leak is on a much larger time scale than all the other dynamics at the in the device.

In this model, we can distinguish four types of synapses influencing the behavior of a neuron, each synapse being associated with a weight parameter indicating a synaptic weight w, positive or negative:

• Potential variation connections, or V-synapses, which directly modify the value of the membrane potential of the neuron: V <- V + w. In other words, the receiving node responds to an event received on a V-synapse by adding to its potential value V the weight w indicated by the weight parameter;

• constant component of current control connections, or g _e -synapses, which directly modify the constant input current of the neuron: g _e <- _e + w g. In other words, the receiving node responds to an event received on a g _e- synapse by adding to the constant component of its current value the weight w indicated by the weight parameter; • exponential decay current component tuning connections, or ^ -synapses, which directly modify the exponential dynamic input current of the neuron: g / - g / + w. In other words, the receiving node responds to an event received on a ^ -synapse by adding to the exponential decay component of its current value the weight w indicated by the weight parameter;

• and activation connections, or gay-synapses, that activate the neuron by fixing <- 1 when they indicate a positive weight w = 1 and turn off the neuron by fixing <- 0 when they indicate a negative weight w = - 1.

Î0Û66] Each synaptic connection is further associated with a delay parameter which gives the delay of propagation between the emitting neuron and the receiving neuron.

[8) 67] A neuron triggers an event, when its potential value V reaches a threshold V _t , that is:

V≥V _t (2)

ÎÛ068] The triggering of the event results in a peak ("spike") delivered on each synapse whose neuron constitutes the sending node and by resetting its state variables to:

V ^ V _reset (3) gf ^ O (5) spoil <- 0 (6)

[0Θ69] Without loss of generality, one can place oneself in the case where V _reset = 0.

[8 (170) In the following, the notation T _syn designates the delay of propagation along a standard synapse, and the notation T _neu designates the time that a neuron puts in transmitting the event by producing its spike after having been triggered by an input synaptic event T _neu may for example reflect the time step of a neural simulator.

We define a standard weight w _e as the minimum excitation weight that must be placed on a V-synapse to trigger a neuron since the reset state, and another standard weight Wi as the inhibition weight d contrary effect: w _e = V _t (7)

Wi = - W _e (8)

[8872] The quantities processed by the device are represented by time intervals between events. Two events of a pair of events are separated by a time interval At which is a function of the quantity x encoded by this pair:

At = f (x) (9) where / is a coding function chosen for the representation of the data in the device.

[01) 73] The two events of the pair encoding this magnitude x can be delivered by the same n neuron or two different neurons.

[8874] When it is the same neuron n, delivering events at successive instants e _n (i), i = 0, 1, 2, etc., we can consider that this neuron n codes a signal u (t ) varying over time, whose discrete values are given by:

V-ÎAÎ}} = + 1) - W =% en p € (10) where ¹ is the inverse coding function chosen and i is an even number.

[1) 875] The encoding function /; I {. → H can be chosen taking into account the signals processed in a particular system, and adapted to the required accuracy. The / function calculates the interval between spikes associated with a particular value. In the remainder of the present description, embodiments of the processing device using a linear coding function are illustrated:

At = f (x) = T _min + x. T _cod (11) with x G [0, 1].

[8876] This representation of the function /: [0, 1] -> X mm, T _ma A is used to linearly code any value x between 0 and 1 by a time interval between T _min and T _max = T _min + T _cod . The value of T _min may be zero. However, it is advantageous that it be non-zero. Indeed, if two events representing a value come from the same neuron or are received by the same neuron, the minimum interval T _m i _n > 0 gives this neuron time to reset. On the other hand, a choice T _m j _n > 0 allows certain neural arrangements to react to the first input event and propagate a change of state before receiving a second event.

The form (11) for the coding function / is not the only one possible. Another sensible choice is to take a logarithmic function, allowing to code an extended range of values with a dynamic suitability for certain applications, in this case with a lower accuracy for large values.

[0) 78] To represent signed values, two different paths can be used, one for each sign. Positive values will then be encoded using a particular neuron, and negative values by means of another neuron. In an arbitrary manner, the zero can be represented as a positive value or a negative value. In the following, it is represented as a positive value.

Thus, to extend the example of the form (11), if a magnitude x has a value in the interval [-1, +1], it is represented by a time interval At = Τ ^ _η + \ x \ .T _cod between two events propagated on the path associated with positive values if x≥ 0, and on the path associated with negative values if x <0.

[0880] The choice (9) or (11) for the coding function leads to defining two standard weights for the g _e- synapses. The weight w _acc is defined as the value of g _e needed to trigger a neuron from its reset state at the end time m _a x = T _min + T _cod, or, by (1): = Wacc V _t . ^ (12)

max

[0881] The weight w _{acc is} further defined as being the value of g _e necessary to trigger a neuron, from its reset state, at the end of the time _∞d , namely:

Wacc = V _t . ^ (13)

1 cod

[8082] For g _e -synapses, we can give ourselves another standard weight g ^ u: Bruni _t = V _t '(14)

[0883] The connections between nodes of the device may further each be associated with a respective delay parameter. This parameter indicates a delay with which the The receiving node of the connection performs a state change, relative to the transmission of an event on the connection. The indication of delay values by these delay parameters associated with the synapses makes it possible to ensure an adequate sequencing of the operations in the processing device. [1] 884] Various technologies can be used to implement the processing nodes and their interconnections to behave in the manner described by equations (I) - (6), including commonly used technologies in the well-known domain of artificial neural networks. Each node can for example be realized using an analog technology, with resistive and capacitive elements to keep and vary a voltage level and transistor elements to deliver events when the voltage level exceeds the threshold V _t .

[8885] Another possibility is to use digital technologies, for example based on FPGA ("field-programmable trick arrays"), which offer a convenient way of implementing artificial neurons. [8886] In the following, we present a number of data processing devices or circuits realized using interconnected processing nodes. In FIGS. 1, 2, 4, 6, 8, 10, 11, 13, 15, 17, 18, 19, 20, 21, 23, 25, 27, 28, 29, 31 and 33:

• the connections between nodes represented in solid lines are V-synapses;

• the connections represented in broken lines are g _e -synapses;

· The connections represented in dotted lines are ^ / - synapses;

• the connections shown in dotted lines are gay-synapses;

• the connections are oriented with a symbol on the side of their receiving nodes. This symbol is an open square for an exciter connection, that is to say a positive one, and a solid square for an inhibitory connection, that is to say of negative weight;

• the parameter pair (w; T) next to a connection indicates the weight w and the delay T associated with the connection. Sometimes only the weight w is indicated.

[0Θ87] Some of the nodes or neurons represented in these figures are named in order to evoke the functions resulting from their arrangement within the circuit: 'input' for an input neuron, 'input +' for the input of a positive value, 'input -' for Γ input of a negative value, 'output' for an output neuron, 'output +' for the output of a positive value, 'output -' for the output of a negative value, 'recall' for a neuron serving to retrieve a value, 'acc' for an accumulator neuron, 'ready' for a neuron indicating the availability of a result or a value, etc. [1) 888] Figure 1 shows a very simple circuit 10 usable for producing the representation of a constant value x on demand. The two V-synapses 11, 12 of weight equal to or greater than w _e (in the example shown, the weights are equal to w _e ) each have a recall neuron 15 as the sending node and an output neuron 16 as the receiving node. The synapse 11 is configured with a delay parameter T _syn , while the synapse 12 is configured with a delay parameter T _syn + f (x).

[08] The activation of the recall neuron 15 causes the output neuron 16 to be triggered at the times T _syn and T _syn + f (x), so that the circuit 10 delivers two time-separated events of the value f (x) representing the constant x.

A. Briefs

A. l. Invertible memory

[8) 90] Figure 2 shows a processing circuit 18 constituting an inverting memory.

[8891] This device 18 stores an analog value x encoded by a pair of input spikes supplied to an input neuron 21 with an interval At _in = f (x), using a current integration on the dynamic g _e in a acc neuron 30. the x value is stored in the membrane potential of the neuron 30 access and read during activation of a recall neuron 31, which leads to issue a pair of events separated by a corresponding time interval at _out to the value 1 - x at the level of the output neuron 33, ie At _out = f (l - x). [) 892] The input neuron 21 belongs to a group of nodes 20 for producing two separate events of f (x) -T _m j _n = xT _co d on ^ -synapses 26, 27 directed to the acc 30 neuron. This group includes a 'first' neuron 23 and a 'last' neuron 25. Two excitatory V-synapses 22, 24 of delay T _syn depart from the input neuron 21 to respectively to neuron first 23 and neuron last 25. V-synapse 22 has a weight w _e , while V-synapse 24 has a weight equal to wJ2. The first neuron 23 self-inhibits by a V-synapse 28 of weight wi and delay T _syn .

[8893] The excitatory _e- synapse 26 goes from the first neuron 23 to the accone neuron 30, and has the weight w _acc and a delay T _syn + T _m i _n . _E g the inhibitory -synapse 27 will last the neuron 25 neuron acc 30, and presents the -w _acc weight and delay T _syn. An excitable V-synapse 32 goes from the recall neuron 31 to the output neuron 33, and has the weight w _e and a delay 2T _syn + T _neu . An excitable V-synapse 34 goes from the recall neuron 31 to the accone neuron 30, and has the weight w _aC c and a delay T _syn . Finally, an excitatory V-synapse 35 goes from the neuron acc 30 to the output neuron 33, and has the weight w _e and a delay T _syn .

[01) 94] The operation of the inverting memory device 18 is illustrated in FIG.

[1) 895] The emission of a first event (spike) at the time tf _n at the level of the input neuron 21 triggers an event at the output of the first neuron 23 at the end of the time T _syn + T _neu , ie at the time tj _first in FIG. 3, and raises to V / 2 the potential value of the neuron last 25. The first neuron 23 is then inhibited via the synapse 28 by giving the value -V _t to its membrane potential, and it starts accumulation by the accelerated neuron after T _syn + T _m i _n , ie at time t _t , via the ^ -synapse 26.

[8896] The emission of the second spike at time tf _n = tf _n + T _min + x. T _cod at the level of the input neuron 21 brings the neuron last 25 to the threshold potential V _t . An event is then produced at the time tf _ast = tf _n + T _syn + T _neu on the inhibitory g _e -synapse 27. The second spike also causes the resetting of the potential of the first neuron 23 via the synapse 22. The event transported by the _e- synapse 27 in response to the second spike stops the accumulation made by the neuron acc 30 = _t + _t +. T _cod . [8897] At this point, the potential value V _t . stored in the neuron acc 30

to keep the value x. Its complement 1 - x can then be read by activating the recall neuron 31, which takes place at the time _shown in FIG. 3. This activation restarts the accumulation process in the neuron acc up to the time t _t = + T _syn and cause an event at the time + 2T _syn + 2T _neu on the neuron output 33. The accumulation continues in the neuron acc 30 until the time tj _nd where its value of potential reaches the threshold V _t , ie t _nd = t _t + T _max - x. T _cod . An event is sent on the V-synapse 35 at the time tj _nd + T _neu and causes another event on the neuron output 33 at time t _out - t _end + T _Syn + 2T _neu - t _reca u + 2T _Syn + 2T _neu + T _m i _n + (1- x). T _C0C j.

[0ΐ> 98] Finally, the two events delivered by the output neuron 33 are separated by a time interval AT _0Ut = t% _ut - t _o ^x _ut = T _min + (1 - x). T _cod = / (l - x).

[8] 99] Note that the value x is stored in the acc cellon neuron upon receipt of the two input spikes, and immediately available to be read by activating the recall neuron 31.

[001.00] Since the standard weight w _e has been defined as the minimum excitation weight that must be put on a V-synapse to trigger a neuron since the reset state, it is noted that the processing circuit 18 of the figure 2 functions similarly if certain weights are chosen as follows: the V-synapse 22 has a weight w equal to or greater than w _e , the V-synapse 24 has a weight at least equal to w _e 12 and smaller than V _t , the first neuron 23 self-inhibits by a V-synapse 28 of weight -w, the excitatory V-synapse 32 has a weight equal to or greater than w _e and the excitatory V-synapse 35 has a weight equal to or greater than w _e . This remark extends to the following processing circuits.

A.2. Memory

[001.01] Figure 4 shows a processing circuit 40 constituting a memory.

This device 40 stores an analog value x encoded by a pair of input spikes supplied to an input neuron 21 with an interval m = f (x), using a current integration on the dynamics g _e in two neurons. cascade access 42, 44 to provide a non-inverting output with a pair of events separated by a time interval At _out = f (x) -

The memory circuit 40 has an input neuron 21 to receive the value to be stored, a read command input constituted by a recall neuron 48, a ready neuron 47 indicating from when a read command can be presented neuron recall 48, and a neuron output 50 to restore the stored value. All synapses of this memory circuit have the delay T _syn . The input neuron 21 belongs to a group of nodes similar to that described with reference to FIG. 2, with a first neuron 23 and a last neuron 25 to separate the two events produced with an interval of (jc) = T _m i _n + xT _cod by the 21 input neuron.

[88105] A ^ -synapse 41 goes from the first neuron 25 to the first acc 42 neuron, and has the weight ¼v _c . The acceleration neuron 42 thus starts an accumulation at time t _t = tf _n + 2 - T _syn + T _neu (FIG. 5). A ^ -synapse 43 goes from the neuron last 25 to the second neuron acc 44, and has the weight w _acc . The accelerator neuron 44 thus starts an accumulation at the time t ⁼ tn + 2- _syn + T _neu . At the exit of the accelerator neuron 42, another λ -synapse 45 of weight Waε goes to the accelerator neuron 44, and a V-synapse 46 of weight w _e goes to the ready neuron 47. Accumulation on the accelerator neuron 42 continues until the time = t _t + T _max where the potential of the acceleration neuron 42 reaches the threshold V _t , which causes the emission of a spike at time t _acc = + T _neu on the _e- synapse 45 (Figure 5). This spike stops the accumulation on the neuron acc 44 time = t _acc + T _syn = tf _n + 3. T _syn + 2- T-neu + T _ma x - The triggering of the acc 42 neuron also causes an event on the ready 47 neuron at time t ^ _eady = t _acc + T _syn + T _neu .

Î00107] At this point, the potential value stored in the neuron acc 44 is ~~ ^V ~ ■ (tend2 ~ ^ ₂ ) ⁼ V _t - (l ^- / W ^T sn T _neu \ ^ ^ keeps the value x Reading can then take place by activating the recall neuron 48, which takes place at the same time in Figure 5. [f) i) ï () 8] Activation of the recall neuron 48 causes a time event = trecaii + Tsyn + T _neu on the neuron output 50 via the V-synapse 49, and restart the accumulation process in the neuron acc 44 via the g _e -synapse 51 at time t _t2 = t-recaii + T _sy n - The accumulation continues in the neuron acc 44 until the time tj _nd2 where its potential value reaches the threshold V _t , ie tf _nd2 = t _t2 + f (x) - T _syn - T _neu . An event is emitted on the V-synapse 52 at the time t _acc2 = tj _nd2 + T _neu and causes another event on the neuron output 50 at time t _gUt = t _acc2 + T _syn + T _neu = + T _syn +

Tneu f (- * ^■ ) ^■

[88109] Finally, the two events delivered by the output neuron 50 are separated by a time interval AT _0Ut = t _gUt - = f (x). [88118] Note that the accelerator neuron 42 of FIG. 4 could be eliminated by configuring T _syn + delays on certain synapses. This may be useful for reducing the number of neurons, but may be difficult to implement with specific integrated circuits (ASICs) because of the lengthening of delays between neighboring neurons.

100111] It is further noted that the memory circuit 40 operates for any encoding of the magnitude x by a time interval between T _min and ^, without being limited to the form (11) above.

A3. Signed memory [88112] Fig. 6 shows a processing circuit 60 constituting a memory for a signed value, i.e., between -1 and +1. Its absolute value is coded by an interval At _in = f (\ x \) between two events which, if x≥ 0, are provided by the input neuron + 61 and then restored by the neuron output + 81 and, if x <0, are provided by the neuron input- 62 then restored by the neuron output- 82. All synapses of this memory circuit have the delay T _syn .

[001.13] The signed memory circuit 60 is based on a memory circuit 40 of the type shown in Figures 4A-B. The input + and input-61 neurons are respectively connected to the input neuron 21 of the circuit 40 by excitatory V-synapses 63, 64 of weight w _e . Thus, that of the two neurons 61, 62 which receives the two spikes representing \ x \ activates twice the input neuron 21 of the circuit 40, so that the time interval / (bel) will be restored on the output neuron 50 of the circuit 40.

[881 14] In addition, neurons 61, 62 are respectively connected to ready + and ready-65 neurons 66 by excitatory V-synapses 67, 68 of weight w _e / 4. The signed memory circuit has a recall neuron 70 connected to the ready + and ready-65 neurons 66 by respective excitatory V-synapses 71, 72 of weight w _e 12. Each of the ready + and ready-65 neurons 66 is connected to the recall neuron 48 of the circuit 40 by respective excitatory V-synapses 73, 74 of weight w _e . An inhibitory V-synapse 75 of weight w, / 2 goes from the ready neuron + 65 to the ready-66 neuron, and conversely a 76-weight w / 2 inhibitory V-synapse goes from the ready-66 neuron to the ready neuron + 65. The neuron ready + 65 is connected to the neuron output- 82 of the memory circuit signed by a weight inhibitory V-synapse 77 wi. The ready-66 neuron is connected to the output neuron 81 of the memory circuit signed by an inhibitory V-synapse 78 of weight 2wi.

The output neuron 50 of the circuit 40 is connected to the neurons output + and output-81, 82 by respective excitatory V-synapses 79, 80 of weight w _e . 100116] The output of the signed memory circuit 60 comprises a ready neuron 84 which is the receiving node of an excitatory V-synapse 85 of weight w _e from the ready neuron 47 of the memory circuit 40.

FIG. 7 shows the behavior of the neurons of the signed memory circuit 60 (a) in the case of a positive input and (b) in the case of a negative input. [001 8] The appearance of the two events at times tf _n and tf _n = tf _n + f Çx) on one of the neurons 61, 62 makes the potential of the ready + 65 or ready-66 neuron rise in two stages. the value V _t / 2. Meanwhile, the memory circuit 40 has its acceleration neuron 44 which is loaded at the value V _t . (l- ^{Tsyn Tneu} _el - _sound ready urone 47 produces an event in time as described above [00119] Once the neuron ready 47 produced its event, the recall neuron 70 can be activated to read the signed data,. which takes place at the time _shown in Fig. 7.

The activation of the recall neuron 70 triggers the ready + 65 or ready-66 neuron via the V-synapse 70 or 71, and this trigger causes the other ready-66 or ready + 65 neuron to zero via the V-synapse. 75 or 76. The event delivered by the ready + 65 or ready-66 neuron inhibits the output-82 or output + 81 neuron via V-synapse 77 or 78, bringing its potential to -2V _t .

[0012] The event delivered by the ready + 65 or ready-66 neuron at the time t _ign is supplied to via the V-synapse 73 or 74. This causes the emission of a pair of spikes separated by an interval of time equal to (| |) by the neuron output 50 of the circuit 40. This pair of spikes communicated to the neurons output + and output- 81, 82 via the V-synapses 79, 80 triggers twice, at times + (| |), that of the neurons output + and output- 81, 82 which corresponds to the sign of the input data x, and resets the potential value of the other neuron 81, 82 to zero. [88122] Note that the signed memory circuit 60 shown in FIG. 6 is not optimized in terms of the number of neurons, since one can:

• dispense with the input neuron 21 of the memory circuit 40, by sending the V-synapses 63 and 64 directly to the first neuron 23 of the circuit 40 shown in FIG. 4 (in place of the V-synapse 22), and adding excitatory V-synapses of weight wJ2 of the input + and input- 61, 62 neurons to the neuron last 25 (instead of the V-synapse 24);

• dispense with the output neuron 50 of the memory circuit 40, sending the ^ -synapse 52 directly to the neurons output + and output- 81, 82 (instead of V-synapses 79, 80); and

• dispense with the recall neuron 48 of the memory circuit 40, sending the V-synapses 73 and 74 directly to the output + and output-81, 82 neurons (instead of the V-synapse 49), and adding excitatory synapses of weight w _acc from the ready + and ready-65 neurons to the access neuron 44 of the circuit 40 (in place of the g _e -synapse 51).

A.4. synchronizer

FIG. 8 shows a processing circuit 90 for synchronizing the received signals to an N number of inputs (N> 2). All the synapses of this synchronization circuit have the delay T _syn .

[0024] Each signal codes a value ¾ for k = 0, 1, N-1 and is in the form of a pair of spikes occurring at times tf _nk and tf _nk = tf _nk + At _k with Atk = fixk ) G XTmm, These signals are restored at the output of the circuit 90 in a synchronized manner, that is to say that each signal coding a value ¾ is found in the form of a pair of spikes occurring at times + At _k with touto ⁼ touti = ·· · = allw-i 'as shown in Figure 9 in a case where N = 2.

The circuit 90 shown in FIG. 8 comprises N input neurons 91 ₀ ,..., 9Ly-i and N output neurons 92 ₀ , 92JV-I. Each input neuron 9 is the transmitting node of a V-synapse 93 _k of weight w _e whose receiving node is the input neuron 21 _¾ of a respective memory circuit 40 _¾ . The output neuron 50 ^ of each memory circuit 40 _¾ is the node emitter of a V-synapse 9 _k of weight w _e whose receiving node is the output neuron 92 _k of the synchronization circuit 90.

The synchronization circuit 90 comprises a sync neuron 95 which is the receiving node of N V-synapses excitatory 96o, 96JV-I of weight w N whose transmitting nodes are respectively the ready 47o, 47JV-I neurons of the circuits. memory 40o, 40jv-i. The circuit 90 further comprises excitatory V-synapses 97o, 97JV-I of weight w _e having the sync neuron 95 for transmitter node and, respectively, the recall 48o, ..., 48JV-I neuron memory circuits 40o, .. ., 40JV-I for receiving nodes.

The sync neuron 95 receives the events produced by the ready 47 ₀ , 47JV-I neurons as the N input signals are loaded into the memory circuits 40o, 40JV-I, ie at the times t _dy0 ^, t ^ _dyl in Figure 9. When the last of these N events has been received, the sync neuron 95 outputs an event T _syn later, that is to say at the time 9. This triggers, via the synapses 97o, 97JV-I and the synapses 49 of the memory circuits 40o, 40JV-I, the transmission of a first synchronized spike (touto ^{= ■} " ⁼ allN-i ^on each neuron output 92o, 92JV-I. Then each memory circuit _40k produces its respective second spike at time t _gUtk.

[0) 128] The presentation of the synchronization circuit with reference to Figure 8 is given to facilitate the explanation, but note that several simplifications are possible by removing some neurons. For example, the input neurons 91o, 91JV-I and output 92 ₀ , 92JV-I are optional, since the inputs can be provided directly by the input neurons 21o, 21JV-I of the memory circuits 40o, 40JV-I and the outputs directly by the neurons output 50o, 50JV-I memory circuits 40o, 40JV-I. The V-synapses 46 of the 40o, 40JV-I memory circuits can go directly to the sync neuron 95, without passing through a ready 47 ₀ , 47JV-I neuron. The synapses 97 ₀ , 97JV-I can directly attack the output 50o, 50JV-I neurons of the memory circuits (thus replacing their synapses 49), and the sync neuron 95 can also constitute the transmitting node of the synopses 51 memory 40o, 40JV-I to control the restart of accumulation in acc 44 neurons (FIGS. 4 and 5).

[0) 129] Moreover, it is possible to get only one event at any time ⁼ t ⁼ t outa-outi = · · · = toutw-i ^'as ¾ of all ^eu first event the pairs forming the synchronized output signals. The sync neuron 95 then directly the emission of the first spike on a particular output of the circuit (which can be one of the output 92 ₀ neurons, ^or a specific neuron), then the second spike of each pair by reactivating the neurons acc 44 memory circuits 40ο, ..., 40JV-I via a ^ -synapse. In other words, the sync neuron 95 plays the role of recall neurons 48 of the different memory circuits.

Such a synchronizer circuit 98 is illustrated in the case where N = 2 in FIG. 10 where, again, all the synapses have the delay T _syn . The sync neuron 95 is excited by two V-synapses 46 of weight wJ2 coming directly from the neurons acc 42 of the two memory circuits, and it is the emitting node of the g _e- synapses 51 to restart the accumulation in the neurons. In this example, a specific neuron 99, denoted Output ref, delivers the first event of each of the two output pairs at the time all ⁼ tlync + T _syn , in response to an excitation received from the sync neuron 95 via the V-synapse 97 The role of this neuron output ref 99 could, alternatively, be held by one of the two output neurons 92 ₀ , 92 _\ .

[0031] It should be noted that, in the example of FIG. 10, the two events encoding the value of an output quantity of the circuit 98 are produced by two different neurons (for example the neurons 99 and 92 _\ for the magnitude x _\ ).

More generally, in the context of the present invention, it is not necessary for the two events of a pair representing the value of a quantity to come from a single node (in the case of a magnitude of output) or be received by a single node (in the case of an input quantity).

B. Logical operations

B.l. Minimum

FIG. 11 shows a processing circuit 100 which calculates the minimum between two values received synchronously on two input nodes 101, 102 and delivers this minimum on an output node 103.

[80134] In addition to the input neurons 101, 102 and the output neuron 103, this circuit 100 comprises two 'smaller' neurons 104, 105. An excitatory V-synapse 106, of weight w 2, ranging from neuron input 101 to smaller neuron 104. An excitatory V-synapse 107, weight wJ2, ranges from neuron input 102 to neuron smaller 105. An excitatory V-synapse 108, weight w 2, goes from neuron input 101 to neuron output 103. An excitable V-synapse 109, of weight w 2, ranges from the input neuron 102 to the output neuron 103. An excitatory V-synapse 110, of weight wJ2, ranges from the smaller neuron 104 to the output neuron 103. A V-synapse exciter 111, of weight wJ2, goes from neuron smaller 105 to neuron output 103. An inhibitory V-synapse 112, of weight Wi / 2, goes from neuron smaller 104 to neuron smaller 105. An inhibitory V-synapse 113, of weight Wi / 2, going from the smaller neuron 105 to the smaller neuron 104. An inhibitory V-synapse 114, of weight w goes from the smaller neuron 104 to the input neuron 102. An inhibitory V-synapse 115, of weight w goes from the neuron smaller 105 to the neuron input 101. All synapses 106-115 shown in Fig. 11 are associated with a delay T _syn , except for synapses 108, 109 for which the delay is 2.T _syn + T _neu .

[00135] The transmission of the first spike on each input neuron 101, 102 at the time tfni tln ⁼ ₂ (Fig ^ure 12) causes each of smaller neurons 104, 105 to a potential value V / 2 at time tf _nl + T _syn , and triggers a first event on the neuron output 103 at the time = tf _nl + 2. T _syn + 2. T _neu . The emission of the second spike on the smaller value neuron input, namely the neuron 101 at the time tf _nl = tf _nl + At _x in the example of FIG. 12, brings one of the smaller neurons to the voltage threshold V _t , namely the neuron 104 in this example, which causes an event at time t | _maHerl = tfni + T _S yn + T _neu at the output of this neuron 104. As a result, the synapse 114 inhibits the other input neuron 102, which will not produce its second spike at time tf _n2 = tf _n2 + At ₂ , and the synapse 112 inhibits the other smaller neuron 105 whose potential is reset. Triggering the smaller neuron 104 also causes the second triggering of the output neuron 103 at time t _gUtl = t ^ _maUerl + T _syn + T _neu = tf _nl + 2. T _syn + 2. T _neu . Finally, the neuron output 103 restores well, between the events it delivers, the minimum time interval t¾ _ut - = tf _nl - tf _nl = At _x between the events of the two pairs produced by the input neurons 101, 102. This minimum is available at the output of the circuit 100 upon receipt of the second event of the pair which represents it as input. The calculation circuit of minimum 100 of FIG. 11 functions as long as the function / such that At = f (x) is an increasing function. B.2. Maximum

FIG. 13 shows a processing circuit 120 which calculates the maximum between two values received synchronously on two input nodes 121, 122 and delivers this maximum on an output node 123. 100139] In addition to the input neurons 121 , 122 and the neuron output 123, this circuit 120 comprises two 'larger' neurons 124, 125. An excitable V-synapse 126, weight w _e / 2, goes from the input neuron 121 to the neuron larger 124. An excitatory V-synapse 127, weight w _e / 2, goes from the input neuron 122 to the neuron larger 125. An excitatory V-synapse 128, weight w _e / 2, goes from the input neuron 121 to the output neuron 123. An excitatory V-synapse 129, weight w _e / 2, goes from the neuron input 122 to the neuron output 123. An inhibitory V-synapse 132, weight w goes from the neuron larger 124 to the neuron larger 125. An inhibitory V-synapse 133, weight w goes from the neuron larger 125 to neuron larger 124. All synapses shown in Fig. 13 are associated with a delay T _syn .

1X 0140] The first spikes emitted in a synchronized manner (tf _nl = tf _n2 ) by the input neurons 121, 122 bring the larger neurons 124, 125 to a value of potential V / 2 at the time tf _nl + T _syn , and trigger a first event on the neuron output 123 at time all ⁼ tf _nl + T _syn + T _neu , (figure 14). The emission of the second spike on the neuron input neuron with the smallest value, namely the neuron 121 at the time tf _nl = tf _nl + At _x in the example of FIG. 14, causes one of the neurons to be larger than the voltage threshold V, namely the neuron 124 in this example, which causes an event at time tf _arger2 = tf _nl + T _S yn + T _neu at the output of this neuron 124. As a result, the synapse 132 inhibits the other neuron larger 125 whose potential changes to the value -V 2. When the second spike is emitted by the other neuron input 122 at the time tf _n2 = tf _n2 + At (with At ₂ > At), the neuron potential greater 125 is reset to zero via the synapse 127, and the output neuron 123 is triggered via the synapse 129 at time t% _ut = tf _n2 + T _syn + T _neu .

[00141] Finally, the neuron output 123 restores well, between the events it delivers, the maximum time interval. = tf _n2 - tf _n2 = At ₂ between the events of the two pairs produced by the input neurons 121, 122. This maximum is available at the output of the circuit 120 upon receipt of the second event of the pair which represents it as input. [88142] The maximum calculation circuit 120 of FIG. 13 functions as long as the function / such that At = f (x) is an increasing function.

C. Linear operations

Cl. Subtraction [88143] Fig. 15 shows a subtraction circuit 140 which calculates the difference between two values xj, X2 received synchronously on two input nodes 141, 142 and outputs the result xi - ¾ on an output node 143 if it is positive and on another output node 144 if it is negative. We assume here that the function / such that Ati = f (xi) and At ₂ = / fe) is a linear function, as it is the case with the form (11). In addition to the input neurons 141, 142 and the output + 143 and output-144 neurons, the subtraction circuit 140 comprises two sync neurons 145, 146 and two 'inb' neurons 147, 148. An excitatory V-synapse 150, of weight wJ2, goes from the input neuron 141 to the sync neuron 145. An excitatory V-synapse 151, weight wJ2, goes from the input neuron 142 to the sync neuron 146. Three excitatory V-synapses 152, 153, 154, each weight w _e range from neuron sync 145 to output neuron + 143, neuron output-144 and neuron inb 147, respectively. Three excitatory V-synapses 155, 156, 157, each weight w _e , range from sync neuron 146 to output-144 neuron, output neuron + 143 and neuron 148, respectively. An inhibitory V-synapse 158, of w weight, ranges from neuron sync 145 to neuron 148. Inhibitory V-synapse 159, weight w goes from neuron sync 146 to neuron 147. Excitatory V-synapse 160, weight wJ2 , goes from the neuron output + 143 to the neuron inb 148. An excitatory V-synapse 161, of weight wJ2, goes from the neuron output-144 to the neuron inb 147. An inhibitory V-synapse 162, of weight 2w goes from the neuron inb 147 to the neuron output + 143. An inhibitory V-synapse 163, weight 2w goes from the neuron inb 163 to the neuron output-144. The synapses 150, 151, 154 and 157-163 are associated with a delay of T _syn . Synapses 152 and 155 are associated with a delay of T _min + 3.T _syn + 2.T _neu . Synapses 153 and 156 are associated with a delay of 3.T _syn + 2.T _neu -

[8 145] The operation of the subtraction circuit 140 according to FIG. 15 is illustrated by FIG. 16 in the case where the result xi - x ₂ is positive. Things happen symmetrically if the result is negative. [00Ï46] The first spikes transmitted synchronously (tf tf _nl = _n2) by the input neurons 141, 142 cause the sync neurons 145, 146 to the potential value V _t / 2 at time tf _nl + T _syn. The emission of the second spike on the input neuron providing the smallest value, namely neuron 142 at time tf _n2 = tf _n2 + At ₂ in the example of FIG. 16 where At <At _x , brings one of the sync neurons at the threshold voltage V _t , namely the 146 neuron in this example, resulting in a time event = tf _n2 + T _syn + T _neu at the output of this neuron 146. Therefore:

The synapse 159 inhibits the inb 147 neuron whose potential passes to the value -V _t at time t _S y _nc2 + T _syn -ti _n2 + 2. T _syn + T _neu ,

The synapse 157 excites the neuron 148 that delivers an event at time ii> 2 = ^t ync2 + ^T syn + T _neu = tf _n2 + 2. T _syn + 2. T _neu , which event in turn inhibits, via the synapse 163, the neuron output- 144 whose potential passes to the value -2V _t at time tf _n2 + 3. T _syn + 2. T _neu ;

The synapse 155 then re-excites the output-144 neuron whose potential passes to the value -V, at time tf _n2 + T _min + 4. T _syn + 3. T _neu ;

• the synapse 156 excites the neuron output + 143 which delivers an event at time all ⁼ tsync2 ^ sn 3- T _neu = tj _n2 + 4. T _syn + 4. T _neu , which event in turn excites the neuron inb 148 whose potential, reset after the previous event transmitted at time tf _nb2 , passes to the value V _t / 2 at the time + T _syn + T _neu - ti _n2 + 5. T _syn + 5. T _neu .

[00147] Next, the emission of the second spike on the other input neuron 141 at time tfm ⁼ tfni + - ^ ι causes the other sync neuron 145 to the threshold voltage V _t , which causes a time event. = tf _nl + T _syn + T _neu at the output of this neuron 145. Therefore:

• the synapse 158 inhibits the neuron 148 whose potential passes to the value -VJ2 at time t _synci + T _syn -ti _ni + 2. T _syn + T _neu ,

The synapse 154 excites the inb 147 neuron which resets its membrane potential;

• the synapse 152 excites the neuron output + 143 which delivers an event at time all ~ t _synci + _m i _n + 3. T _syn + 3. T _neu- ti _ni + T _m i _n + 4. T _syn + 4. T _neu , which one This event in turn excites the neuron 148 whose potential is reset to zero at the time t + T _S y _n + T _neu- ti _ni + T _m i _n + 5. T _S y _n + 5. T _neu .

• the synapse 153 excites the output-144 neuron whose potential is reset to zero at time t _{S nc} i + 3. T _S y _n + 2. T _neu t ^ ni 4- T _S y _n + 3. ^ neu -

[0048] The two excitatory events received by the output-144 neuron, at times ^f i¾ ₂ + ^T min + 4. T _syn + 3. T _neu and tf _nl + 4. r _syn + 3. T _neu are much later than the inhibitory event received at time tf _n2 + 3. T _syn + 2. T _neu . As a result, this neuron 144 emits no event when At ₂ <At _\ , so that the sign of the result is properly signaled.

[01) 149] Finally, the neuron output + 143 delivers two events having between them a time interval At _out between the events of the two pairs produced by the input neurons 141, 142, with: any ~ (-in T min 4- Tsyn 4- T _neu ) - (tj _n2 + 4. T _S y _n + 4. T _neu )

= T _min + (x _l - x ₂ ). T _cod (15)

[0 (U5ft) We obtain, well on the neuron output of a good sign at the output of the subtractor circuit 140, two events having between them the time interval At _out = f (x _\ - ¾) · This result is available as output of the circuit upon receipt of the second event of the input pair having the largest absolute value. [8) 151] When two equal values are presented to it at the input, the subtractor circuit 140 shown in Fig. 15 activates the two parallel paths and the result is delivered on the two neurons output + 143 and output-144, the neurons inb 147, 148 having no time to select a winning path. To avoid this, it is possible to add to the subtractor circuit a zero neuron 171 and fast V-synapses 172-178 to form a subtractor circuit 170 according to FIG. 17.

In FIG. 17, the numerical references of the neurons and synapses arranged in the same manner as in FIG. 15 are not reported. Zero neuron 171 is the receiving node of two excitatory V-synapses 172, 173 of weight wJ2 and of delay T _neu , one from the neuron sync 145 and the other from the sync neuron 146. It is on the other hand the receptor node of two inhibitory V-synapses 174, 175 of weight wJ2 and of delay 2.T _neu , one coming from the sync neuron 145 and the other of the sync neuron 146. The zero neuron 171 is self-excited by a V-synapse 176 of weight w _e and delay T _neu . On the other hand, it is the transmitting node of two inhibitory V-synapses of delay T _neu , one 177 of weight Wi directed towards the neuron inb 148 and the other 178 of weight directed to the neuron output- 144.

[C 53] The zero neuron 171 acts as a coincidence detector between the events delivered by the sync neurons 145, 146. Since these two neurons only deliver events at the time of the second coding spike of their associated input, detecting this temporal coincidence is equivalent to detecting the equality of the two input values, provided that they are correctly synchronized. The zero neuron 171 produces an event only if it receives two events separated by a time interval less than T _neu from the sync neurons 145, 146. In this case, it directly inhibits the output-144 neuron via the synapse 178 , and disables the inb 148 neuron via the synapse 177.

Consequently, two equal input values supplied to the subtractor circuit of FIG. 17 give rise to two events separated by a time interval equal to T _min , that is to say coding a zero difference, at the output neuron output + 143, and no event on the output-144 neuron. If the input values are not equal, the zero neuron 171 is not activated and the subtractor operates in the same manner as that of FIG. 15 .

C.2. Cumulum (MMSS) Figure 18 shows a circuit 160 for summing positive input quantities with weights, whose purpose is to load into a neuron acc 184 a potential value related to a weighted sum: s = ΣΣ a _k . x _k (16) where OQ, <¾, .. ·, OCN-I are positive or zero weighting coefficients and the input quantities χο, χι, XN-Ï are positive or zero.

[88156] For each input value ¾ (0 <k <N), the circuit 180 comprises an input neuron 181 _k and input-182 _k each forming part of a respective group of neurons arranged in the same way as in group 20 described above with reference to FIG.

[88157] The outgoing connections of the first and last neurons of these N groups of neurons 20 are configured according to the coefficients <¾ of the weighted sum to be calculated.

[88158] The neuron first connected to the input neuron 18 (0 <k <N) is the emitter node of a stimulating _e- synapse 182 ^ of weight <¾.¼v _c and delay T _min + T _syn . The last neuron connected to the input neuron 18 is the node emitting an inhibitory γ-synapse 183 of weight - Xk Waœ and of delay T _syn .

The neuron acc 184 accumulates the terms <¾.¾. Thus, for each entry k, the accelerator neuron 187 is the receptor node of the excitatory γ-synapse 182 and the inhibitory γ-synapse 183.

[0060] The circuit 180 further comprises a sync neuron 185 which is the receiving node of N V-synapses, each wJN weight and delay T _syn , respectively from the last neurons connected to N input neuron 18 (0 <k < NOT). The sync neuron 185 is the emitting node of an excitatory _e- synapse 186 of weight w _acc and delay T _syn , whose receiving node is the accession neuron 184.

[0061] For each input having two spikes separated from At _k = T _m i _n + Xk-T _co d on the input neuron 18, the acc echon neuron 184 integrates the quantity CCk-V _t IT _max over a period of time.

Once all the second spikes of the input signals have been received, the sync neuron 185 is triggered and excites the accelerated neuron via the ε-synapse 186. The potential of the accelerator neuron 184 continues to grow for a period of time. residual time equal to Tmax ^~ Σfe = ok - ^x k- T _œ d - At this point, the threshold V _t is reached by the acceleration neuron 184 which triggers an event.

The delay of this event compared to that delivered by the sync neuron 185 is T _max - a _k . x _k . _Cod = T / (l -Σ "^ ¹ a _k x _k.) = /. (L - s) s The weighted sum is made available by the circuit 180 in its inverted form (1 - s).

[8) 164] The circuit 180 operates in the manner which has just been described on condition that r is _cod .Σ "-To a _fe. X _fe <T _max. One can normalize the coefficients <¾ for this condition is fulfilled for all possible values of ¾, that is, so that

C .3. Weighted summation

[08165] A weighted summation circuit 190 may have the structure shown in FIG. 19.

[88166] To obtain the representation of the weighted sum s according to (16), a weighted cumulative circuit 180 of the type described with reference to FIG. 18 is associated with another acc 188 neuron and a neuron output 189.

[0] 167] The accelerator neuron 188 is the receiving node of an excitatory ^ -synapse 191 of weight Waoe and delay T _syn , and the emitter node of an excitatory V-synapse 192 of weight w _e and delay T _min + T _syn . The output neuron 189 is also the receiving node of an excitatory V-synapse 193 of weight w _e and of delay T _syn .

The linear dynamic accumulation starts on the accelerated neuron 188 at the same time as it restarts on the acceleration neuron 184 of the circuit 180, the two acceleration neurons 184, 188 being excited on the nonsynapses 186, 191 by the same event coming from the sync neuron 185. Their residual accumulation durations up to the threshold V _t are respectively T _max -Σ "= o ^a k- ^x k-T _C od ^and Τ ^. the synapse 192 has a relative delay of T _min , the two events triggered on the output neuron 189 have between them the time interval T _min + _k, x _k, T _cod = / (s).

The expected weighted sum is well represented at the output of the circuit 190. When N = 2 and <% = <¾ = 1/2, this circuit 190 is reduced to a simple adder circuit, with a scale factor 1 / 2 to avoid overflows in the neuron acc 184.

C.4. Linear combination

[08178] The more general case of linear combination is also expressed by equation (16) above, but the coefficients <¾ can be positive or negative, as can the input quantities ¾. Without loss of generality, the input coefficients and quantities are ordered so that the coefficients <%, <¾, <¾ _i _ ₁ are positive or zero and the coefficients a _{M +} 1, X _M + 2, are negative (N≥2, M≥0, N - M≥0). [88171] To take into account the positive or negative values, the linear combination calculation circuit 200 shown in FIG. 20 comprises two accumulation circuits 180A, 180B of the type of that described with reference to FIG. 18.

[88172] The input neurons 18 of the cumulative circuit 180A are respectively associated with the coefficients <¾ for 0 <k <M and with the inverted coefficients - <¾ for M <k <N. These input neurons 18 for 0 <k <M receive a pair of spikes representing ¾ when ¾> 0 and therefore form input + neurons for these quantities x ₀ , XM- \ - The input 18 neurons of the circuit 180A for M <k <N receive a pair of spikes representing ¾ when ¾ <0 and therefore form input-type neurons for these XM variables, · · ·, XN-I -

100173] The input 18 neurons of the weighted cumulative circuit 180B are respectively associated with the inverted coefficients - <¾ for 0 <k <M and with the coefficients <¾ for M <k <N. These input neurons 18 for 0 <k <M receive a pair of spikes representing ¾ when ¾ <0 and thus form input-type neurons for these magnitudes x ₀ , XM- \ - The input 18 neurons of the circuit 180B for M <k <N receive a pair of spikes representing ¾ when ¾> 0 and therefore form input + neurons for these XM variables, · · ·, XN-I -

The two aggregation circuits 180A, 180B share their sync neuron 185 which is thus the receiving node of 2N V-synapses, each of weights w _e IN and of delay T _syn , from the neurons last coupled to the 2N neurons input 18. The sync neuron 185 of the linear combination calculating circuit 200 is therefore triggered once the N input variables x ₀ ,..., ¾ν- _ΐ , positive or negative, have been received on the neurons l & lk.

flows between the events respectively delivered by the sync neuron 185 and the acceleration neuron 184 of the circuit 180A.

[08176] A time AT _B = T _max

flows between the events respectively delivered by the sync neuron 185 and the acceleration neuron 184 of the circuit 180B.

A subtractor circuit 170, which may be of the type shown in FIG. 17, is then used to combine the ATA and ATB time slots to produce the representation of \ s \ = Σ _akJCk≥0 \ a _k . x _k \ -Σ _{akJCk <0} \ a _k . x _k \ on an output indicative of the sign of s. The linear combination calculation circuit 200 of FIG. 20 comprises for this purpose two excitatory V-synapses 198, 199, of weight w _e and of delay T _min + T _syn , directed towards the input neurons 141, 142 of the subtraction circuit 170. Moreover, an excitatory V-synapse 201 of weight w _e and delay T _syn goes from the neuron acc 184 of the circuit 180A to the input neuron 141 of the subtractor circuit 170. An excitatory V-synapse 202 of weight w _e and delay T _syn goes from the neuron acc 184 of the circuit 180B to the other neuron input 142 of the subtractor circuit 170.

[88178] The output-144 and output + 143 neurons of the subtractor circuit 170 are respectively connected, via exciter V-synapses 205, 206 of weight w _e and of delay T _syn , to two other neurons output + 203 and output-204 which constitute the outputs of the linear combination calculation circuit 200.

[08179] Which of these two neurons is triggered indicates the sign of the result s of the linear combination. It delivers a pair of events separated by the time interval At _out = T _min + AT _A - AT _B = -

Î00180] The availability of this result is indicated externally by a 'start' 207 neuron receiving two excitatory V-synapses 208, 209, of weight w _e and of delay T _syn , from the neurons output + 143 and output-144 of the subtractor circuit 170. The start neuron 207 self-inhibits by means of a V-synapse 210, weight Wi and delay T _syn . The start 204 neuron delivers a spike simultaneously to the first spike of the output + 203 or output-204 neuron activated.

[08181] It can normalize the coefficients <¾ for the Σa terms _k .x ≥o _k k ^x k \ - T od _C <Tmax a _k . x _k \. T _cod <T _max are fulfilled for all possible values of ¾, that is, so that "" = ο Ι < _¾ 1 <^ ² ^, so that the circuit of

TCOD

linear combination calculation 200 operates as described above. The normalization factor must be taken into account in the result.

D. Non-linear operations

D. l. Logarithm FIG. 21 shows a circuit 210 for calculating the natural logarithm of a number xe] 0, 1] of which a coded representation is produced by an input neuron 211 in the form of two events occurring at times tf _n and tf _n. = tf _n + At (figure 22) with At = f (x) = T _min + x _cod . [001.83] The input neuron 211 belongs to a group of nodes 20 similar to that described with reference to FIG. 2. The first neuron 213 of this group 20 is the emitting node of a stimulating _e- synapse 212 of weight w _acc and delay T _m i _n + T _syn , while the neuron last 215 is the node emitting an inhibitory ^ -synapse 214 of weight-w _acc and delay T _syn . Both ^ -synapses 212, 214 have the same access neuron 216 as the receiving node. From neuron last 215 to neuron acc 216, there is also a ^ / - synapse 217 of weight 9mu.it ⁼ V _f ~ ^and of delay T _syn , and a gay-synapse 218 of weight 1 and of delay T _syn .

The circuit 210 further comprises a neuron output 220 which is the receiving node of an excitatory V-synapse 221 of weight w _e and of delay 2.T _syn from the neuron last 215, and a V-synapse exciter 222 of weight w _e and delay T _m i _n + T _syn from the neuron acc 216.

[0 185] The operation of the log computation circuit 210 according to FIG. 21 is illustrated by FIG. 22.

The emission of the first spike at time tf _n at the level of the input neuron 211 triggers an event at the output of the first neuron 213 at the time tj _irst = tf _n + T _syn + T _neu . The first neuron 213 starts accumulation by the neuron acc 216 at time t = t} _n + T _min + 2. T _syn + T _neu via g _e -synapse 212.

[80187] The emission of the second spike at time tf _n = tf _n + T _min + x. T _cod at the level of the input neuron 211 causes the neuron last 215 to deliver an event at time t-iast ⁼ tfn + T _S yn + T _neu . This event carried by the _e -synapse 214 stops the accumulation made by the neuron acc 216 time = tf _ast + T _syn = + x. T _cod . At this time, the potential value V _t .x is stored in the acc 216 neuron.

Through synapses 217 and 218, the last neuron 215 also activates the exponential dynamics on the neuron acc 216 at the same time.

And 217 g _ate -synapse 218. It should be noted that alternatively, the event transported by ^ -synapse 217 could also happen later to the acceleration neuron 216 if it is desired to store therein the potential value V _t .x while other operations occur in the device.

[88189] After activation by the synapses 217 and 218, the g / component of the acc 222 neuron evolves according to: t ^{~ t} enti

g _f (t) = V _t . ^T. e V (17) and its membrane potential according to:

Î0Û190] This potential V (t) reaches the threshold V _t and causes an event on the V-synapse 222 at the time t _acc = - r _f . log (x).

[1) 8191] A first event is triggered on the neuron output 220 because of the V-synapse 221 at time t _o ^x _ut = tl _ast + 2T _syn + T _neu = + T _syn + T _neu . The second event triggered by synapse 222 occurs at time t% _ut = t _acc + T _min + T _syn +

^ neu ^~ all Tmin ^~ T ^. log (x).

[1) 8192] Finally, the two events delivered by the output neuron 220 are separated by a time interval AT _0Ut = t% _ut - t _o ^x _ut = T _min - r _f . log (x) = f (- ^ - log (x)).

V ^T cod

[88193] The representation of a number proportional to the natural logarithm log (jc) of the input value x is well obtained. As 0 <x <1, the logarithm log (jc) is negative.

¹ cod

[001] If A = e ^T f is denoted, the circuit 210 of FIG. 21 delivers the representation of log _A c) when it receives the representation of a real number x such that A <x <1, where log _A (.) Denotes the basic logarithmic operation A. Assuming that, in the form (11), the time interval between the two events delivered by the output neuron 220 may exceed,, the circuit 210 delivers the representation of \ Ο§Α (Χ) for any number x such that 0 <x <1.

D.2. exponential FIG. 23 shows an exponential calculating circuit 230 of a number x G [0, 1], a coded representation of which is produced by an input neuron 231 in the form of two events occurring at times tf _n and tf _n = tf _n + At (figure 24) with At = f (x) = T _min + x _cod .

The input neuron 231 belongs to a group of nodes 20 similar to that described with reference to FIG. 2. The first neuron 233 of this group 20 is the node emitting a n -synapse 232 of weight g _mu i _t and of delay T _min + T _syn , as well as of an excitatory gay-synapse 234 of weight 1 and of delay T _m i _n + T _syn . The group 235 neuron last 235 is the node emitting an inhibitory gay-synapse 236 of weight -1 and delay T _syn , as well as an excitatory _e- synapse 237 of weight w _acc and of delay T _syn . Synapses have the same acc 238 neuron for receiving node.

The circuit 230 further comprises a neuron output 240 which is the receiving node of an excitatory V-synapse 241 of weight w _e and of delay 2.T _syn from the neuron last 235, and a V-synapse exciter 242 weight w _e and delay T _min + T _syn from the neuron acc 238.

[88198] The operation of the exponential calculation circuit 230 according to FIG. 23 is illustrated in FIG. 24.

[80199] The emission of the first spike at time tf _n at the level of the input neuron 231 triggers an event at the output of the first neuron 233 at the time tj _irst = tf _n + T _syn + T _neu . The neuron 233 first starts an exponential dynamic storage on the access neuron at time = 238 tf _n + T _min + T + T 2 _syn _neu via the ^ / - synapse 232 and 234 g _ate -synapse.

[08208] The gf component of the acc 238 neuron then evolves according to:

and its membrane potential according to:

(20) emission of the second spike at time tf _n = tf _n + T _min + x. T _cod at the neuron input level 231 causes the neuron last 235 to deliver an event at time t _iast = t ifnn + ^~ + TT ¹ _s y _y nn + T _neu . This event carried by the gay-synapse 236 stops the accumulation with exponential dynamics carried out by the neuron acc 238 at the time = tf _ast + T _syn = t _t + x. T _cod . At this time, the potential value V _t . (L - A ^x ) is stored in the neuron acc

_Σcod_

238, where, as previously, A = e ^T f. Via the _e- synapse 237, the last 235 neuron further activates the linear dynamics of weight w _acc on the accelerator neuron 238 at the same time

The membrane potential of neuron 238 then evolves according to:

V (t) = V _t . (l - A ^x + - ^t ^ (21)

V 'cod'

100203] This potential V (t) reaches the threshold V _t and causes an event on V-synapse 222 at time t _acc = + A ^x. T _cod .

[8 (1204) A first event is triggered on the output neuron 240 because of the

V-synapse 241 at time t _o ^x _ut = tl _ast + 2T _syn + T _neu = + T _syn + T _neu . The second event triggered by synapse 242 occurs at time t = _ut _acc + T _min + T _syn +

T ¹ neu - f ^L o ¹ ut A ^~ - T ¹ mi ■ n A ^~ - A ^x · T ¹ cod, -

[0D20S] Finally, the two events delivered by the neuron output 240 are separated by a time interval of AT _0Ut = t% _ut - t _ut = T _min + A ^x . T _cod = f (A ^x ).

The circuit 230 of FIG. 23 thus delivers the representation of A ^x when it receives the representation of a number x between 0 and 1. This circuit can admit input values x greater than 1 (At> Τ ^) and still deliver the representation of A ^x on its output neuron 240.

[0] 207] The circuit 230 of FIG. 23 performs the inversion of the operation performed by the circuit 210 of FIG. 21. [00208] It is possible to take advantage of this to implement various non-linear calculations using simple operations between log computation and exponential computation circuits. For example, the sum of two logarithms allows to implement a multiplication, their subtraction allows to implement a division, the sum of n times the logarithm allows to raise a number x to an integer power n, and so on.

D.3. Multiplication

[00209] FIG. 25 shows a multiplier circuit 250 which calculates the product of two values x ₁ , x ₂ , coded representations of which are respectively produced by two input neurons 251 _1; 251 ₂ as two pairs of events occurring at times tf _nl and tf _nl = tf _nl + At _x for the value x _\ and at times tf _n2 and tf _n2 = tf _n2 + At ₂ for the value x ₂ (figure 25) with Ah = T _min + x ₂ .T _cod .

Each neuron input 251 _k (k = 1 or 2) belongs to a group of nodes 20 _¾ similar to that described with reference to FIG. 2. The first neuron 253 _k of this group 20 _¾ is the transmitting node of a g _e _k -synapse exciter 252 weight w _acc and delay T _min + T _syn, while the last neuron _k 255 is the source node of a g _e inhibitory -synapse 254 _¾ weight- w _acc and delay T _syn . The two g _e -synapses 252 _¾ , 254 _¾ from the node group 20 _¾ have as receiving node the same acc 256 _k neuron which plays a role similar to the accelerator neuron 216 of FIG. 21. further a sync neuron 260 which is the receiver of two V-excitatory synapses node 261 _l5 261 ₂ WJ2 weight and delay T _syn respectively from the neurones last 255 _\, 255 _2. A synapse 262 of weight g ^ u and of delay T _syn and an excitatory gay-synapse 264 of weight 1 and of delay T _syn go from neuron sync 260 to neuron acc 256 _\ . [00212] A ^ / - synapse 265 of weight g _mu i _t and of delay T _syn and an excitatory gay-synapse 266 of weight 1 and of delay T _syn go from the neuron acc 256 _\ to the neuron acc 256 ₂ .

The circuit 250 comprises another acc 268 neuron which plays a role similar to the accelerator neuron 238 of FIG. 23. The accelerator neuron 268 is the receptor node of a 269 μ / synapse of weight g _mu i _t and 3T _syn , and a 270 excitatory gay synapse, weight 1 and 3T _{syn syn} , both from the sync neuron 260. In addition, the acc 268 neuron is the receiving node of an inhibitory gay synapse 271, weight -1 and delay T _syn , and excitatory _e- synapse 272, weight w _acc and delay T _syn , both from the neuron acc 256 ₂ .

The circuit 250 finally has a neuron output 274 which is the receiving node an excitatory V-synapse 275, of weight w _e and 2T _syn late, from the acceler 256 neuron ₂ and an excitatory V-synapse 276, weight w _e and delay T _syn + T _syn , from the neuron acc 268.

[88215] The operation of the multiplier circuit 250 according to FIG. 25 is illustrated in FIG. 26.

[01) 216] Each of the two neurons acc 256 _1; 256 ₂ behaves initially like the neuron acc 216 of Figure 21, with a linear progression 278 _1; 278 ₂ of weight w _acc over a first period of respective duration xi.T _cod , X2-T _cod , leading to store the potential values V _t .x _\ and V _t .X2 in acc 2561, 256 ₂ neurons. [8) 217] The emission of the second spike at time tf tf _n2 + _n2 = T _min + x ₂ - T _C o _d ^at the input neuron having the smallest value (the neuron input 251 ₂ in the example shown in figure 26 where one ax _\ > JC ₂ ) stops the accumulation with linear dynamics on the acc corresponding neuron 256 ₂ via the g _e -synapse 254 ₂ at the time tl _ast2 + T _syn = tf _n2 + 2T _syn + T _neu . The membrane potential of this neuron acc 256 ₂ then presents a plateau 279 which lasts until its reactivation via the synapses 265, 266. At time t1 _ast2 + T _syn = tfm + 2T _syn + T _neu , the potential of the sync neuron 260 passes to the value V _t / 2 due to the event received from the neuron last 255 ₂ via the V-synapse 261 ₂ .

[1) 8218] The emission of the second spike at time tf _nl = tf _nl + T _min + x _x . T _cod at the level of the neuron input having the highest value (the input neuron 25 \ _\ in the case of Figure 26) stops linear dynamic accumulation on the corresponding acce neuron 256 _\ via the ^ -synapse 254i at time tf _astl + T _syn = tf _nl + 2T _syn + T _neu . At the same time, the potential of this neuron sync 260 reaches the value due to the event received on the V-synapse 2611. The result is the emission of an event at the time = tf _nl + 2T _syn + 2T _neu on the synapses 262 and 264. The exponential dynamics 280i is then activated on the accelerometer 256i instead of the linear dynamics 278i at the time t _tl = + T _syn . At the same time, the synapses 269, 270 activate the exponential dynamics 281 on the acc 268 neuron at time t _t3 = + 3T _syn .

[08219] The potential of access 256 _\ neuron reaches the threshold V _t and causes an event on synapses 265, 266 at time t = tf _ogl _t - r ^. log (x ₁ ). The exponential dynamics 280i is then activated on the neuron acc 256 ₂ at time = tfogi + T _syn . The potential of this neuron acc 256 ₂ reaches the threshold V _t and causes an event on the synapses 271, 272, 275 at the time î. log (x ₂ ) = t ync ^~ Tf. \ og (x ₁ x ₂ ) + 2T _syn . The gay-synapse 271 disables the exponential dynamic 281 on the acc 268 neuron at time t _gnd3 = + T _syn , and simultaneously the linear dynamics 282 of the acc 268 neuron is activated via the g _e -synapse 272 from the value:

[88221] The V-synapse 275 causes the emission of a first spike on the neuron output 274 at the time + 2T _syn + T _neu . [00222] The acc 268 neuron reaches the threshold V _t and causes an event on the

V-synapse 276 at the time ex _x p _v = + x ₁ . x ₂ . T _cod . As a result, at the level of the output neuron 21 the emission of a second spike at time t% _ut = + T _min + T _syn + T _neu .

[8) 223] Finally, two events issued by the output neuron 268 are separated by a time interval AT _0UT t =% _C - t £ _ut = T _min + x _1. x ₂ . T _cod = f {x. x ₂ ). [8 (1224] The circuit 250 of FIG. 25 thus delivers on its output neuron 268 the representation of the product x \ .X2 of the two numbers x _\ , x ₂ between A and 1 from which it receives the respective representations on its neurons. 251 _1; 251 ₂ .

[80225] For this, the event pairs did not have to be received synchronized on neurons input 251 _1; 251 ₂ , the sync neuron 260 taking care of the synchronization. D.4. Signed multiplication

Figure 27 shows a multiplier circuit 290 which calculates the product of two signed values x _\ , JC ₂ . All the synapses shown in Figure 27 show the delay T

[88227] For each input value ¾ (1 <k <2), the multiplier circuit 290 comprises an input neuron + 29 and an input-292 _k neuron which are the transmitting nodes of two respective V-synapses 293 _¾ and 294 ^ weight _e . The y-synapses 293i and 294i are directed towards a neuron input 25 \ _\ of a multiplier circuit 250 of the kind shown in Figure 25, while the V-synapses 293 and 29-i are directed to the other input neuron 251 ₂ of the circuit 250.

[01) 228] The multiplier circuit 290 has a + 295 output neuron and an output-296 neuron which are the receptor nodes of two respective excitatory V-synapses 297 and 298 of weight w _e from the output neuron 274 of the circuit 250.

[01) 229] The multiplier circuit 290 further comprises four sign 300-303 neurons connected to form a selection logic of the sign of the result of the multiplication. Each signaling neuron 300-303 is the receiving node of two respective excitatory V-synapses of weight w _e / 4 from two of the four input neurons 291 _¾ , 292 ^. The sign 300 neuron connected to input + 291 ₁ neurons _; 291 ₂ detects the reception of two positive x X2 inputs. It forms the emitting node of an inhibitory V-synapse 305 of weight 2wi going to the neuron output- 296. The sign 303 neuron connected to the input-292 ₁ neurons _; 292 ₂ detects the reception of two x _\ , x ₂ negative inputs. It forms the transmitting node of a 308 inhibitory V-synapse of weight to neuron output- 296. The signal neuron 301 connected to the input- 292 _\ neurons and input + 292 _\ detects the reception of a negative input x _\ and a positive input JC ₂ . It forms the emitter node of an inhibitory synapse V-306 2wi weight from the neuron 295. The neuron output + sign 302 connected to input neurons + 29 \ _\ input- and 292 ₂ detects the reception of an input x _\ positive and a negative x ₂ input. It forms the transmitting node of an inhibitory V-synapse 307 of weight 2wi going to the neuron output + 295.

[8) 230] Inhibitory V-synapses are arranged between the 300-303 sign neurons to ensure that only one of them intervenes to inhibit one of the output 295 and output 296 neurons. Each neuron sign 300-303 corresponding to a sign (+ or -) of the product is thus the node emitting two inhibitory V-synapses of weight wJ2 going respectively to the two sign neurons corresponding to the opposite sign.

[00231] Thus arranged, the circuit 290 of FIG. 27 delivers two events separated from the time interval. on one of its outputs 295, 296, according to the sign of X1.X2, when the two numbers x _\ , JC ₂ are presented with their respective signs on the inputs 29, 292¾. [0] 232] Zero detection logic can be added to one of the inputs, as in Figure 17, to ensure that zero input will produce the time T _min between two events produced on the neuron output + 295 and not the neuron output- 296.

E. Resolution of differential equations E.1. Integration [1) 8233] Figure 28 shows a circuit 310 that reconstructs a signal from its derivatives provided in signed form on a neuron of a pair of input + 311 and input-312 neurons. The integrated signal is presented, based on of its sign, by a neuron of a pair of output + 313 and output-314 neurons. The 321-332 synapses shown in FIG. 28 are excitatory V-synapses of weight w _e . They have all the delay T _syn except the synapse 329 whose delay is T _m i _n + T _syn .

[01) 234] To achieve the integration, the circuit 310 uses a linear combination circuit 200 of the kind shown in FIG. 20, with N = 2 and coefficients ac _> = 1 and a = dt, where dt is the integration step chosen.

[01) 235] Neurons input + 311 and input- 312 are respectively connected to the input neurons and input- + 18 \ _\ circuit 200 associated with the coefficient a _\ = dt by two V-synapses 321, 322.

[01) 236] The other input neurons + and input- 181 _\ circuit 200, associated with the coefficient ao = 1, are respectively connected by two V-synapses 323, 324 to two output neurons + 315 and output- 316 of a circuit 217 whose role is to provide an initialization value xc, for the integration process. The circuit 317 essentially consists of the pair of output + 315 and output-316 neurons connected to the same recall neuron 15 as shown in FIG.

Another initiating neuron 318 of the integration circuit 310 is the transmitting node of a synapse 325 whose receiving node is the recall neuron 15 of the circuit 317. The initiating neuron 318 loads the integrator with its initial value x _0. stored in circuit 317.

Synapses 326, 327 are arranged to retroact, respectively, the neuron output + 143 of the linear combination circuit 200 on its input neuron + 18 lo and the output-144 neuron of the integration circuit 200 on its neuron input-18. lo- [88239] A start neuron 319 is the transmitting node of two synapses 328, 329 which have a zero value in the form of two events separated from the time interval T _m in on the input neuron + 18 of the integration circuit 180.

[88248] The neurons output + 143 and output-144 of the linear combination circuit 200 are the respective transmitting nodes of two synapses 330, 331 whose receiving nodes are respectively the output 313 and output 314 neurons of the integration circuit 310.

The integration circuit 310 finally has a new input neuron 320 which is the receiving node of a synapse 332 coming from the start neuron 207 of the linear combination circuit 200. The initial value xc is, according to its sign, delivered on the neuron output + 313 or output- 314 once the neuron init 318 and then the neuron start 319 have been activated. At the same time, an event is delivered by the new input neuron 320. This event signals to the environment of the circuit 310 that the derivative value g k.dt), with k = 0, can be provided. As soon as this derivative value g k.dt) is presented on the input + 311 or input-312 neuron, a new integral value is delivered by the output + 313 or output-314 neuron and a new event delivered by the new input neuron. 320 signals to the environment of circuit 310 that the next derivative value g ^''' ((k + 1) .dt) can be provided. This process is repeated as many times as derivative values g k.dt) are provided (k = 0, 1, 2, etc.). After providing a (fc + 1) -th derivative value g k.dt) to the integrator circuit 310, the output is represented by the value: x ₀ + Σ _{= 0} g '(i .dt) ). dt (23) which, to an additive constant, is an approximation of g (T) = / g '(t). dt, with T = (k + l) .dt. The circuits described above with reference to FIGS. 1-28 can be assembled and configured to perform many types of calculations in which the quantities manipulated, input and / or output are represented by time intervals between events received or delivered. by neurons. In particular, Figures 29, 31 and 33 illustrate examples of processing devices according to the invention for solving differential equations. Calculations have been made with circuits constructed as in these figures, with parameters chosen purely by way of example as follows: T _m = 100 s, - ^ = 20 ms, V ^ 10 mV, Tmin = 10 ms and T _cod = 100 ms.

E.2. Differential equation of the first order

[88246] Figure 29 shows a processing device that implements the resolution of the differential equation: x. - + X {t) = X _∞ (24) where τ and X _∞ are parameters that can take different values. The synapses shown in Figure 29 are all excitatory V-synapses of weight w _e and delay T

[88247] To solve equation (24), the device of FIG. 29 uses:

A linear combination circuit 200 as represented in FIG. 20, with N = 2 and coefficients ac _> = -l / τ and a _\ = + 1 / τ;

An integrator circuit 310 as represented in FIG. 28, with an integration step dt; and

A circuit 317 for supplying the constant X∞, similar to the circuit 317 described with reference to FIG. 28, in the form of the time interval f (\ XJ) between two spikes delivered either by its output neuron + 315, or by its output-316 neuron, according to the sign of X _∞ .

[88248] The constant X _∞ is supplied to one of the input + and input-18 neurons associated with the coefficient a _\ = 1 / f in the linear combination circuit 200 after each activation of the recall neuron 15 which is the receiving node of a synapse 340 from the new input neuron 320 of the integrator circuit 310. Two synapses 341, 342 retroact the output + 313 of the integrator circuit 310 on the other input input + 18 lo of the linear combination circuit 200 and, respectively, the output output 314 of the circuit 310 on the other input-18 input of the circuit 200. Two synapses 343, 344 go from the output output + 203 of the linear combination circuit 200 at input input + 311 of integrator circuit 310 and, respectively, of output output 204 of circuit 200 at input input 312 of circuit 310.

[01) 249] The device of FIG. 29 has a pair of output + 346 and output-347 neurons which are the receiving nodes of two synapses resulting from the output + 313 and output-314 neurons of the integrator circuit 310.

[t) D25ft] The init 348 and start 349 neurons are used to initialize and start the integration process. The init neuron 348 must be triggered before the integration process to load the initial value in the integrator circuit 310. The start neuron 349 is triggered to deliver the first value from the circuit 310. The device of Fig. 29 is carried out using 118 neurons if the components as described with reference to the preceding figures are used. This number of neurons can be reduced by optimization.

100252] Simulation results of this device with different sets of parameters τ, Xoo and with an integration step dt = 0.5 are presented in FIG. 30A for different values of τ and in FIG. 30B for different values of X _∞ (X _∞ = -0.2, X _∞ = 0.1 and Xoo = -0.4). Each point of the curves C1-C3, C '1-C'3 shown in FIGS. 30A and 30B corresponds to a respective output value coded by a pair of spikes delivered by the output neuron + 346 or the output-347 neuron. that the curves thus obtained for the solution X (t) of the differential equation (24) are in accordance with what is expected (by analytical resolution).

E.3. Differential equation of the second order

[88253] Figure 31 shows a processing device that implements the resolution of the differential ^equation? O ^"dt ^{^.} U $ ² dt ^ * ^, where ξ and &> o are parameters that can take different values The synapses shown in Fig. 31 are all excitatory V-synapses of weight w _e and delay T _syn, since the quantities manipulated in this example are all positive. necessary to provide two separate paths for positive and negative values. Only the path relative to the positive values is therefore included.

[00254] To solve equation (25), the device of FIG. 31 uses:

• a linear combination circuit 200 as shown in Figure 20, with N = 3 and the coefficients ο = a ₂ = & Ό ² and ai = -ζ.ω;

Two integrating circuits 310A, 310B such as that shown in FIG. 28, with an integration step dt; and

A circuit 317 for supplying the constant X∞, similar to the circuit described with reference to FIG. 1, in the form of the time interval flX∞) between two spikes delivered by its output neuron 16 (X∞> 0).

[88255] The constant X _∞ is supplied to the input neuron 181 ₂ associated with the coefficient 2 = a> o in the linear combination circuit 200 after each activation of the recall neuron 15 which is the receiving node of a synapse 350 originating from the neuron new input 320 of the second integrator circuit 310B. Two synapses 351, 352 make the output output 313 of the second integrator circuit 310B back to the input input 18 _\ of the linear combination circuit 200 associated with the coefficient a _\ = -ξ.ωο and, respectively, the output output 313 of the first integrator circuit 310A on the other input input 18 lo of the circuit 200 associated with the coefficient ao = ωο. A synapse 353 goes from the output output 203 of the linear combination circuit 200 to the input input 311 of the first integrator circuit 310A. A synapse 354 goes from the output output 313 of the first integrator circuit 310A to the input input 311 of the second integrator circuit 310B.

The device of FIG. 31 has a output neuron 356 which is the receiving node of a synapse originating from the output neuron 313 of the second integrating circuit 310B.

[88257] The init 358 and start 359 neurons make it possible to initialize and start the integration process. The init neuron 358 must be triggered prior to the integration process to load the initial values into the integrator circuits 310A, 310B. The start neuron 359 is triggered to deliver the first value from the second integrator circuit 310B. [88258] The device of FIG. 31 is made using 187 neurons if the components as described with reference to the preceding figures are used. This number of neurons can be reduced by optimization.

[88259] Simulation results of this device with different sets of parameters ξ, coç, and with an integration step dt = 0.2 and X _∞ = 0.5 are presented in FIG. 32A for different values of coç, and in Fig. 32B for different values of ξ. Each point on the curves D1-D3, D '1-D'3 shown in FIGS. 32A and 32B corresponds to a respective output value coded by a pair of spikes delivered by the output neuron 356. It can be seen that the curves thus obtained for the solution X (t) of the differential equation (25) are again in accordance with what is expected.

E.4. Resolution of a system of nonlinear differential equations

[88260] Figure 33 shows a processing device that implements the resolution of E. Lorenz's system of non-linear differential equations for the modeling of a deterministic nonperiodic flow (Journal of the Atmospheric Sciences). Vol 20, No. 2, pages 130-141, March 1963): = o {Y (t) - X (t))

<^ _t = p. X (t) - Y (t) - X (t). Z {t) (26)

[I) 8261] To ensure that the modeled system has a chaotic behavior, the device of figure 33 was simulated with the choice of parameters σ = 10, β = 8/3 and p = 28. The variables were set to scale to obtain X, Y and Z state variables each moving in the range [0, 1] so that they can be represented in the form

(I I) above. The initial state of the system was set at X = - 0.15, Y = - 0.20, and Z = 0.20. The integration step used was dt = 0.01.

The synapses shown in Fig. 33 are all excitatory V-synapses of weight w _e and delay T _syn . To simplify the drawing, only one path is represented, but it must be understood that each time there is a path for the positive values of the variables and, in parallel, a path for their negative values.

To solve the system (26), the device of FIG. 33 uses: Two signed multiplication circuits 290A, 290B such as that shown in FIG. 27 to calculate the nonlinearities contained in the derivatives of X, Y and Z;

Three linear combination circuits 200A, 200B, 200C such as that shown in FIG. 20 to calculate the derivatives of X, Y and Z;

A signed synchronizer circuit 90 of the type shown in FIG.

N = 3 to wait until the three derivatives are calculated before changing the state of the system;

Three integrating circuits 310A, 310B, 310C of steps dt such as that represented in FIG. 28 to calculate the new state from the derivatives of X, Y and Z. The linear combination circuit 200A is configured N = 2 and coefficients ac> = σ and ai = -σ. Its input neuron 181Ao is excited from the output neuron 313A of the integrator circuit 310A, and its input neuron 181Ai from the output neuron 313B of the integrator circuit 310B. Its output neuron 203A is the transmitting node of a synapse going to the input neuron 91 ₀ of the synchronizing circuit 90. [0026] The linear combination circuit 200B is configured N = 3 and the coefficients ac> = p and a1 = a ₂ = - 1. Its input neuron I8IB ₀ is excited from the output neuron 313B of the integrator circuit 310B, its input neuron 181Bi from the output neuron 313A of the integrator circuit 310A, and its input neuron 181B ₂ from the output neuron 295A of the multiplier circuit 290A. Its output neuron 203B is the node transmitting a synapse going to the input neuron 91 ₁ of the synchronizer circuit 90.

The linear combination circuit 200C is configured N = 2 and coefficients ac> = 1 and ai = - β. Its input neuron I8 IC ₀ is excited from the output neuron 295B of the multiplier circuit 290B, and its input neuron 18 1Ci from the output neuron 313C of the integrator circuit 310C. Its output 203C neuron is the node transmitting a synapse going to the input neuron 91 ₂ of the synchronizer circuit 90.

[00267] Three synapses are respectively the neuron output 92 ₀ Circuit synchronizer 90 to the input neuron 311A of 310A integrator circuit, the neuron output 92 _\ circuit 90 at input neuron 311B from 310B integrator circuit, and the output neuron 92 ₂ Circuit 90 to the input neuron 311C of the integrator circuit 310C. [88268] The input neuron 291 Ai of the multiplier circuit 290A is excited from the output neuron 313A of the integrator circuit 310A, and its input neuron 291A ₂ from the output neuron 313C of the integrator circuit 31C0. The input neuron 291Bi of the multiplier circuit 290B is excited from the output neuron 313A of the integrator circuit 310A, and its input neuron 291B ₂ from the output neuron 313B of the integrator circuit 310B.

The device of FIG. 33 has three output neurons 361, 362 and 363 which are the receiving nodes of three respective excitatory V-synapses from the output neurons 313A, 313B and 313C of the integrator circuits 310A, 310B, 310C. These three output neurons 361-363 deliver event pairs whose intervals represent values of the solution {X (t), Y (t), Z (t)} calculated for the system (26).

[01) 278] The device of FIG. 33 is made using 549 neurons if the components as described with reference to the preceding figures are used. This number of neurons can be significantly reduced by optimization.

The points in FIG. 34 each correspond to a triplet {X (t), Y (t), Z (t)} of output values encoded by three pairs of spikes respectively delivered by the three output neurons 361-363 , in a three-dimensional graph illustrating a simulation of the device shown in FIG. 33. The point P represents the initialization values X (0), Y (0), Z (0) of the simulation. The other points represent triplets calculated by the device of Figure 33. [0) 272] The system behaves in the expected manner, in accordance with the strange attractor described by Lorenz.

F. Discussion

It has been shown that the proposed calculation architecture, with the representation of data in the form of time intervals between events within a set of processing nodes, makes it possible to design relatively simple circuits for performing functions. elementary in a very efficient and fast way. In general, the results of the calculations are available as soon as the different input data have been provided (with some synaptic delays). [88274] These circuits can then be assembled to perform more sophisticated calculations. They form types of bricks from which one can build efficient computing structures. Examples have been shown for the resolution of differential equations. [08275] When the elementary circuits are assembled, it is possible to optimize the number of neurons used. For example, some of the circuits have been described with input neurons, and / or output neurons and / or first, last neurons. In practice, these neurons can often be dispensed with at the interfaces between elementary circuits without changing the functionality that is fulfilled. The processing nodes are typically organized into a matrix. This lends itself particularly to an implementation using FPGA.

A programmable network 400 constituting the set of processing nodes, or a part thereof, in an exemplary implementation of the processing device is illustrated schematically in FIG. 35. The network 400 consists of multiple neurons. all having the same pattern of behavior based on events received on their connections. For example, the behavior can be modeled by the equations (1) indicated above, with identical parameters T _m and Tf for the different nodes of the network.

A programming or configuration logic 420 is associated with the network 400 for adjusting the synaptic weights and the delay parameters of the connections between the nodes of the network 400. This configuration is operated in a manner analogous to that which is commonly practiced in the network. field of artificial neural networks. In the present context, the configuration of the parameters of the connections is carried out according to the calculation program which it is necessary to execute and taking into account the relation employed between the intervals of time and the quantities which they represent, by example the relation (11). If the program is broken down into elementary operations, the configuration may result from a circuit assembly of the kind described above. This configuration is performed under the control of a control unit 410 provided with a man-machine interface. Another role of the control unit 410 and to provide the input quantities to the programmable network 400 as events separated by time intervals appropriate, for the network processing nodes 400 to execute the calculation and to deliver the results. These results are quickly retrieved by the control unit 410 to be presented to a user or an application that uses them.

[88288] This computation architecture is well suited for fast execution of massively parallel calculations.

[8828] In addition, it is relatively easy to have a pipeline organization of calculations for the execution of algorithms that lend themselves to this type of organization.

[88282] The embodiments described above are illustrations of the present invention. Various modifications can be made without departing from the scope of the invention which emerges from the appended claims.

Claims

A data processing device, comprising a set of processing nodes and connections between the nodes,

wherein each connection has a transmitting node and a receiving node among the set of processing nodes and is configured to transmit events delivered by the transmitting node to the receiving node,

wherein each node is arranged to vary a respective potential value (V) as a function of events received by said node and to deliver an event when the potential value reaches a predefined threshold (V _t ),

wherein at least one input variable (x) of the data processing device is represented by a time interval (At) between two events received by at least one node,

and wherein at least one output quantity of the data processing device is represented by a time interval between two events delivered by at least one node.

2. Device according to claim 1,

wherein each processing node is arranged to reset its potential value when delivering an event.

3. Device according to any one of the preceding claims,

wherein the connections between the nodes comprise potential variation connections each having a respective weight,

and wherein the receiver node of a potential variation connection is arranged to react to an event received on said potential variation connection by adding to its potential value (V) the weight of said potential variation connection.

4. Device according to claim 3, wherein the set of processing nodes comprises at least a first node (23) forming the receiving node of a first potential variation connection (22) having a first positive weight at least equal to the predefined threshold (V _t ) for the potential value, and at least one second node (25) forming the receiving node of a second potential variation connection (24) of weight at least equal to half the predefined threshold for the potential value and below the threshold predefined (V _t ) for the potential value, wherein the first node (23) further forms the transmitting node and the receiving node of a third potential variation connection (28) of equal weight opposite the first weight,

wherein the first node (23) further forms the transmitting node of a fourth connection (26) and the second node (25) further forms the transmitting node of a fifth connection (27),

and wherein the first and second potential variation connections (22, 24) are configured to each receive two events separated by a first time interval (At) representing an input quantity so that the fourth and fifth connections (26) , 27) carry respective events having between them a second time interval related to the first time interval (At).

5. Device according to claim 3, comprising at least one minimum calculation circuit (100),

wherein the minimum calculation circuit comprises:

first and second input nodes (101, 102);

an output node (103);

first and second selection nodes (104, 105);

first, second, third, fourth, fifth and sixth potential variation connections (106-111) each having a first positive weight at least equal to half the predefined threshold (V _t ) for the potential value and less than the threshold predefined value (V _t ) for the potential value;

seventh and eighth potential variation connections (112-113) each having a second weight opposite the first weight; and ninth and tenth potential variation connections (114-115) each having a third double weight of the second weight,

wherein the first input node (101) forms the transmitting node of the first and third connections (106, 108) and the receiving node of the tenth connection (115),

wherein the second input node (102) forms the sending node of the second and fourth connections (107, 109) and the receiving node of the ninth connection (114), wherein the first selection node (104) forms the node emitter of the fifth, seventh and ninth connections (110, 112, 114) and the receiving node of the first and eighth connections (106, 113),

wherein the second selection node (105) forms the transmitting node of the sixth, eighth and tenth connections (111, 113, 115) and the receiving node of the second and seventh connections (107, 112),

and wherein the output node (103) forms the receiving node of the third, fourth, fifth and sixth connections (108-111).

6. Device according to claim 3, comprising at least one calculation circuit of maximum (120),

in which the maximum calculation circuit comprises:

first and second input nodes (121, 122);

an output node (123);

first and second selection nodes (124, 125);

first, second, third and fourth potential variation connections (126-129) each having a first positive weight at least equal to half the predefined threshold (V _t ) for the potential value and less than the predefined threshold (V _t ) for the potential value; and

fifth and sixth potential variation connections (132-133) each having a second weight equal to twice the opposite of the first weight, wherein the first input node (121) forms the transmitting node of the first and third connections (126, 128),

wherein the second input node (122) forms the transmitting node of the second and fourth connections (127, 129), wherein the first selection node (104) forms the transmitting node of the fifth connection (132) and the receiving node of the first and sixth connections (126, 133),

wherein the second selection node (105) forms the sending node of the sixth connection (133) and the receiving node of the second and fifth connections (127, 132), and wherein the output node (123) forms the receiving node third and fourth connections (128, 129).

7. Device according to claim 3, comprising at least one subtraction circuit (140, 170),

wherein the subtracter circuit (140, 170) comprises:

first and second synchronization nodes (145, 146); first and second inhibition nodes (147, 148);

first and second output nodes (143, 144);

first, second, third, fourth, fifth and sixth potential variation connections (152-157) each having a first positive weight at least equal to the predefined threshold (V _t ) for the potential value; seventh and eighth potential variation connections (160, 161) each having a second weight equal to half the first weight;

ninth and tenth potential variation connections (158, 159) each having a third weight opposite the first weight; and

eleventh and twelfth potential variation connections (162, 163) each having a fourth weight double the third weight,

wherein the first synchronization node (145) forms the transmitting node of the first, second, third and ninth connections (152, 153, 154, 158),

wherein the second synchronization node (146) forms the transmitting node of the fourth, fifth, sixth and tenth connections (155, 156, 157, 159),

wherein the first muting node (147) forms the transmitting node of the eleventh connection (162) and the receiving node of the third, eighth and tenth connections (154, 161, 159), wherein the second muting node (148) forms the transmitting node of the twelfth connection (163) and the receiving node of the sixth, seventh and ninth connections (157, 160, 158),

wherein the first output node (143) forms the sending node of the seventh connection (160) and the receiving node of the first, fifth and eleventh connections (152, 156, 162),

wherein the second output node (144) forms the transmitting node of the eighth connection (161) and the receiving node of the second, fourth and twelfth connections (153, 155, 163),

and wherein the first synchronization node (145) is configured to receive, on at least one potential variation connection (150) having the second weight, a first pair of events having a first time interval between them (At _\ ) representing a first operand (x), and the second synchronization node (146) is configured to receive, on at least one potential variation connection (15 1) having the second weight, a second pair of events having them a second time interval (_dt ₂ ) representing a second operand (x ₂ ), so that a third pair of events having between them a third time interval (zli _out ) is delivered by the first output node (143); ) if the first time interval (At _\ ) is longer than the second time interval (_dt ₂ ) and the second output node (144) if the first time interval (At _\ ) is shorter than the second time interval (At _\ ) time interval (At2), the third th time interval (zliout) representing the absolute value of the difference between the first and second operands (xi, x ₂ ).

8. Device according to claim 7,

wherein the subtractor circuit (170) further comprises a zero detection logic including at least one detection node (17 1) associated with detection and inhibition connections (172-178) with the first and second node of synchronization (145, 146), one of the first and second muting nodes (147, 148) and one of the first and second output nodes (143, 144),

and wherein the detection and inhibition (172-178) connections are faster than the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth connections (152-163) , for inhibiting the generation of events by one of the first and second output nodes (143, 144) when the first and second time slots (Mu Mi) are substantially equal.

9. Device according to any one of claims 3 to 8,

wherein the set of processing nodes comprises at least one node arranged to vary a current value as a function of events received on at least one current setting connection, and to vary its potential value over time with a rate of change proportional to said current value.

Device according to claim 9,

wherein a processing node arranged to vary a current value is arranged to reset said current value when delivering an event.

11. Device according to claim 9 or claim 10,

wherein the current value in at least one node has a constant component (g _e ) between two events received on at least one constant current component setting connection having a respective weight,

and wherein the receiving node of a current constant component tuning connection is arranged to react to an event received on said connection by adding the weight of said connection to the constant component (g _e ) of its current value.

Device according to claim 11, comprising at least one inverting memory circuit (18),

wherein the inverting memory circuit comprises:

an accumulator node (30);

first, second and third current constant component control connections, the first and third connections (26, 34) having the same positive weight (w _acc ) and the second connection (27) having an opposite weight (-w _acc ) the weight of the first and third connections; and

at least one fourth connection (35), wherein the accumulator node (30) forms the receiving node of the first, second and third connections (26, 27, 34) and the transmitting node of the fourth connection (35),

and wherein the first and second connections (26, 27) are configured to respectively address to the accumulator node (30) first and second events having between them a first time interval in relation to a time interval representing a magnitude to be stored, whereby the accumulator node (30) then responds to a third event received on the third connection (34) by increasing its potential value until a fourth event is delivered on the fourth connection (35), the third and fourth events having between them a second time interval in relation to the first time interval.

Device according to claim 12, comprising at least one memory circuit (40),

wherein the memory circuit comprises:

first and second accumulator nodes (42, 44);

first, second, third and fourth current constant component control connections, the first, second and fourth connections (41, 43, 51) each having a first positive weight (w _acc ) and the third connection (45) having a weight (-w _acc ) opposite to the weight of the first, second and fourth connections; and

at least one fifth connection (52),

wherein the first storage node (42) forms the receiving node of the first connection (41) and the transmitting node of the third connection (45),

wherein the second storage node (44) forms the receiving node of the second, third and fourth and fifth connections (43, 45, 51) and the transmitting node of the fifth connection (52),

and wherein the first and second connections (41, 43) are configured to respectively address to the first and second accumulator nodes (42, 44) first and second events having between them a first time interval in relation to a time interval representing a magnitude to be stored, so that the second accumulator node (44) then responds to a third event received on the fourth connection (51) by increasing its potential value until delivery of a fourth event on the fifth connection (52), the third and fourth events having between them a second time interval in relation to the first time interval.

14. Device according to claim 13,

wherein the memory circuit (40) comprises a sixth connection (46) having the first storage node (42) as the transmitting node, the sixth connection providing an event for signaling the read availability of the memory circuit.

Device according to claim 14, comprising at least one synchronization circuit (90, 98) including a number N> 1 of memory circuits (40 _1; 40 JV-I) and a synchronization node (95),

wherein the synchronization node (95) is responsive to each event delivered on the sixth connection of one of the N memory circuits (40 _1; 40JV-I) via a respective potential variation connection (46; 96o, 96JV). -I) of weight equal to the first weight divided by N,

and wherein the synchronization node (95) is arranged to cause simultaneous reception of the third events via the fourth respective connections (51) of the N memory circuits (40 _1; ..., 40JV-I).

Device according to claim 11, comprising at least one accumulation circuit (180), in which the accumulation circuit comprises:

N entries (181o, 181JV-I) each having a respective weighting coefficient (<%, ..., <¾v-i), N being an integer greater than 1;

an accumulator node (184);

a synchronization node (185);

for each of the N inputs of the accumulation circuit (180):

a first current constant component control connection (182o, 182JV-I) having a first positive weight (<% ¼v _c , CCN-Ï W _OCC ) proportional to the respective weighting coefficient of said input; and a second current constant component control connection (183o, · · ·, 183JV-I) having a second weight (- <% ¼v _c , opposite the first weight; and

a third constant current component setting connection (186) having a third positive weight (w _acc ),

wherein the accumulator node (184) forms the receiving node of the first, second and third connections (181o, 181JV-I, 182 ₀ , 182jv-i, 186),

wherein the synchronization node (185) forms the transmitting node of the third connection (186),

wherein, for each of the N inputs, the first and second connections (18 lo,, 181 j-i, 182 ₀ , 182JV-I) are configured to respectively address the accumulator node (184) of the first and second events having them a first time interval representing a respective operand provided on said input,

wherein the synchronization node (185) is configured to output a third event after the first and second events have been addressed for each of the N inputs, so that the accumulator node (184) increases its potential value to at issuing a fourth event, the third and fourth events having between them a second time interval in relation to a time interval representing a weighted sum of the operands provided on the N entries.

Device according to claim 16,

wherein the stacking circuit (180) is part of a weighted summation circuit (190) further comprising:

a second accumulator node (188);

a fourth current constant component control connection (191) having the third weight (¼v _c ); and

fifth and sixth connections (193, 192),

wherein the synchronization node (185) of the accumulation circuit forms the transmitting node of the fourth connection (191),

wherein the accumulator circuit accumulator node (184) forms the transmitting node of the fifth connection (193), wherein the second storage node (188) forms the receiving node of the fourth connection (191) and the transmitting node of the sixth connection (192),

wherein, in response to the delivery of the third event by the synchronization node (185), the accumulator node (184) of the accumulation circuit increases its potential value until delivery of the fourth event on the fifth connection (193) , and the second accumulator node (188) increases its potential value until a fifth event is delivered on the sixth connection (192), the fourth and fifth events having a third time interval in relation to an interval between them time representing a weighted sum of the operands provided on the N inputs of the accumulation circuit (180).

Device according to claim 16, comprising two accumulation circuits (180A, 180B) assembled in a linear combination circuit (200),

wherein the two accumulator circuits (180A, 180B) share their synchronization node (184),

wherein the linear combination circuit further comprises a subtractor circuit (170) configured to respond to the third event delivered by the shared synchronization node (185) and the fourth events respectively delivered by the accumulator nodes (184) of the two accumulation circuits (180A, 180B) by delivering a pair of events having between them a third time interval representative of the difference between the weighted sum for one of the two accumulation circuits and the weighted sum for the other of the two accumulation circuits .

19. Device according to any one of claims 11 to 18,

wherein the current value in at least one node has an exponentially decreasing component (gf) between two events received on at least one exponential decay current component setting connection having a respective weight, and wherein the receive node an exponential decay current component setting connection is arranged to react to an event received on said connection by adding the weight of said connection to the exponential decay component (gf) of its current value.

Device according to claim 19, comprising at least one log calculating circuit (210),

wherein the log computation circuit comprises:

an accumulator node (216);

first and second current constant component control connections, the first connection (212) having a positive weight (w _acc ), and the second connection (214) having a weight (- w _acc ) opposite to the weight of the first connection ;

a third exponential decay current component control connection (217); and

at least one fourth connection (222),

wherein the accumulator node (216) forms the receiving node of the first, second and third connections (212, 214, 217) and the transmitting node of the fourth connection (222),

wherein the first and second connections (212, 214) are configured to address to the accumulator node (216) first and second respective events having between them a first time interval in relation to a time interval (At) representing a magnitude of input (x) of the log computation circuit (210),

wherein the third connection (217) is configured to address to the accumulator node (216) a third event concurrent with or subsequent to the second event, so that the accumulator node increases its potential value until a fourth event is delivered on the fourth connection (222), the third and fourth events having between them a second time interval in relation to a time interval (At _out ) representing a logarithm of said input quantity.

Device according to claim 19,

wherein at least one node (238; 268) accounting for an exponential decaying current component (gf) is the receiving node of a disabling connection (236; 271) for receiving decay component deactivation events exponential.

22. Device according to claim 21, comprising at least one exponential calculation circuit (230),

wherein the exponential calculating circuit comprises:

an accumulator node (238);

a first exponential decay current component setting connection (232);

a second deactivation connection (236);

a third current constant component setting connection (237); and

at least one fourth connection (242),

wherein the accumulator node (238) forms the receiving node of the first, second and third connections (232, 236, 237) and the transmitting node of the fourth connection (242),

wherein the first and second connections (232, 236) are configured to address to the accumulator node (238) first and second respective events having between them a first time interval in relation to a time interval (At) representing a magnitude of input (x) of the exponential calculating circuit (230),

wherein the third connection (237) is configured to address to the accumulator node (238) a third event concurrent with or subsequent to the second event, so that the accumulator node increases its potential value until a fourth event is delivered on the fourth connection (242), the third and fourth events having between them a second time interval in relation to a time interval (At _out ) representing an exponential of said input quantity.

23. Device according to claim 21, comprising at least one multiplier circuit (250),

wherein the multiplier circuit comprises:

first, second and third accumulator nodes (256 _1, 256 ₂ , 268); a synchronization node (260);

first, second, third, fourth and fifth current constant component control connections, the first, third and fifth connections (252 _1; 252 ₂ , 272) having a first positive weight (w _acc ), and the second and fourth connections (254 _1; 254 ₂ ) having a second weight (- w _acc ) opposite the first weight;

sixth, seventh and eighth exponential decay current component tuning connections (262, 265, 269);

a ninth deactivation connection (271); and

at least one tenth connection (276),

wherein the first storage node (2560) forms the receiving node of the first, second and sixth connections (252 _1; 254 _1; 262) and the transmitting node of the seventh connection (265);

wherein the second storage node (256 ₂ ) forms the receiving node of the third, fourth and seventh connections (252 ₂ , 254 ₂ , 265) and the transmitting node of the fifth and ninth connections (272, 271),

wherein the third storage node (268) forms the receiving node of the fifth, eighth and ninth connections (272, 269, 271) and the transmitting node of the tenth connection (276),

wherein the synchronization node (260) forms the transmitting node of the sixth and eighth connections (272, 271),

wherein the first and second connections (252 _1; 2540 are configured to address to the first accumulator node (2560) respective first and second events having between them a first time slot in relation to a time slot (Ati) representing a first operand (JCO multiplier circuit (250),

wherein the third and fourth connections (252 ₂ , 254 ₂ ) are configured to address to the second storage node (256 ₂ ) respective third and fourth events having between them a second time slot in relation to a time slot (_dt ₂ ) representing a second operand (x ₂ ) of the multiplier circuit (250),

wherein the synchronization node (260) is configured to deliver a fifth event on the sixth and eighth connections once the first, second, third and fourth events have been received, so that:

that the first accumulator node (2560 increases its potential value until a sixth event is delivered on the seventh connection (265); in response to the sixth event, the second accumulator node (256 ₂ ) increases its potential value until a seventh event is delivered on the fifth and ninth connections (272, 271);

in response to the seventh event, the third accumulator node (268) increases its potential value until an eighth event is delivered on the tenth connection (276), with the seventh and eighth events having a third interval between them. time in relation to a time interval (At _out ) representing the product of the first and second operands (x, ¾).

The apparatus of claim 23, further comprising a sign detection logic (300-303) associated with the multiplier circuit (250) for detecting the respective signs of the first and second operands (x, JC ₂ ) and having two events delivered having between them the time interval (At _out ) representing the product of the first and second operands on one or the other of two outputs of the multiplier circuit (250) according to the detected signs.

25. Device according to any one of the preceding claims,

wherein each connection is associated with a delay parameter, for signaling to the receiving node of said connection to perform a state change with, with respect to receiving an event on said connection, a delay indicated by said parameter.

26. Device according to any one of the preceding claims,

wherein the time interval Δt between two events representing a magnitude of absolute value x is of the form Δt = T _m j _n + xT _cod , where T _m j _n and T _cod are predefined time parameters.

27. Device according to claim 26,

wherein the quantities represented by time intervals have absolute values x between 0 and 1.

28. Device according to any one of the preceding claims, comprising, for an input quantity (x): a first input having a node or two nodes among the set of processing nodes, the first input being arranged to receive two events having between them a time interval (At) representing a positive value of said input quantity (x) ; and

a second input having a node or two nodes among the set of processing nodes, the second input being arranged to receive two events having between them a time interval (At) representing a negative value of said input quantity (x) .

Device according to any one of the preceding claims, comprising, for an output quantity (x):

a first output having a node or two nodes among the set of processing nodes, the first output being arranged to output two events having between them a time interval (At) representing a positive value of said output quantity (x); and

a second output having a node or two nodes among the set of processing nodes, the second output being arranged to deliver two events having between them a time interval (At) representing a negative value of said output quantity (x).

Apparatus according to any one of the preceding claims,

wherein the set of processing nodes is in the form of at least one programmable network (400), the nodes of the network having a common behavior pattern as a function of the received events, the device further comprising programming logic ( 420) for adjusting weights and delay parameters of the connections between the nodes of the network according to a calculation program, and a control unit (410) for supplying input quantities to the network and recovering output quantities calculated in accordance with the program.