EP3317996A4 - Mots de code d'identification pour une version à vitesse adaptée d'un flux de données - Google Patents

Mots de code d'identification pour une version à vitesse adaptée d'un flux de données Download PDF

Info

Publication number
EP3317996A4
EP3317996A4 EP15897327.1A EP15897327A EP3317996A4 EP 3317996 A4 EP3317996 A4 EP 3317996A4 EP 15897327 A EP15897327 A EP 15897327A EP 3317996 A4 EP3317996 A4 EP 3317996A4
Authority
EP
European Patent Office
Prior art keywords
rate
data stream
adapted version
identification codewords
codewords
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP15897327.1A
Other languages
German (de)
English (en)
Other versions
EP3317996A1 (fr
Inventor
Francesco Caggioni
Dimitrios Giannakopoulos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MACOM Connectivity Solutions LLC
Original Assignee
Applied Micro Circuits Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Micro Circuits Corp filed Critical Applied Micro Circuits Corp
Publication of EP3317996A1 publication Critical patent/EP3317996A1/fr
Publication of EP3317996A4 publication Critical patent/EP3317996A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40013—Details regarding a bus controller
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L2007/045—Fill bit or bits, idle words

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
EP15897327.1A 2015-06-30 2015-06-30 Mots de code d'identification pour une version à vitesse adaptée d'un flux de données Withdrawn EP3317996A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/038450 WO2017003441A1 (fr) 2015-06-30 2015-06-30 Mots de code d'identification pour une version à vitesse adaptée d'un flux de données

Publications (2)

Publication Number Publication Date
EP3317996A1 EP3317996A1 (fr) 2018-05-09
EP3317996A4 true EP3317996A4 (fr) 2019-03-13

Family

ID=57608774

Family Applications (1)

Application Number Title Priority Date Filing Date
EP15897327.1A Withdrawn EP3317996A4 (fr) 2015-06-30 2015-06-30 Mots de code d'identification pour une version à vitesse adaptée d'un flux de données

Country Status (3)

Country Link
EP (1) EP3317996A4 (fr)
CN (1) CN107925557B (fr)
WO (1) WO2017003441A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11082539B2 (en) * 2018-06-20 2021-08-03 Avago Technologies International Sales Pte. Limited System and method for performing interpacket gap repair for lossy protocols

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070153831A1 (en) * 2005-12-30 2007-07-05 Michael Kauschke Information transparent adaptation function for packet based network connections
US7366803B1 (en) * 2005-02-23 2008-04-29 Xilinx, Inc. Integrated circuit for buffering data by removing idle blocks to create a modified data stream when memory device is not near empty
US8873579B1 (en) * 2011-09-29 2014-10-28 Marvell International Ltd. Multi-rate media independent interface over a physical coding sublayer

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323426A (en) * 1992-02-21 1994-06-21 Apple Computer, Inc. Elasticity buffer for data/clock synchronization
US7113507B2 (en) * 2000-11-22 2006-09-26 Silicon Image Method and system for communicating control information via out-of-band symbols
US20040028164A1 (en) * 2002-08-07 2004-02-12 Hongtao Jiang System and method for data transition control in a multirate communication system
US7281077B2 (en) * 2005-04-06 2007-10-09 Qlogic, Corporation Elastic buffer module for PCI express devices
WO2007002789A2 (fr) * 2005-06-29 2007-01-04 Teknovus, Inc. Etablissement de differentes frequences d'horloge dans un reseau optique passif ethernet
US8867683B2 (en) * 2006-01-27 2014-10-21 Ati Technologies Ulc Receiver and method for synchronizing and aligning serial streams
SE533185C2 (sv) * 2007-02-16 2010-07-13 Scalado Ab Metod för behandling av en digital bild samt bildrepresentationsformat
JP2009246668A (ja) * 2008-03-31 2009-10-22 Fujitsu Ltd クロック再生装置及び再生方法並びに伝送装置及び中継通信システム
KR101356905B1 (ko) * 2012-04-03 2014-02-05 (주)유비쿼스 이더넷 ｌ２ 스위치 장치 및 그 데이터 전송 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7366803B1 (en) * 2005-02-23 2008-04-29 Xilinx, Inc. Integrated circuit for buffering data by removing idle blocks to create a modified data stream when memory device is not near empty
US20070153831A1 (en) * 2005-12-30 2007-07-05 Michael Kauschke Information transparent adaptation function for packet based network connections
US8873579B1 (en) * 2011-09-29 2014-10-28 Marvell International Ltd. Multi-rate media independent interface over a physical coding sublayer

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of WO2017003441A1 *
TIMOTHY P WALKER AMCC (U S A): "Information Transparent Transport of 10 GbE LAN Signals over OTN; D 79", ITU-T DRAFT STUDY PERIOD 2005-2008, INTERNATIONAL TELECOMMUNICATION UNION, GENEVA ; CH, vol. STUDY GROUP 15, 29 November 2004 (2004-11-29), pages 1 - 15, XP017407196 *

Also Published As

Publication number Publication date
CN107925557B (zh) 2020-11-06
WO2017003441A1 (fr) 2017-01-05
EP3317996A1 (fr) 2018-05-09
CN107925557A (zh) 2018-04-17

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