EP3314832A4 - Kalibrierung von verschachtelten hochgeschwindigkeitsarrays - Google Patents

Kalibrierung von verschachtelten hochgeschwindigkeitsarrays Download PDF

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Publication number
EP3314832A4
EP3314832A4 EP15896522.8A EP15896522A EP3314832A4 EP 3314832 A4 EP3314832 A4 EP 3314832A4 EP 15896522 A EP15896522 A EP 15896522A EP 3314832 A4 EP3314832 A4 EP 3314832A4
Authority
EP
European Patent Office
Prior art keywords
calibration
interleaved arrays
speed interleaved
speed
arrays
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP15896522.8A
Other languages
English (en)
French (fr)
Other versions
EP3314832A1 (de
Inventor
Moshe Malkin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MACOM Connectivity Solutions LLC
Original Assignee
Applied Micro Circuits Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Micro Circuits Corp filed Critical Applied Micro Circuits Corp
Publication of EP3314832A1 publication Critical patent/EP3314832A1/de
Publication of EP3314832A4 publication Critical patent/EP3314832A4/de
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/024—Channel estimation channel estimation algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/0204—Channel estimation of multiple channels
EP15896522.8A 2015-06-25 2015-06-25 Kalibrierung von verschachtelten hochgeschwindigkeitsarrays Withdrawn EP3314832A4 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/037597 WO2016209231A1 (en) 2015-06-25 2015-06-25 Calibration of high-speed interleaved arrays

Publications (2)

Publication Number Publication Date
EP3314832A1 EP3314832A1 (de) 2018-05-02
EP3314832A4 true EP3314832A4 (de) 2019-01-30

Family

ID=57585322

Family Applications (1)

Application Number Title Priority Date Filing Date
EP15896522.8A Withdrawn EP3314832A4 (de) 2015-06-25 2015-06-25 Kalibrierung von verschachtelten hochgeschwindigkeitsarrays

Country Status (6)

Country Link
EP (1) EP3314832A4 (de)
JP (1) JP2018520590A (de)
KR (1) KR20180034441A (de)
CN (1) CN108028814B (de)
CA (1) CA2990153A1 (de)
WO (1) WO2016209231A1 (de)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090185613A1 (en) * 2005-10-03 2009-07-23 Agazzi Oscar E High-Speed Receiver Architecture
US20130307712A1 (en) * 2012-05-18 2013-11-21 Analog Devices, Inc. CALIBRATING TIMING, GAIN AND BANDWIDTH MISMATCH IN INTERLEAVED ADCs USING INJECTION OF RANDOM PULSES

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002246910A (ja) * 2001-02-20 2002-08-30 Advantest Corp インターリーブａｄ変換方式波形ディジタイザ装置
JP2003133954A (ja) * 2001-10-26 2003-05-09 Agilent Technologies Japan Ltd インターリーブａ／ｄ変換器の校正方法
US7292170B2 (en) * 2005-06-13 2007-11-06 Texas Instruments Incorporated System and method for improved time-interleaved analog-to-digital converter arrays
ATE417409T1 (de) * 2006-02-17 2008-12-15 Sicon Semiconductor Ab Zeitverschachtelter analog-digital-wandler
KR20080077755A (ko) * 2007-02-21 2008-08-26 삼성전자주식회사 다중 안테나 시스템에서 신호 보정 장치 및 방법
US7978104B2 (en) * 2007-06-21 2011-07-12 Signal Processing Devices Sweden Ab Compensation of mismatch errors in a time-interleaved analog-to-digital converter
JP4623151B2 (ja) * 2008-06-30 2011-02-02 ソニー株式会社 受信装置、受信方法、および無線通信システム
ATE543259T1 (de) * 2009-01-26 2012-02-15 Fujitsu Semiconductor Ltd Abtastung
US9036689B2 (en) * 2012-03-29 2015-05-19 Terasquare Co., Ltd. Variable-precision distributed arithmetic multi-input multi-output equalizer for power-and-area-efficient optical dual-polarization quadrature phase-shift-keying system
US9030341B2 (en) * 2012-06-27 2015-05-12 Broadcom Corporation Compensation for lane imbalance in a multi-lane analog-to-digital converter (ADC)
CN103107966B (zh) * 2013-01-16 2016-03-30 华为技术有限公司 射频信号收发和处理的方法、设备及基站系统

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090185613A1 (en) * 2005-10-03 2009-07-23 Agazzi Oscar E High-Speed Receiver Architecture
US20130307712A1 (en) * 2012-05-18 2013-11-21 Analog Devices, Inc. CALIBRATING TIMING, GAIN AND BANDWIDTH MISMATCH IN INTERLEAVED ADCs USING INJECTION OF RANDOM PULSES

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
SANDEEP PONNURU ET AL: "On the convergence of joint channel and mismatch estimation for time-interleaved data converters", SIGNALS, SYSTEMS AND COMPUTERS (ASILOMAR), 2011 CONFERENCE RECORD OF THE FORTY FIFTH ASILOMAR CONFERENCE ON, IEEE, 6 November 2011 (2011-11-06), pages 985 - 989, XP032172243, ISBN: 978-1-4673-0321-7, DOI: 10.1109/ACSSC.2011.6190158 *
See also references of WO2016209231A1 *

Also Published As

Publication number Publication date
JP2018520590A (ja) 2018-07-26
CA2990153A1 (en) 2016-12-29
WO2016209231A1 (en) 2016-12-29
CN108028814B (zh) 2021-01-05
KR20180034441A (ko) 2018-04-04
EP3314832A1 (de) 2018-05-02
CN108028814A (zh) 2018-05-11

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