EP3267586A1 - Ladungspumpentreiberschaltung - Google Patents

Ladungspumpentreiberschaltung Download PDF

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Publication number
EP3267586A1
EP3267586A1 EP16305854.8A EP16305854A EP3267586A1 EP 3267586 A1 EP3267586 A1 EP 3267586A1 EP 16305854 A EP16305854 A EP 16305854A EP 3267586 A1 EP3267586 A1 EP 3267586A1
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EP
European Patent Office
Prior art keywords
signal
current
charge pump
voltage
control
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Granted
Application number
EP16305854.8A
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English (en)
French (fr)
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EP3267586B1 (de
Inventor
Pierre Pascal SAVARY
Dominique Delbecq
Birama GOUMBALLA
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NXP USA Inc
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NXP USA Inc
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Priority to EP16305854.8A priority Critical patent/EP3267586B1/de
Priority to US15/410,890 priority patent/US10211840B2/en
Priority to CN201710530170.4A priority patent/CN107592109B/zh
Publication of EP3267586A1 publication Critical patent/EP3267586A1/de
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0898—Details of the current generators the source or sink current values being variable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number

Definitions

  • This invention relates to a charge pump driver circuit.
  • this invention relates to a charge pump driver circuit arranged to output a charge pump control voltage signal for a charge pump within a phase-locked loop.
  • Radar circuits often use a phase-locked loop (PLL) to generate a ramp modulated signal.
  • PLL phase-locked loop
  • the charge pump is used to drive a control port of a voltage controlled oscillator (VCO).
  • VCO voltage controlled oscillator
  • the voltage range of the varactor within the VCO can extend beyond the maximum voltage tolerated by the (high-speed) output bipolar transistor of the charge pump. Accordingly, in order to maximize the frequency coverage of the PLL, the output voltage of the charge pump must exceed the maximum voltage of the charge pump transistors.
  • FIG. 1 illustrates a simplified circuit diagram of a charge pump circuit 100.
  • the charge pump circuit 100 consists of a pair of bipolar transistors 110, 120 having emitter terminals coupled to a pulse current source 130.
  • a collector terminal of the first bipolar transistor 110 is coupled to a trickle current source 140 and to an output node 105 of the charge pump circuit 100.
  • a collector terminal of the second bipolar transistor 120 is coupled to a supply rail 150.
  • a first voltage control signal 115 is received at a base terminal of the first bipolar transistor 110, and is arranged to control the switching of the first bipolar transistor 110.
  • a second voltage control signal 125 is received at a base terminal of the second bipolar transistor 120, and is arranged to control the switching of the second bipolar transistor 120.
  • the first voltage control signal 115 is generated to control the first bipolar transistor 110 such that when the first bipolar transistor 110 is 'off the trickle current from the trickle current source 140 flows through the output node 105 of the charge pump circuit 100. Conversely, when the first bipolar transistor 110 is 'on', the current flowing to the output node 105 will equal the difference between the pulse current from the pulse current source 130 and the trickle current from the trickle current source 140.
  • the second voltage control signal 125 is generated to control the second bipolar transistor 120 to provide a current path for the pulse current from the pulse current source 130 when the first bipolar transistor 110 is off, in order to allow the pulse current source 130 to always be on. Accordingly, the first and second voltage control signals 115, 125 may be viewed as differential voltage signals arranged to control the first and second bipolar transistors 110, 120 in a differential manner.
  • the voltage signals 115, 125 received at the base terminals of the bipolar transistors 110, 120 are generated by way of respective first and second current signals 112, 122 injected into the voltage signal nodes and a resistance network 160 coupled between the voltage signal nodes and a reference voltage (e.g. ground).
  • a reference voltage e.g. ground
  • the full voltage range for driving the varactor within the VCO might be, for example, 0.4V to 4.5V.
  • the charge pump circuit 100 should be capable of generating an output voltage V out of a corresponding range: 0.4V to 4.5V.
  • the charge pump circuit 100 should be able to generate a ramped output voltage signal whereby during the 'ramp up' phase the voltage at the output node 105 increases up to the maximum output voltage of 4.5V, whilst during 'the ramp down' phase the voltage at the output node 105 decreases down to the minimum output voltage of 0.4V.
  • the voltage signal at the output node 105 is achieved by generating current pulses at the output node 105 that are converted into a voltage signal by a filter (not shown).
  • the BICMOS millimetre wave bipolar transistors 110, 120 are unable to tolerate voltage levels as high as 4.5V, and may be limited to voltage levels of, for example, 3.9V or less. Accordingly, in order to achieve the high-end output voltage level of 4.5V at the output node 105, the voltage at the emitter terminal of the first bipolar transistor 110 must be at least 0.6V in order to limit the voltage across the first bipolar transistor 110 to 3.9V. Such a high voltage level at the emitter terminal of the first bipolar transistor would result in a minimum achievable output voltage V out at the output node 105 of 0.8V.
  • the present invention provides a charge pump driver circuit, a phase-locked loop and a method of generating a charge pump control voltage signal as described in the accompanying claims.
  • a charge pump driver circuit for generating a charge pump control voltage signal used for controlling a bipolar transistor within a charge pump circuit.
  • a feedback current is generated dependent on the voltage level of a charge pump output signal.
  • the feedback current is injected into a resistive path used to convert a control current signal into the charge pump control voltage signal.
  • the voltage at the emitter terminal of a bipolar transistor within the charge pump circuit may be scaled with the voltage level of the output signal to enable a large target output voltage range to be achieved at the output of the charge pump circuit, without the voltage across the bipolar transistor exceeding a maximum tolerated voltage.
  • the PLL 200 includes a phase detector 210, a charge pump module 220, a loop filter 230 and a voltage controlled oscillator (VCO) 240, all coupled in series.
  • VCO voltage controlled oscillator
  • the VCO 240 In response to a voltage signal 235 output by the loop filter 230 at its control port, the VCO 240 outputs an oscillating output signal 245 having an oscillation frequency dependent on the voltage signal 235.
  • the output signal 245 is fed back to the phase detector 210 as a feedback signal 255 via a feedback path.
  • a programmable divider 250 is provided within the feedback path and arranged to receive the output signal 245, divide the frequency of the output signal 245 by a programmed amount and output the divided frequency signal as the feedback signal 255.
  • the phase detector 210 compares the phase of the feedback signal 255 to the phase of a reference signal 205, and outputs a charge pump control signal 215 to the charge pump module 220.
  • the charge pump control signal 215 generated by the phase detector 210 typically consists of voltage pulses in response to detecting phase differences between the feedback signal 255 and the reference signal 205.
  • the phase detector 210 is arranged to generate a pulse-width modulated charge pump control signal 215 having a pulse width dependent on the phase difference between the feedback signal 255 and the phase of a reference signal 205.
  • the charge pump module 220 responds to voltage pulses received from the phase detector 210 by outputting a signal 225 consisting of current pulses to the loop filter 230.
  • the loop filter 230 'averages' the current pulses to generate a DC (continuous) voltage signal 235 at the control port of the VCO 240.
  • the charge pump module 220 consists of a charge pump circuit 310 arranged to generate the output signal 225 used to drive the control port of the VCO 240.
  • the charge pump module 220 further includes a charge pump driver circuit 320 arranged to output a charge pump control voltage signal 325 to the charge pump circuit 310.
  • the charge pump driver circuit 320 includes a control stage 340 arranged to receive as an input signal the charge pump control signal 215 and to generate a control current signal 345 in accordance with the input signal 215.
  • the charge pump driver circuit 320 further includes an output stage 350 arranged to receive at an input node 352 thereof the control current signal 345 output by the control stage 340 and to generate the charge pump control voltage signal 325 based on the control current signal 345 output by the control stage 340.
  • the output stage 350 includes a resistance network 360 coupled between the input node 352 and a reference voltage node (e.g. ground), and arranged to provide a resistive path through which the control current signal 345 flows.
  • the resistance network 360 is arranged to convert the control current signal 345 into a voltage signal at the input node 352 of the output stage 350, and the output stage 350 is arranged to generate the charge pump control voltage signal 325 based on the voltage level at the input node 352 thereof.
  • FIG. 4 illustrates a simplified graph showing an example of voltage over time for the output signal 225 of the charge pump circuit 310 used to drive the control port of the VCO 240.
  • the charge pump control signal 215 causes the charge pump circuit 320 to drive the voltage of the output signal 225 up until it reaches a maximum voltage level (V out_max ) 415.
  • V out_max a maximum voltage level
  • the charge pump control signal 215 causes the charge pump module 220 to drive the voltage of the output signal 225 down until it reaches a minimum voltage level (V out_min ) 425.
  • the up and down voltage ramps may have different gradient slopes.
  • the output voltage signal 225 is achieved by generating current pulses at the output node of the charge pump that are converted in to a voltage signal by the filter 230 ( Figure 2 ).
  • the full voltage range for driving the varactor within the VCO 240 might be, for example, 0.4V to 4.5V. Accordingly, in order to maximize the frequency coverage of the PLL 200, the charge pump should be capable of an output voltage range of 0.4V to 4.5V.
  • the voltage across the bipolar transistor 315 required to achieve the maximum voltage level (V out_max ) 415 of 4.5V would be 4.3V, in excess of the maximum voltage of 3.9V that the bipolar transistor 315 is able to tolerate.
  • the minimum achievable voltage at the output of the charge pump circuit 310 is limited to 0.8V, greater than the target minimum voltage level (V out_min ) 425 of 0.4V.
  • V e V b ⁇ V be
  • the voltage V be across the base and emitter terminals of a bipolar transistor is constant (under fixed conditions, e.g. temperature, current, etc.). Accordingly, the voltage V e at the emitter terminal of the bipolar transistor 315, and thus across the pulse current source 312, may be controlled using the voltage V b at the base terminal of the bipolar transistor 315; i.e. by controlling the voltage level of the charge pump control voltage signal 325.
  • the resistance network 360 of the output stage 350 of the charge pump driver circuit 320 is arranged to convert the control current signal 345 into a voltage signal at the input node 352 of the output stage 350, and the output stage 350 is arranged to generate the charge pump control voltage signal 325 based on the voltage level at the input node 352 thereof.
  • the charge pump driver circuit 320 further includes a current generator component 330 arranged to receive an indication 370 of the voltage level of the output signal 225 used to drive the control port of the VCO 240, and to generate a feedback current 335 dependent on the voltage level of the output signal 225.
  • the feedback current 335 is injected into the resistive path of the resistance network 360 through which the control current signal 345 flows.
  • the voltage across the resistance network 360, and thus of the charge pump control voltage signal 325 received at the base terminal of the bipolar transistor 315 of the charge pump circuit 310, is further dependent on the feedback current I f(Vout) 335, and thus dependent on the voltage level of the output signal 225 used to drive the control port of the VCO 240.
  • the voltage at the emitter terminal of the bipolar transistor 315 may be scaled with the voltage level of the output signal 225 to enable the target output voltage range of 0.4V to 4.5V to be achieved at the output of the charge pump circuit 310, without the voltage V ce across the bipolar transistor 315 exceeding the maximum tolerated voltage of 3.9V.
  • FIG. 5 illustrates a simplified circuit diagram of an example of the charge pump module 220 of Figures 2 and 3 , and in particular of the current generator component 330 and the output stage 350 of the charge pump driver circuit 320, and the charge pump circuit 310.
  • the charge pump circuit 310 consists of a pair of bipolar transistors 315, 317 having emitter terminals coupled to the pulse current source 312.
  • a collector terminal of the first bipolar transistor 315 is coupled to the trickle current source 314 and to an output node 505 of the charge pump circuit 310.
  • a collector terminal of the second bipolar transistor 317 is coupled to a supply rail 550, which for the illustrated example consists of a 3.3V supply rail.
  • a first voltage control signal 515 is received at a base terminal of the first bipolar transistor 315 of the charge pump circuit 310, and is arranged to control the switching of the first bipolar transistor 315.
  • a second voltage control signal 525 is received at a base terminal of the second bipolar transistor 317 of the charge pump circuit 310, and is arranged to control the switching of the second bipolar transistor 317.
  • the first voltage control signal 515 is generated to control the first bipolar transistor 315 such that when the first bipolar transistor 315 is 'off the trickle current from the trickle current source 314 flows through the output node 505 of the charge pump circuit 310. Conversely, when the first bipolar transistor 315 is 'on', the current flowing to the output node 505 will equal the difference between the pulse current from the pulse current source 312 and the trickle current from the trickle current source 314.
  • the second voltage control signal 525 is generated to control the second bipolar transistor 317 to provide a current path for the pulse current from the pulse current source 312 when the first bipolar transistor 315 is off, in order to allow the pulse current source 312 to constantly be on. Accordingly, the first and second voltage control signals 515, 525 may be viewed as differential voltage signals arranged to control the first and second bipolar transistors 315, 317 in a differential manner.
  • the output stage 350 of the charge pump driver circuit 320 is arranged to receive the control current signal 345 from the control stage 340.
  • the control current signal 345 consists of differential, pulse width modulated current signals 512,522.
  • the output stage 350 is arranged to generate the voltage signals 515, 525 at output nodes 555 thereof by way of the resistance network 360 coupled between the input nodes 352 of the output stage 350 and a reference voltage node, which in the illustrated example consists of a ground node 500. Accordingly the first voltage control signal 515 at the base terminal of the first bipolar transistor 315 is dependent on the respective current signal 512 and the resistive path provided by the resistance network 360 through which the current signal 512 flows. Similarly, the second voltage signal 525 at the base terminal of the second bipolar transistor 317 is dependent on the respective current signal 522 and the resistive path provided by the resistance network 360 through which the current signal 522 flows.
  • the charge pump driver circuit 320 further includes a current generator component 330 arranged to receive an indication 370 of the voltage level of the output signal 225 ( Figure 2 ) at the output node 505 of the charge pump circuit 310 used to drive the control port of the VCO 240, and to generate a feedback current 335 dependent on the voltage level of the output signal 225.
  • the feedback current 335 is injected into the resistive paths of the resistance network 360 through which the current signals 512, 522 flow. In this manner, the voltage across the resistance network 360, and thus at the input nodes 352 of the output stage 350, is further dependent on the feedback current 335, and thus dependent on the voltage level of the output signal 225 used to drive the control port of the VCO 240.
  • the current generator component 330 is arranged to generate the feedback current I f(Vout) 335 having a positive slope amplitude profile with respect to the voltage V out of the output signal 225. In this manner, the resulting voltage across the resistance network 360, and thus at the input nodes 352 of the output stage 350, will also have a positive slope profile with respect to the voltage V out of the output signal 225.
  • the combined current I C 585 is the sum of the feedback current I f(Vout) 335 and either I 1 512 or I 2 522, depending on at what point of its pulse cycle the differential control current signal 345 is in.
  • I 1_on the first current component I1 512 when I 1 is 'on'
  • I 2_on the second current component I 2 522 when I 2 is 'on'
  • Equation 5 it can be seen that for a given output voltage, the voltage across the first bipolar transistor 315 of the charge pump circuit 310 may be dynamically controlled through the feedback current I f(Vout) 335.
  • FIG. 6 illustrates a simplified graph showing an example of voltage levels within the charge pump circuit 310 with respect to the output signal voltage V out 225.
  • V out_min minimum voltage level
  • the feedback current I f(Vout) 335 is generated such that the voltage V e at the common emitter node of the bipolar transistors 315, 317, represented by the first area 610 of the graph in Figure 6 , is at a first, minimum voltage level of, in the illustrated example, 0.2V, with a 0.2V collector-emitter voltage V ce across the first bipolar transistor 315 represented by the second area 620 of the graph in Figure 6 .
  • the feedback current I f(Vout) 335 is generated such that the voltage V e 610 at the common emitter node of the bipolar transistors 315, 317 is at a second, maximum voltage level of, in the illustrated example, 0.6V, with a 3.9V collector-emitter voltage V ce 620 across the first bipolar transistor 315.
  • the feedback current I f(Vout) 335 is adapted in response to the voltage V out of the output signal 225 such that voltage V e 610 at the common emitter node of the bipolar transistors 315, 317 is 'scaled' with the voltage V out of the output signal 225, enabling a full output voltage range from 0.4V to 4.5V to be achieved, without the collector-emitter voltage V ce 620 across the first bipolar transistor 315 exceeding a maximum tolerated voltage of, for example, 3.9V.
  • the full output voltage range from 0.4V to 4.5V is achievable in a single, uninterrupted and continuous 'sweep'.
  • the feedback current I f(Vout) 335 is automatically adapted in response to the voltage V out of the output signal 225
  • the voltage V e 610 at the common emitter node of the bipolar transistors 315, 317 is automatically scaled in response to the voltage V out of the output signal 225.
  • overvoltage protection of the bipolar transistors 315, 317 is automatically provided, even before any calibration of the charge pump module 220 is performed.
  • the current generator component 330 is arranged to receive a configuration signal 530 and to generate the feedback current 335 further dependent on the received configuration signal 530.
  • the common resistance element R c 590 of the resistance network 360 through which control current signal components 512, 522 flow consists of a configurable (e.g. switched) resistive component.
  • the pulse current source 312 and trickle current source 314 may also be arranged to be configurable.
  • the pulse current source 312 and trickle current source 314 are each programmable by a control signal I cp_ code in order to enable the trickle and pulse currents to be programmed depending on a required output current strength of the charge pump circuit 310.
  • the control signal I cp_ code allows the PLL bandwidth to be adjusted, depending on the VCO gain (or sensitivity). As the pulse current through the pulse current source 312 increases, the voltage across the pulse current source 312, and thus at the emitter of the bipolar transistor 315, will increase and thus need compensating for.
  • the common resistance element R c 590 of the resistance network 360 through which control current signal components 512, 522 flow consists of a configurable (e.g. switched) resistive component configurable by the control signal I cp_ code in order to influence the voltage across the resistance network 360, and thus at the base of the bipolar transistor 315, to compensate for voltage changes across the pulse current source 312 as a result of changes to the pulse current flowing there through.
  • the current generator component 330 is arranged to receive a configuration signal 530 consisting of an inverse of the control signal I cp_ code, to generate the feedback current 335 further dependent on the received inverse of the control signal I cp_ code 530. In this manner, the current generator component 330 is arranged to further adapt the feedback current 335 depending on the configuration of the pulse and trickle current sources in order to further compensate for voltage changes across the pulse current source 312 as a result of changes to the pulse current flowing there through.
  • the graph of Figure 6 shows a first example of voltage levels within the charge pump circuit 310 with respect to the output signal voltage V out 225, for example when the control signal I cp_ code is set to configure low trickle and pulse currents, and thus the voltage across the pulse current source 312 is low, i.e. 0.2 V in the illustrated example.
  • the feedback current I f(Vout) 335 is generated such that the voltage V e at the common emitter node of the bipolar transistors 315, 317, represented by the first area 610 of the graph in Figure 6 , is at a first, minimum voltage level of 0.2V, with a 0.2V collector-emitter voltage V ce across the first bipolar transistor 315 represented by the second area 620 of the graph in Figure 6 .
  • the feedback current I f(Vout) 335 is generated such that the voltage V e 610 at the common emitter node of the bipolar transistors 315, 317 is at a second, maximum voltage level of 0.6V, with a 3.9V collector-emitter voltage V ce 620 across the first bipolar transistor 315.
  • Figure 7 illustrates a simplified graph showing an alternative example of voltage levels within the charge pump circuit 310 with respect to the output signal voltage V out 225, for example when the control signal I cp_ code is set to configure high trickle and pulse currents, and thus the voltage across the pulse current source 312 is high, i.e. 0.5 V in the illustrated example.
  • the feedback current I f(Vout) 335 is generated such that the voltage V e at the common emitter node of the bipolar transistors 315, 317, represented by the first area 710 of the graph in Figure 7 , is at a first, minimum voltage level of 0.5V, with a 0.2V collector-emitter voltage V ce across the first bipolar transistor 315 represented by the second area 720 of the graph in Figure 7 .
  • the feedback current I f(Vout) 335 is generated such that the voltage V e 710 at the common emitter node of the bipolar transistors 315, 317 is at a second, maximum voltage level of 0.9V, with a 3.6V collector-emitter voltage V ce 720 across the first bipolar transistor 315.
  • FIG. 8 there is illustrated a simplified flowchart 800 of an example of a method of generating a charge pump control voltage signal, such as may be implemented within the charge pump module 220 illustrated in Figure 3 .
  • the method starts at 810 and moves on to 820 where an input signal is received.
  • a control current signal is then generated at 830 in accordance with the received input signal.
  • the control current signal is then applied to a resistive path between an input node and a reference voltage node such that the control current signal flows through the resistive path, at 840.
  • An indication of a voltage level of a charge pump output signal is received at 850, and a feedback current is generated at 860 dependent on the indicated voltage level of the output signal.
  • the feedback current is then injected into the resistive path, at 870.
  • the charge pump control voltage signal is then generated based on a voltage level at the input node at 880, the voltage level at the input node being co-dependent on the control current signal flow through the resistive path and the injected feedback current within the resistive path.
  • the method then ends at 890.
  • the method may further comprise receiving a configuration signal and generating the feedback current further dependent on the configuration signal.
  • the method may further comprise configuring at least one resistive component within the resistive path.
  • the method may comprise generating a differential current control signal comprising a first current component and a second current component, applying the first current component of the differential current control signal to a first resistive path between a first input node and the reference voltage node, applying the second current component of the differential current control signal to a second resistive path between a second input node and the reference voltage node, injecting the feedback current into the first and second resistive paths, and generating a first charge pump control voltage signal based on a voltage level at the first input node and a second charge pump control voltage signal based on a voltage level at the second input node.
  • the first and second resistive paths may share a common path section through which both the first and second current components of the differential current control signal flow, and the method may comprise injecting the feedback current into the common path section.
  • the method may comprise generating the feedback current comprising a positive slope amplitude profile with respect to the voltage level of the charge pump output signal.
  • connections as discussed herein may be any type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise, the connections may for example be direct connections or indirect connections.
  • the connections may be illustrated or described in reference to being a single connection, a plurality of connections, unidirectional connections, or bidirectional connections. However, different embodiments may vary the implementation of the connections. For example, separate unidirectional connections may be used rather than bidirectional connections and vice versa.
  • plurality of connections may be replaced with a single connection that transfers multiple signals serially or in a time multiplexed manner. Likewise, single connections carrying multiple signals may be separated out into various different connections carrying subsets of these signals. Therefore, many options exist for transferring signals.
  • Each signal described herein may be designed as positive or negative logic.
  • the signal In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero.
  • the signal In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one.
  • any of the signals described herein can be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.
  • the terms 'assert' or 'set' and 'negate' are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.
  • logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements.
  • architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality.
  • any arrangement of components to achieve the same functionality is effectively 'associated' such that the desired functionality is achieved.
  • any two components herein combined to achieve a particular functionality can be seen as 'associated with' each other such that the desired functionality is achieved, irrespective of architectures or intermediary components.
  • any two components so associated can also be viewed as being 'operably connected,' or 'coupled,' to each other to achieve the desired functionality.
  • the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device.
  • the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word 'comprising' does not exclude the presence of other elements or steps then those listed in a claim.
  • the terms 'a' or 'an,' as used herein, are defined as one or more than one.
EP16305854.8A 2016-07-07 2016-07-07 Ladungspumpentreiberschaltung Active EP3267586B1 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP16305854.8A EP3267586B1 (de) 2016-07-07 2016-07-07 Ladungspumpentreiberschaltung
US15/410,890 US10211840B2 (en) 2016-07-07 2017-01-20 Charge pump driver circuit
CN201710530170.4A CN107592109B (zh) 2016-07-07 2017-06-30 电荷泵驱动器电路

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EP16305854.8A EP3267586B1 (de) 2016-07-07 2016-07-07 Ladungspumpentreiberschaltung

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DE112015006542T5 (de) * 2015-06-26 2018-02-22 Olympus Corporation Phasenregelschleifensender mit abgestimmten Versatz

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US6265946B1 (en) * 1998-12-31 2001-07-24 Lsi Logic Corporation Differential mode charge pump and loop filter with common mode feedback
US20070090885A1 (en) * 2005-10-20 2007-04-26 Matsushita Electric Industrial Co., Ltd. Charge pump circuit and phase-locked loop circuit
US20090189654A1 (en) * 2008-01-25 2009-07-30 Clements Steven M Common-Mode Feedback Method Using a Current Starved Replica Biasing

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US6181210B1 (en) * 1998-09-21 2001-01-30 Broadcom Corporation Low offset and low glitch energy charge pump for PLL-based timing recovery systems
US6249164B1 (en) * 1998-09-25 2001-06-19 International Business Machines Corporation Delay circuit arrangement for use in a DAC/driver waveform generator with phase lock rise time control
US7567105B2 (en) * 2004-12-28 2009-07-28 Texas Instruments Incorporated High speed controller area network receiver having improved EMI immunity
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US6265946B1 (en) * 1998-12-31 2001-07-24 Lsi Logic Corporation Differential mode charge pump and loop filter with common mode feedback
US20070090885A1 (en) * 2005-10-20 2007-04-26 Matsushita Electric Industrial Co., Ltd. Charge pump circuit and phase-locked loop circuit
US20090189654A1 (en) * 2008-01-25 2009-07-30 Clements Steven M Common-Mode Feedback Method Using a Current Starved Replica Biasing

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CN107592109A (zh) 2018-01-16
EP3267586B1 (de) 2020-06-03
CN107592109B (zh) 2023-08-01
US20180013436A1 (en) 2018-01-11
US10211840B2 (en) 2019-02-19

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