EP3259751B1 - Appareil d'affichage et son procédé de commande - Google Patents
Appareil d'affichage et son procédé de commande Download PDFInfo
- Publication number
- EP3259751B1 EP3259751B1 EP16807831.9A EP16807831A EP3259751B1 EP 3259751 B1 EP3259751 B1 EP 3259751B1 EP 16807831 A EP16807831 A EP 16807831A EP 3259751 B1 EP3259751 B1 EP 3259751B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- gate
- driving voltage
- gate driving
- backlight
- driver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 22
- 230000004044 response Effects 0.000 description 14
- 239000003990 capacitor Substances 0.000 description 12
- 239000004973 liquid crystal related substance Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 238000010276 construction Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 238000012938 design process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 206010047571 Visual impairment Diseases 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
- G09G3/342—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Definitions
- Exemplary embodiments relate to a display apparatus and a method for controlling the same, and more particularly, to a display apparatus which compensates for brightness non-uniformity of a display panel and a method for controlling the same.
- LCD liquid crystal display
- OA office automation
- audio/video devices audio/video devices
- diverse user terminal apparatuses The LCD displays an image by controlling an amount of a light beam transmitted according to an image signal applied to a plurality of control switches arranged in a matrix form.
- the LCD is a light receiving element which cannot emit light. Accordingly, the LCD includes a backlight having a high transmittance on a rear surface of a liquid crystal panel such that a user is able to view an image displayed on the LCD.
- a resistance-capacitance (RC) delay of each gate line increases accordingly.
- RC delay time taken to turn on the last end pixel of the gate line increases accordingly.
- the related art has used a method of connecting a gate driver integrated circuit (IC) to one side surface of a display panel, connecting another gate driver IC for compensating for an RC delay to the other side surface of the display panel, and applying gate power to each line of the display panel through the gate driver ICs on both side surfaces.
- IC gate driver integrated circuit
- the above-described method requires that a bezel for the gate driver IC is present on each of the side surfaces of the display panel.
- a bezel mounted on a connection end of each display apparatus interrupts presentation of a view.
- the number of driver ICs is increased by two, and, thus, this negatively affects price competitiveness of a product.
- Patent publication US 2013/0147856 A1 discloses a display device including a feedback circuit which determines an RC delay affecting a gate pulse applied to the pixels of a gate line. Compensation of the distortion due to the RC delay is achieved by adjusting a gate pulse voltage square waveform, by applying an increased voltage set according to the feedback in a starting section of the gate pulse.
- Patent publication US 2010/0245317 A1 discloses a display device including a feedback circuit which determines an RC delay affecting a gate pulse applied to the pixels of a gate line. Compensation of the distortion due to the RC delay is achieved by adjusting a width of the gate pulses, so as to avoid times in which consecutive rows are simultaneously active.
- Patent publication US 2014/327708 discloses an LCD display device with a backlight unit including a higher density of light sources in correspondence to pixels located far away from the scan driver, to compensate for a dropping luminance profile along the scan lines.
- Patent publication EP 2 096 621 A2 discloses a drive circuit of display panel and display apparatus.
- Patent publication US 2013/0235011 A1 discloses an LCD panel driving method, display circuit, and LCD device.
- Exemplary embodiments may address at least the above problems and/or disadvantages and other disadvantages not described above. Also, exemplary embodiments are not required to overcome the disadvantages described above, and may not overcome any of the problems described above.
- One or more exemplary embodiments provide a display apparatus which compensates for bright non-uniformity without an RC delay even though a gate driver IC is mounted on only one side surface of a display panel and a method for controlling the same.
- the backlight driver may drive the backlight unit such that brightness of the backlight supplied to the backlight unit increases in a direction away from the gate driver IC.
- the controller may generate a synchronization signal every time the gate driving voltage is applied to the gate lines and transmit the generated synchronization signal to the backlight driver.
- the backlight driver may drive the backlight unit to supply the backlight upon the gate driving voltage being applied based on the received synchronization signal.
- the apparatus may further include a storage configured to include a lookup table where each of the plurality of pixels of the display panel is matched with a brightness value of a light source to be irradiated to each of the pixels in order to maintain brightness of the display panel consistently according to a position of each of the pixels of the display panel.
- the backlight driver may drive the backlight unit by using the pre-stored Lookup Table.
- the backlight driver may increase the brightness of the backlight linearly.
- the method may include increasing a brightness of a backlight supplied from a backlight unit in a direction away from the gate driver IC.
- a difference in a display quality between a left-side pixel and a right-side pixel of a display panel due to a signal delay may be improved even though a gate driver IC is mounted on only one side surface of the display panel, and thus, a size of a bezel of the display panel may be reduced.
- a term including an ordinal such as, 'first,' 'second,' etc., may be used to distinguish elements.
- the ordinal is used to distinguish the same or similar elements and does not limit the meaning of the term. For instance, ordinals do not affect an order of use or an order of arrangement of elements expressed with the ordinals. Respective ordinals may be replaced with each other, if necessary.
- the term 'module,' 'unit,' or 'part' refers to an element which performs at least one function or operation.
- the 'module,' 'unit,' or 'part' may be realized as hardware, software, or combination thereof.
- a plurality of 'modules,' 'units,' and 'parts' may be integrated into at least one module or chip such that it may include at least one processor except for a case where respective 'modules,' 'units,' and 'parts' need to be realized as discrete specific hardware.
- connection When it is described that one part is connected to another part, the connection includes a direct connection of the parts and an indirection connection through other medium.
- the description that a certain part includes an element signifies that the part may further include other elements rather than signifying that the part excludes other elements, unless otherwise described.
- FIG. 1A is a block diagram illustrating a structure of a display apparatus according to an exemplary embodiment.
- FIG. 1B illustrates a display panel according to an exemplary embodiment.
- a display apparatus 100 may include various types of image-processable monitors including a television (TV), a smart phone, a portable terminal, a mobile terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a computer, a laptop computer, a notepad, a wireless broadband Internet (WiBro) terminal, a tablet personal computer (PC), a smart TV, and the like.
- TV television
- smart phone portable terminal
- mobile terminal a personal digital assistant
- PMP portable multimedia player
- PMP portable multimedia player
- computer a laptop computer
- a notepad a wireless broadband Internet (WiBro) terminal
- WiBro wireless broadband Internet
- PC tablet personal computer
- the display apparatus 100 includes a display panel 110, a source driver IC 120, a gate driver IC 130, and a controller 140.
- the display panel 110 displays image data.
- the display panel 110 may include a gate-in-panel (GIP) structure where a gate line is installed in a panel.
- the display panel 110 may include a thin film transistor-LCD (TFT-LCD) panel, but this is not limiting. That is, a display panel of an exemplary embodiment may include any other appropriate display panel.
- GIP gate-in-panel
- TFT-LCD thin film transistor-LCD
- a TFT-LCD has a matrix-type pixel structure.
- a plurality of gate lines intersect a plurality of data lines perpendicularly, and a pixel region is formed between each gate line and each data line.
- the pixel region includes a TFT and a liquid crystal to display a screen.
- a pixel includes an electrode layer including an upper electrode and a lower electrode.
- the upper electrode refers to a pixel electrode
- the lower electrode refers to a common electrode.
- An on/off state of the TFT is controlled depending upon a level of a gate voltage applied to the gate lines.
- a data voltage applied through the data lines is supplied to a pixel electrode of a corresponding pixel, and display of the pixel is performed according to a difference between the data voltage and a voltage applied to a common electrode.
- the display panel 110 is connected with the source driver IC 120 and the gate driver IC 130.
- a gate driving voltage and a data voltage are supplied to the display panel 110 through the gate driver IC 130 and the source driver IC 120, respectively.
- FIG. 1B illustrates a display panel 110 according to an exemplary embodiment.
- the display panel 110 includes an LCD panel in which liquid crystal cells are arranged in a matrix form.
- the display panel 110 includes a plurality of gate lines GL1 and GL2 to GLN, a plurality of data lines DL1 and DL2 to DLN, a plurality of TFTs T1 and T2 to TN, and a plurality of capacitors C1 and C2 to CN. Although only one gate line is illustrated to have TFTs and capacitors, the remaining data lines GL2 to GLN have similar components.
- the plurality of gate lines GL1 and GL2 to GLN receives a plurality of gate signals from a gate driver IC 130.
- the plurality of data lines DL2, DL2,... and DLN crosses the plurality of gate lines and receives a data voltage from a source driver IC 120 corresponding to a data signal.
- the plurality of TFTs T1, T2,..., and TN is formed at an intersection of the gate lines GL1 and GL2 to GLN and the data lines DL1, DL2,..., and DLN.
- a gate electrode of the each TFT is connected to the gate lines GL1 and GL2 to GLN, and a source electrode of the TFT is connected to the data lines DL1, DL2,... and DLN.
- Each pixel area (not shown) is formed at an intersection of the gate lines GL1 and GL2 to GLN and the data lines DL1, DL2,... and DLN, and a pixel electrode is formed in the pixel area.
- the plurality of capacitors C1, C2, ...., CN includes the pixel electrode, the common electrode which receives a common voltage from the voltage generator 96, and liquid crystal which is interposed between the pixel electrode and the common electrode.
- a predetermined signal is applied from the gate lines GL1 and GL2 to GLN and the data lines DL1, DL2,... and DLN to turn on the TFTs T1, T2,..., and TN
- a data voltage which is supplied to the data lines DL1, DL2,..., and DLN is applied to a pixel electrode through the TFTs.
- An electric field which falls under a difference between a data voltage applied to the pixel electrode and a common voltage supplied by the voltage generator 96 is applied to the capacitors C1, C2, ...., CN and light passes through at the transmissivity ratio corresponding to the strength of the electric field.
- An array structure of a source driver IC and a gate driver IC in a display panel may be divided into a single bank structure where one source driver IC and one gate driver IC are arrayed on only a certain side of the display panel (see reference numerals 80, 82 in FIG. 1B ) and a dual bank structure where two source driver ICs and two gate driver ICs are arrayed on both sides of the display panel. As shown in FIG. 1B , there is no source driver IC and no gate driver IC on sides 84, 86 of the display panel 110.
- the single bank structure is more desirable in this regard, but the single bank structure is not widely used due to a signal delay which occurs at a gate line in a display panel in the single bank structure.
- a gate driving voltage which is actually measured at the rightmost position of the gate line (a position of CN on one of the corresponding gate lines closest to a right side 84 in FIG. 1B ) has a waveform which is delayed more than a gate voltage which is actually measured at the leftmost position of the gate line (a position of C1 on one of the corresponding gate lines closest to a left side 80 in FIG. 1B ).
- a kickback voltage of a pixel region at each position varies depending upon the delay of the gate driving voltage since a charge is supplied through a TFT of a pixel at a corresponding position during a predetermined period of time of applying a delayed waveform of the gate driving voltage. For example, even though a data voltage in the same gradation is applied to a pixel of one line, a left-side pixel which is closest to the gate driver IC and a right-side pixel which is farthest from the gate driver IC are charged with different voltages.
- a difference in the charged voltages causes deterioration of a display quality due to a difference in brightness of a left-side pixel, e.g., corresponding to C1, and a right-side pixel, e.g., corresponding to CN, of the display panel, a direct current (DC) stress with respect to a liquid crystal material, and an afterimage problem, which degrades image quality.
- the controller 140 is a component for resolving the above-described problems. The controller 140 controls overall operations of the display apparatus 100.
- the controller 140 may receive a feedback signal Fb on a gate driving voltage applied to at least one pixel among a plurality of pixels and detect distortion of the gate driving voltage applied to the at least one pixel based on the feedback. In order to compensate for the distortion of the gate driving voltage, the controller 140 may adjust a level of a gate driving voltage applied to the gate lines and apply the adjusted gate driving voltage to the gate lines.
- the pixel which supplies the feedback voltage to the controller 140 is a pixel where the most intense distortion of the gate driving voltage occurs among the pixels included in the gate lines, that is, a pixel located at a position which is farthest from the gate driver IC 130.
- FIG. 2 is a block diagram illustrating a detailed structure of a display apparatus according to an exemplary embodiment.
- a timing controller 150 controls a timing at which a data voltage and a gate driving voltage are applied.
- the timing controller 150 receives RGB data, that is, a chrominance signal, a horizontal synchronization (H-SYNC) signal, a vertical synchronization (V-SYNC) signal, a clock signal (MCLK), and a data enable signal (DE).
- the timing controller 150 may receive voltages supplied from a voltage generator (not shown), adjust a timing of the signals, and generate signals for driving the display panel 110.
- the timing controller 150 converts a format of the RGB data to correspond to a specification of an interface of the source driver IC 120 and outputs the converted RGB data through the source driver IC 120.
- the timing controller 150 outputs a data control signal (for example, an output start signal (TP), a horizontal start signal (STH), and a clock signal (HCLK)) through the source driver IC 120 and outputs a gate control signal (for example, a vertical start signal (STV), a gate clock signal (CPV), and an output enable signal (OE)) through the gate driver IC 130.
- TP output start signal
- STH horizontal start signal
- HCLK clock signal
- a gate control signal for example, a vertical start signal (STV), a gate clock signal (CPV), and an output enable signal (OE)
- the source driver IC 120 may receive a gradation voltage generated in the voltage generator through the timing controller 150, select a proper gradation voltage according to the RGB data, convert the selected gradation voltage into a voltage which may be applied to the display panel 110, and apply the converted voltage to each data line of the display panel 110.
- the source driver IC 120 selects gradation voltages corresponding to the RGB data among the generated gradation voltages in response to the data control signal (TP, STH, and HCLK) transmitted from the timing controller 150 and apply the selected gradation voltages to each data line of the display panel 110.
- the data control signal TP, STH, and HCLK
- the gate driver IC 130 may receive a gate voltage generated in the voltage generator through the timing controller 150, convert the received gate voltage into a voltage which may be applied to the display panel 110, and apply the converted voltage to each gate line of the display panel 110.
- the gate driver IC 130 receives a gate-on voltage (Von) and a gate-off voltage (Voff) and outputs a gate driving voltage having the gate-on voltage (Von) sequentially in response to the gate control signal (STV, CPV, and OE) transmitted from the timing controller 150.
- the gate driving voltage is applied to the gate lines of the display panel 110 sequentially and scans the gate lines sequentially.
- the display apparatus 100 may further include a regulator configured to convert an input voltage into a gate-on voltage (Von) and a gate-off voltage (Voff) and output the converted voltages.
- the data signals are applied to the data lines in synchronization with the gate signals.
- a TFT connected to the selected gate line is turned on according to the gate signal.
- the applied data signal is charged into a liquid crystal capacitor and a storage capacitor by passing the turned-on TFT.
- the liquid crystal capacitor controls light transmittance of a liquid crystal according to the charged voltage.
- the storage capacitor may maintain a charged state of the liquid crystal capacitor by accumulating the data signal in response to the TFT being turned on and applying the accumulated data signal to the liquid crystal capacitor in response to the TFT being turned off.
- the display panel 110 may display an image in this manner.
- the controller 140 may be disposed between the timing controller 150 and the gate driver IC 130.
- the controller 140 may receive a timing signal for controlling a timing at which the data voltage and the gate driving voltage are applied from the timing controller 150.
- the controller 140 may apply the gate driving voltage of which level has been adjusted to the gate lines according to the timing signal applied from the timing controller 150. As the controller 140 applies the adjusted gate driving voltage to the gate lines, a charging time of each pixel may be compensated according to the original gate driving voltage even though the applied gate driving voltage is distorted.
- the controller 140 may be referred to as 'compensation circuit' in this regard.
- the gate driving voltage may be applied to the gate lines as a square wave.
- the controller 140 may raise a level of a voltage of a section in which the insufficient charging time occurred in the square wave.
- the square wave may raise a level of a voltage of a section after a certain period of time from when a gate is changed from an OFF state to an ON state (OFF-ON section) and a section before a certain period of time from when the gate is changed from the ON state to the OFF state (ON-OFF section).
- the voltage generator may generate and supply a voltage for driving the display panel 110. That is, the voltage generator may generate a gate-on/off voltage, a gradation voltage, and/or a common electrode voltage and supply the generated voltage to the timing controller 150.
- the voltage generator may be the same as the voltage generator 96 of FIG. 1B or different.
- the display panel 110 may receive a backlight from the backlight unit 160 and the backlight driver 170.
- the backlight unit 160 may be disposed on a rear surface of the display panel 110.
- the backlight unit 160 may supply a light with desired brightness to the display panel 110 in response to a driving signal transmitted from the backlight driver 170.
- the backlight unit 160 may include a plurality of light sources.
- the plurality of light sources may include a plurality of light emitting diodes (LEDs) (refer to FIG. 8 ).
- the plurality of LEDs may be connected to each other in series on a printed circuit board (PCB) forming a plurality of blocks.
- PCB printed circuit board
- the backlight driver 170 may generate a clock signal and a brightness data signal which synchronizes with the clock signal in response to an enable signal.
- the brightness data signal includes brightness information for controlling brightness of the backlight unit 160.
- FIG. 3A is a view provided to describe a process where a gate driving voltage is distorted thereby causing an insufficient charging time.
- a gate driving voltage which is applied through the gate driver IC 130 during one horizontal scanning period (one frame) has a waveform 31, e.g., a square wave.
- a pulse of the gate driving voltage is formed with a width allowing a sufficient charging time for each pixel.
- An amplitude of the gate driving voltage is formed to be higher than a gate-on level of a field effect transistor (FET) element.
- FET field effect transistor
- a waveform of the gate driving voltage is changed to a waveform 32 where a high-level section becomes shorter according to the distortion, and, thus, a charging time of a pixel becomes insufficient, which becomes worse as a signal delay becomes greater.
- the distortion appears more intense at a pixel located at a position which is farthest from the gate driver IC 130 among the plurality of pixels of the gate line.
- a sufficient charging time of a pixel is not achieved, deterioration of a contrast ratio and bright non-uniformity may occur.
- problems occur intensely when a data voltage has a broad amplitude, for example, high voltage driving.
- FIG. 3B is a view provided to describe a waveform of a gate driving voltage for compensating for an insufficient charging time, according to an exemplary embodiment.
- the controller 140 may control to raise a level of a voltage of one or more sections 36 in which the insufficient charging time is predicted to occur in a current frame based on a received feedback signal providing information about the previous frame, and apply the higher voltage value in a section of the square wave.
- an amplitude of a section in which an insufficient charging time in a waveform of the gate driving voltage that is, a section in which a loss of charging time occurs due to the distortion, may be higher than the gate-on level voltage.
- the amplitude of the section which the loss of charging time occurs may be formed to be high enough to secure a high-level section for allowing a sufficient charging time despite occurrence of the distortion.
- the controller 140 may apply the gate driving voltage having a waveform 33 for compensating for the signal loss due to the distortion, to each gate line of the display panel 110.
- the gate driving voltage may be changed to a gate driving voltage having a distorted waveform 34 while passing the pixels of the gate line.
- the gate driving voltage having the distorted waveform 34 secures a charging time of the gate driving voltage before distortion even though it is distorted, by having an amplitude of sufficiently high value for a duration of a certain charging time, and thus, a difference in a charging voltage of the pixels due to the RC delay along the gate line may be substantially eliminated.
- the compensated gate driving voltage which may compensate for the distortion will be called 'compensation gate driving voltage' for convenience of description.
- FIG. 4 is a view provided to describe a waveform of a gate driving voltage for compensating for an insufficient charging time at each frame according to feedback, according to an exemplary embodiment.
- the controller 140 may apply the compensation gate driving voltage to each gate line at each frame.
- the compensation gate driving voltage applied to each gate line may have a different form according to a degree of distortion of the gate driving voltage at each frame.
- an OFF-ON section 38 and an ON-OFF section 40 of a waveform 41 of a first gate signal of the gate driving voltage may have a higher value than a gate-on level 44 by an amount of a first height h1.
- an OFF-ON section 38 and an ON-OFF section 40 of a waveform 42 of a second gate signal of the gate driving voltage may have a higher value than the gate-on level 44 by an amount of a second height h2 smaller than the first height h1.
- an OFF-ON section 38 and an ON-OFF section 40 of a waveform 46 of an Nth gate signal of the gate driving voltage may have a higher value than the gate-on level 44 by an amount of the first height h1 or any other appropriate amount. That is, the signal corresponding to the compensation gate driving voltage applied to each frame may have a different waveform with sections having different amplitude or amplitudes, which may be determined by a gate driving voltage which is fed back from a previous frame.
- the controller 140 may receive feedback on a gate driving voltage applied to at least one pixel among the plurality of pixels of the gate line.
- the controller 140 may receive feedback on a gate driving voltage applied to at least one pixel located at a position which is farthest from the gate driver IC 130 among the plurality of pixels of each gate line.
- the controller 140 may receive, as a feedback signal, the gate driving voltage which has been most recently applied, from a pixel at the gate line, and detect the distortion based on the received gate driving voltage.
- the pixel may be a pixel disposed at a farthest position from the gate driver IC, on a gate line, e.g., a pixel corresponding to the capacitor CN.
- the controller 140 may quantify an amount of distortion of the gate driving voltage applied to the pixel by comparison with an undistorted normal gate driving voltage and generate a compensation gate driving to compensate the amount of distortion of the voltage signal amplitude, for example, by adding a comparison difference value to the undistorted voltage signal value.
- the generated compensation gate driving voltage may be applied to a gate line at a subsequent frame to reduce a difference in the charging voltages in the frame.
- a waveform of the compensation gate driving voltage is determined according to the amount of distortion detected based on the feedback on the gate driving voltage, and thus, a compensation gate driving voltage at each frame may have a different form.
- FIGS. 5A and 5B are views provided to describe a method for adjusting brightness according to a position of a backlight in order to maintain brightness of a panel consistently.
- FIG. 5A illustrates brightness of a backlight when a backlight unit for supplying a backlight to a display panel provides consistent brightness regardless of a position of a pixel.
- a level of a driving voltage according to a position of a backlight may be expressed as a graph 50.
- a horizontal axis represents a position of the backlight unit 160, e.g., a position of a light source of the backlight unit, corresponding to each pixel at one gate line
- a vertical axis represents a level of a driving voltage of the backlight driver 170 at each position. That is, the backlight driver 170 applies a consistent driving voltage regardless of a position of the backlight unit 160.
- a difference may occur between the brightness of the backlight unit 160 (graph 54) and the brightness of the display panel 110 (graph 56).
- the brightness of a pixel which is far from the gate driver IC 130 may be relatively lower than the brightness of a pixel which is closer to the gate driver IC 130 according to the difference in the charging time due to the RC delay.
- a brightness difference according to a difference in a charging time may be minimized by applying a different level of driving voltages according to the position of the light source of the backlight unit 160.
- the backlight driver 170 may drive the backlight unit 160 such that the brightness of the backlight supplied to the backlight unit 160 increases in a direction 58 away from the gate driver IC 130.
- the backlight driver 170 may increase the brightness of the backlight linearly or non-linearly.
- an imbalance of the brightness due to the insufficient charging time may be compensated by the backlight 160 which increases the brightness in the direction away from the gate driver IC 130.
- the brightness supplied by the backlight unit 160 may increase in the direction away from the gate driver IC 130 such that the brightness of the display panel 110 (graph 56) is maintained at a consistent level regardless of a distance of a pixel from the gate driver IC 130.
- the backlight driver 170 may compensate for the imbalance between the left-side brightness and the right-side brightness of the display panel 110 by driving the backlight such that the backlight driving voltage is applied differently at each position of the light source of the backlight unit 160.
- a brightness value provided by each light source of the backlight unit 160 to compensate for the imbalance between left-side brightness and right-side brightness of the display panel 110 may be preset and stored in advance, for example, during a manufacturing process.
- the display apparatus 100 may further include a storage device 98 (refer to FIG. 1 ).
- the storage may include a lookup table where each of the plurality of pixels of the display panel is matched with a brightness value of a light source which needs to be irradiated to each of the pixels in order to maintain the brightness of the display panel consistently according to a position of each of the pixels of the display panel.
- FIG. 6 is a view provided to describe a lookup table 60 where backlight brightness values adjusted according to RC delay values are matched with the RC delay.
- the backlight driver 170 may drive the backlight unit 160 by using the lookup table stored in the storage.
- the lookup table matches and stores RC delay values and brightness values of a backlight in such a way that a brightness value of an adjusted backlight increases toward a pixel having a great RC delay value.
- the brightness value of the backlight unit 160 according to the RC delay may be measured and stored as a predetermined value in a design and manufacturing process of the display apparatus 100.
- FIG. 6 illustrates only four RC delay values which are matched with the corresponding brightness values, but brightness values of the light sources corresponding to different ones and/or more RC delay values may be stored.
- a position of a light source may be adjusted, e.g., by a physical position or by appropriate control of activation function, such that the brightness of the pixels of each gate line is consistent.
- a distance between the light sources which supply a backlight to each pixel of the gate lines may be adjusted in such a way that the light sources 800 located closer to the gate driver IC 130 are arranged with a greater distance therebetween, and the light sources 810 located farther away from the gate driver IC 130 are arranged with a smaller distance therebetween.
- the brightness of the backlight by the light sources 810 located farther away from the gate driver IC 130 is made higher than the brightness of the backlight by the light sources 800 located closer to the gate driver IC 130.
- the brightness difference may further offset the brightness difference due to the difference in the charging time and reduce the imbalance of the brightness of the display panel 110.
- the brightness of the backlight unit 160 according to the RC delay may be measured in the design and manufacturing process of the display apparatus 100, and the light sources of the backlight unit 160 may be arranged with the adjusted distance such that the brightness of the display panel 110 is maintained consistently based on the measured brightness values.
- FIG. 7 is a flowchart provided to describe a method for controlling a display apparatus according to an exemplary embodiment.
- the gate driving voltage may be applied as a square wave.
- feedback on a gate driving voltage applied to at least one pixel located at a position which is farthest from the gate driver IC among the plurality of pixels may be received.
- a level of the gate driving voltage applied to the gate lines is adjusted to compensate for the distortion of the gate driving voltage in operation S730. For example, in order to compensate for an insufficient charging time which occurs in at least one pixel due to the distortion of the gate driving voltage, a level of a voltage of a section which the insufficient charging time occurred in a square wave may be raised.
- the adjusted gate driving voltage is applied to the gate lines in operation S740.
- the adjusted gate driving voltage may be applied according to a timing signal applied from a timing controller for controlling a timing at which a data voltage and a gate driving voltage are applied.
- the brightness of a backlight supplied to a backlight unit may be increased in a direction away from the gate driver IC.
- a synchronization signal may be generated every time the gate driving voltage is applied to the gate lines, and the backlight may be supplied upon the gate driving voltage being applied based on the generated synchronization signal.
- the brightness of the backlight may be increased by using a lookup table where each of the plurality of pixels of the display panel is matched with a brightness value of a light source to be irradiated to each of the pixels in order to maintain brightness of the display panel consistently according to a position of each of the pixels of the display panel.
- the brightness of the backlight may be increased linearly.
- deterioration of the brightness uniformity due to a signal delay at a gate line may be improved by reducing a difference in a charging voltage amount of a left-side pixel and a right-side pixel of a display panel.
- the method for controlling a display apparatus may be realized as a program and stored in diverse type of recording mediums. That is, a computer program which is processed by a various processors and executes the above-described methods may be stored in a recoding medium and executed.
- a non-transitory computer-readable medium including a program for executing operations of receiving feedback on a gate driving voltage applied to at least one pixel among a plurality of pixels arranged at an intersection of data lines to which a data voltage is applied by a source driver IC and gate lines to which a gate driving voltage is applied by a gate driver IC, detecting distortion of the gate driving voltage applied to at least one pixel based on the feedback, adjusting a level of the gate driving voltage applied to the gate lines to compensate for the distortion of the gate driving voltage, and applying the adjusted gate driving voltage to the gate lines, may be provided.
- the non-transitory computer-readable recording medium refers to a medium which may store data permanently or semi-permanently rather than storing data for a short time, such as, register, cache, memory, and the like, and may be readable by an apparatus.
- the above-described various applications and programs may be stored in and provided through the non-transitory computer-readable recording medium, such as, compact disc (CD), digital versatile disk (DVD), hard disk, Blu-ray disk, universal serial bus (USB), memory card, Read-Only Memory (ROM), and the like.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Claims (7)
- Appareil d'affichage (100) comprenant :un panneau d'affichage (110) conçu pour inclure une pluralité de pixels agencés aux intersections de lignes de données et de lignes de grille ;un circuit intégré, CI, de commande de source (120) conçu pour être disposé sur une surface latérale du panneau d'affichage afin d'appliquer une tension de données aux lignes de données ;un CI de commande de grille (130) conçu pour être disposé sur l'une des deux surfaces latérales du panneau d'affichage qui sont adjacentes à la surface latérale du panneau d'affichage, afin d'appliquer des impulsions de tension de commande de grille aux lignes de grille ;un dispositif de commande (140) conçu pour recevoir un signal de rétroaction comprenant des informations sur la tension de commande de grille appliquée à un pixel parmi la pluralité de pixels, pour détecter une distorsion de la tension de commande de grille appliquée audit pixel sur la base du signal de rétroaction, pour régler un niveau des impulsions de tension de commande de grille appliquées aux lignes de grille conformément à une quantité de la distorsion détectée de la tension de commande de grille pour compenser la distorsion de la tension de commande de grille, et pour appliquer les impulsions de tension de commande de grille réglées aux lignes de grille par l'intermédiaire du CI de commande de grille (130) ;une unité de rétroéclairage (160) conçue pour fournir un rétroéclairage au panneau d'affichage ; etun pilote de rétroéclairage (170) conçu pour piloter l'unité de rétroéclairage,dans lequel ledit pixel est situé à une position la plus éloignée du CI de commande de grille sur la ligne de grille à laquelle le pixel est connecté, et dans lequel chacune desdites impulsions de tension de commande de grille est constituée d'une première section, d'une section intermédiaire après la première section et d'une dernière section après la section intermédiaire, etle dispositif de commande (140) est conçu pour régler les impulsions de tension de commande de grille en augmentant le niveau de la tension uniquement dans la première section et dans la dernière section desdites impulsions, conformément à la quantité de la distorsion détectée.
- Appareil selon la revendication 1,
dans lequel le pilote de rétroéclairage est conçu pour piloter l'unité de rétroéclairage de sorte qu'une luminosité du rétroéclairage fourni à partir de l'unité de rétroéclairage augmente dans une direction opposée au CI de commande de grille. - Appareil selon la revendication 1, dans lequel le dispositif de commande est conçu pour générer un signal de synchronisation chaque fois que la tension de commande de grille est appliquée aux lignes de grille et pour transmettre le signal de synchronisation généré au pilote de rétroéclairage,
dans lequel le pilote de rétroéclairage est conçu pour piloter l'unité de rétroéclairage afin de fournir le rétroéclairage lorsque la tension de commande de grille est appliquée sur la base du signal de synchronisation reçu. - Appareil selon la revendication 3, comprenant en outre :un dispositif de stockage conçu pour stocker à l'avance une table de consultation où chacun de la pluralité de pixels du panneau d'affichage est mis en correspondance avec des valeurs de luminosité de sources lumineuses de l'unité de rétroéclairage devant être irradiées en direction des pixels afin de maintenir la luminosité du panneau d'affichage à un certain niveau constant en fonction d'une position de chacun des pixels du panneau d'affichage,dans lequel le pilote de rétroéclairage est conçu pour piloter l'unité de rétroéclairage à l'aide de la table de consultation stockée à l'avance.
- Appareil selon la revendication 2, dans lequel le pilote de rétroéclairage est conçu pour augmenter progressivement la luminosité du rétroéclairage dans la direction opposée au CI de commande de grille.
- Procédé de commande de l'appareil d'affichage selon la revendication 1, le procédé comprenant :la réception, en tant que signal de rétroaction, d'informations sur la tension de commande de grille, qui a été appliquée audit pixel situé à une position la plus éloignée du CI de commande de grille (S710) ;la détection d'une distorsion de la tension de commande de grille appliquée au pixel sur la base du signal de rétroaction (S720) ;le réglage d'un niveau des impulsions de tension de commande de grille appliquées aux lignes de grille conformément à la quantité de la distorsion détectée de la tension de commande de grille pour compenser la distorsion de la tension de commande de grille (S730) ;l'application des impulsions de tension de commande de grille réglées aux lignes de grille (S740) ; etl'application d'un niveau de tension de commande à l'unité de rétroéclairage,dans lequel chacune desdites impulsions de tension de commande de grille est constituée d'une première section, d'une section intermédiaire après la première section et d'une dernière section après la section intermédiaire, et le procédé comprend le réglage des impulsions de tension de commande de grille en augmentant le niveau de la tension uniquement dans la première section et dans la dernière section desdites impulsions, conformément à la quantité de la distorsion détectée.
- Procédé selon la revendication 6, comprenant en outre :
l'augmentation d'une luminosité d'un rétroéclairage fourni par l'unité de rétroéclairage dans une direction opposée au CI de commande de grille.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562173582P | 2015-06-10 | 2015-06-10 | |
KR1020150173468A KR102185696B1 (ko) | 2015-06-10 | 2015-12-07 | 디스플레이 장치 및 그 제어 방법 |
PCT/KR2016/006152 WO2016200191A1 (fr) | 2015-06-10 | 2016-06-10 | Appareil d'affichage et son procédé de commande |
Publications (3)
Publication Number | Publication Date |
---|---|
EP3259751A1 EP3259751A1 (fr) | 2017-12-27 |
EP3259751A4 EP3259751A4 (fr) | 2018-03-07 |
EP3259751B1 true EP3259751B1 (fr) | 2021-05-19 |
Family
ID=57734419
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP16807831.9A Active EP3259751B1 (fr) | 2015-06-10 | 2016-06-10 | Appareil d'affichage et son procédé de commande |
Country Status (2)
Country | Link |
---|---|
EP (1) | EP3259751B1 (fr) |
KR (1) | KR102185696B1 (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102417204B1 (ko) * | 2017-10-11 | 2022-07-06 | 삼성디스플레이 주식회사 | 표시장치 및 이의 구동 방법 |
KR102472083B1 (ko) * | 2018-03-14 | 2022-11-30 | 삼성디스플레이 주식회사 | 표시 장치 |
TWI767654B (zh) * | 2021-04-16 | 2022-06-11 | 友達光電股份有限公司 | 顯示裝置及其驅動方法 |
KR102584486B1 (ko) * | 2021-10-29 | 2023-10-04 | 한양대학교 산학협력단 | 디스플레이 장치 및 디스플레이 장치의 제어 방법 |
CN114637148B (zh) * | 2022-05-10 | 2022-10-11 | 惠科股份有限公司 | 阵列基板、液晶显示面板以及控制方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140327708A1 (en) * | 2011-11-15 | 2014-11-06 | Sharp Kabushiki Kaisha | Display device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009230108A (ja) * | 2008-02-29 | 2009-10-08 | Canon Inc | 表示パネルの駆動回路および表示装置 |
TWI406246B (zh) * | 2009-03-26 | 2013-08-21 | Chunghwa Picture Tubes Ltd | 輸出致能訊號的調整裝置及其方法 |
TWI455092B (zh) * | 2011-12-09 | 2014-10-01 | Innolux Corp | 顯示器驅動方法、驅動模組及顯示裝置 |
US20130235011A1 (en) * | 2012-03-06 | 2013-09-12 | Poshen Lin | LCD Panel Driving Method, Display Drive Circuit, and LCD Device |
-
2015
- 2015-12-07 KR KR1020150173468A patent/KR102185696B1/ko active IP Right Grant
-
2016
- 2016-06-10 EP EP16807831.9A patent/EP3259751B1/fr active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140327708A1 (en) * | 2011-11-15 | 2014-11-06 | Sharp Kabushiki Kaisha | Display device |
Also Published As
Publication number | Publication date |
---|---|
EP3259751A4 (fr) | 2018-03-07 |
EP3259751A1 (fr) | 2017-12-27 |
KR102185696B1 (ko) | 2020-12-02 |
KR20160145471A (ko) | 2016-12-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10366666B2 (en) | Display apparatus and method for controlling the same | |
EP3259751B1 (fr) | Appareil d'affichage et son procédé de commande | |
CN107111981B (zh) | 具有板内栅极电路的柔性显示装置 | |
EP2993663B1 (fr) | Dispositif d'affichage à cristaux liquides | |
EP3038096B1 (fr) | Écran a cristaux liquides et procédé de commande correspondant | |
US10276085B2 (en) | Pixel signal compensation for a display panel | |
US20150015564A1 (en) | Display device | |
KR101818247B1 (ko) | 액정표시장치 및 그 구동방법 | |
US9135890B2 (en) | Display device and driving method thereof | |
KR20160037010A (ko) | 디스플레이 구동 회로 및 디스플레이 구동 방법 | |
US8004487B2 (en) | Display device | |
US20110234561A1 (en) | Display controller and method for driving liquid crystal display panel | |
US9007359B2 (en) | Display device having increased aperture ratio | |
US8072445B2 (en) | Driving device and display apparatus having the same | |
KR102525544B1 (ko) | 표시 장치 및 이의 구동 방법 | |
US20140118321A1 (en) | Display device | |
KR20170028000A (ko) | 표시장치 및 이의 구동방법 | |
JP5705401B2 (ja) | 表示装置を含む電子装置 | |
KR101677761B1 (ko) | 액정표시장치 | |
KR20110072116A (ko) | 액정 표시장치 및 그의 구동방법 | |
US9947284B2 (en) | Display apparatus selecting and applying external voltage and method of driving the same | |
US20170004787A1 (en) | Display apparatus and method of operating the same | |
KR102037695B1 (ko) | 액정표시장치 및 그 제어방법 | |
KR102679882B1 (ko) | 표시장치 및 표시장치의 구동 방법 | |
CN106875903B (zh) | 显示装置及其驱动方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20170919 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
AX | Request for extension of the european patent |
Extension state: BA ME |
|
A4 | Supplementary search report drawn up and despatched |
Effective date: 20180202 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: G09G 3/34 20060101ALI20180129BHEP Ipc: G09G 3/36 20060101AFI20180129BHEP |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) | ||
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: EXAMINATION IS IN PROGRESS |
|
17Q | First examination report despatched |
Effective date: 20190531 |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
INTG | Intention to grant announced |
Effective date: 20201209 |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: PARK, YOUNG-MOOK Inventor name: KIM, DAE-SIK Inventor name: JUNG, JONG-HOON |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE PATENT HAS BEEN GRANTED |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 602016058147 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: REF Ref document number: 1394746 Country of ref document: AT Kind code of ref document: T Effective date: 20210615 |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D |
|
REG | Reference to a national code |
Ref country code: LT Ref legal event code: MG9D |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: MK05 Ref document number: 1394746 Country of ref document: AT Kind code of ref document: T Effective date: 20210519 |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: MP Effective date: 20210519 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: LT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: HR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: BG Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210819 Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LV Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210820 Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210919 Ref country code: NO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210819 Ref country code: PL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210920 Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: RS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SM Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: RO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 602016058147 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: BE Ref legal event code: MM Effective date: 20210630 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210610 |
|
26N | No opposition filed |
Effective date: 20220222 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210630 Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210610 Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210630 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210919 Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210719 Ref country code: AL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210630 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: HU Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO Effective date: 20160610 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210519 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20240520 Year of fee payment: 9 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20240520 Year of fee payment: 9 |