EP3213409B1 - Mélangeur déphaseur - Google Patents

Mélangeur déphaseur Download PDF

Info

Publication number
EP3213409B1
EP3213409B1 EP15778516.3A EP15778516A EP3213409B1 EP 3213409 B1 EP3213409 B1 EP 3213409B1 EP 15778516 A EP15778516 A EP 15778516A EP 3213409 B1 EP3213409 B1 EP 3213409B1
Authority
EP
European Patent Office
Prior art keywords
signal
differential
mixer
circuit
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP15778516.3A
Other languages
German (de)
English (en)
Other versions
EP3213409A1 (fr
Inventor
Hasnain Mohammedi Lakdawala
Bin Fan
Ojas Mahendra Choksi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of EP3213409A1 publication Critical patent/EP3213409A1/fr
Application granted granted Critical
Publication of EP3213409B1 publication Critical patent/EP3213409B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
    • H03D3/009—Compensating quadrature phase or amplitude imbalances
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1441—Balanced arrangements with transistors using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1466—Passive mixer arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
    • H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
    • H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers
    • H04L27/2067—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers with more than two phase states
    • H04L27/2089—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers with more than two phase states with unbalanced quadrature channels

Definitions

  • This invention relates generally to mixers, and more specifically, to phase adjusting circuits in the mixers.
  • Wireless communication networks are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcasts, and so on.
  • Such networks which are usually multiple access networks, support communications for multiple users by sharing the available network resources.
  • one network may be a 3G (the third generation of mobile phone standards and technology) system, which may provide network service via any one of various 3G radio access technologies (RATs) including EVDO (Evolution-Data Optimized), 1xRTT (1 times Radio Transmission Technology, or simply 1x), W-CDMA (Wideband Code Division Multiple Access), UMTS-TDD (Universal Mobile Telecommunications System - Time Division Duplexing), HSPA (High Speed Packet Access), GPRS (General Packet Radio Service), or EDGE (Enhanced Data rates for Global Evolution).
  • RATs 3G radio access technologies
  • the 3G network is a wide area cellular telephone network that evolved to incorporate high-speed internet access and video telephony, in addition to voice calls. Furthermore, a 3G network may be more established and provide larger coverage areas than other network systems.
  • Such multiple access networks may also include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single-carrier FDMA (SC-FDMA) networks, 3 rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) networks, and Long Term Evolution Advanced (LTE-A) networks.
  • CDMA code division multiple access
  • TDMA time division multiple access
  • FDMA frequency division multiple access
  • OFDMA orthogonal frequency division multiple access
  • SC-FDMA single-carrier FDMA
  • 3GPP 3 rd Generation Partnership Project
  • LTE Long Term Evolution
  • LTE-A Long Term Evolution Advanced
  • a wireless communication network may include a number of base stations that can support communication for a number of mobile stations.
  • a mobile station may communicate with a base station (BS) via a downlink and an uplink.
  • the downlink (or forward link) refers to the communication link from the base station to the mobile station
  • the uplink (or reverse link) refers to the communication link from the mobile station to the base station.
  • a base station may transmit data and control information on the downlink to a mobile station and/or may receive data and control information on the uplink from the mobile station.
  • the dual inductor circuit comprises an inductor-within-inductor design in which a small inductor is disposed within a large inductor.
  • the two inductors may share a ground terminal, but are otherwise physically separated and independent from one another.
  • an apparatus includes first through sixth transistors.
  • the first transistor receives an input signal and provides an amplified signal.
  • the second transistor receives the amplified signal and provides signal drive for an output signal.
  • the third transistor receives the input signal and provides an intermediate signal.
  • the fourth transistor provides bias for the third transistor in a high linearity mode.
  • the fifth transistor receives the intermediate signal and provides signal drive for the output signal in a low linearity mode.
  • the third and fourth transistors form a deboost path that is enabled in the high linearity mode to improve linearity.
  • the third and fifth transistors form a cascode path that is enabled in the low linearity mode to improve gain and noise performance.
  • the sixth transistor generates distortion component used to cancel distortion component from the first transistor
  • Certain embodiments of the present disclosure generally relate to quadrature combining and adjusting in radio frequency (RF) circuits including phase shifting mixers.
  • the present disclosure provides for adjusting phase imbalance at the baseband (BB) I and Q components in auxiliary mixer devices.
  • each auxiliary mixer device is configured as a combination of devices having a plurality of paths of multiple linearity modes.
  • exemplary is used herein to mean “serving as an example, instance, or illustration.” Any design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other designs.
  • the detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary designs of the present disclosure. It will be apparent to those skilled in the art that the exemplary designs described herein may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary designs presented herein.
  • CDMA Code Division Multiple Access
  • OFDM Orthogonal Frequency Division Multiplexing
  • TDMA Time Division Multiple Access
  • SDMA Spatial Division Multiple Access
  • SC-FDMA Single Carrier Frequency Division Multiple Access
  • TD-SCDMA Time Division Synchronous Code Division Multiple Access
  • Multiple user terminals can concurrently transmit/receive data via different (1) orthogonal code channels for CDMA, (2) time slots for TDMA, or (3) sub-bands for OFDM.
  • a CDMA system may implement IS-2000, IS-95, IS-856, Wideband-CDMA (W-CDMA), or some other standards.
  • An OFDM system may implement Institute of Electrical and Electronics Engineers (IEEE) 802.11 (Wireless Local Area Network (WLAN)), IEEE 802.16 (Worldwide Interoperability for Microwave Access (WiMAX)), Long Term Evolution (LTE) (e.g., in TDD and/or FDD modes), or some other standards.
  • IEEE Institute of Electrical and Electronics Engineers
  • WiMAX Worldwide Interoperability for Microwave Access
  • LTE Long Term Evolution
  • a TDMA system may implement Global System for Mobile Communications (GSM) or some other standards.
  • GSM Global System for Mobile Communications
  • the techniques described herein may also be implemented in any of various other suitable wireless systems using radio frequency (RF) technology, including Global Navigation Satellite System (GNSS), Bluetooth, IEEE 802.15 (Wireless Personal Area Network (WPAN)), Near Field Communication (NFC), Small Cell, Frequency Modulation (FM), and the like.
  • GNSS Global Navigation Satellite System
  • WLAN Global Navigation Satellite System
  • WiMAX Worldwide Interoperability for Micro
  • FIG. 1 illustrates a wireless communications system 100 with access points and user terminals.
  • An access point is generally a fixed station that communicates with the user terminals and may also be referred to as a base station (BS), an evolved Node B (eNB), or some other terminology.
  • a user terminal may be fixed or mobile and may also be referred to as a mobile station (MS), an access terminal, user equipment (UE), a station (STA), a client, a wireless device, or some other terminology.
  • a user terminal may be a wireless device, such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless modem, a laptop computer, a tablet, a personal computer, etc.
  • PDA personal digital assistant
  • Access point 110 may communicate with one or more user terminals 120 at any given moment on the downlink and uplink.
  • the downlink i.e., forward link
  • the uplink i.e., reverse link
  • a user terminal may also communicate peer-to-peer with another user terminal.
  • a system controller 130 couples to and provides coordination and control for the access points.
  • System 100 employs multiple transmit and multiple receive antennas for data transmission on the downlink and uplink.
  • Access point 110 may be equipped with a number N ap of antennas to achieve transmit diversity for downlink transmissions and/or receive diversity for uplink transmissions.
  • a set N u of selected user terminals 120 may receive downlink transmissions and transmit uplink transmissions.
  • Each selected user terminal transmits user-specific data to and/or receives user-specific data from the access point.
  • each selected user terminal may be equipped with one or multiple antennas (i.e., N ut ⁇ 1).
  • the N u selected user terminals can have the same or different number of antennas.
  • Wireless system 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system.
  • TDD time division duplex
  • FDD frequency division duplex
  • the downlink and uplink may share the same frequency band.
  • the downlink and uplink use different frequency bands.
  • System 100 may also utilize a single carrier or multiple carriers for transmission.
  • Each user terminal may be equipped with a single antenna (e.g., in order to keep costs down) or multiple antennas (e.g., where the additional cost can be supported).
  • FIG. 2 shows a block diagram of access point 110 and two user terminals 120m and 120x in wireless system 100.
  • Access point 110 is equipped with N ap antennas 224a through 224ap.
  • User terminal 120m is equipped with N ut,m antennas 252ma through 252mu
  • user terminal 120x is equipped with N ut,x antennas 252xa through 252xu.
  • Access point 110 is a transmitting entity for the downlink and a receiving entity for the uplink.
  • Each user terminal 120 is a transmitting entity for the uplink and a receiving entity for the downlink.
  • a “transmitting entity” is an independently operated apparatus or device capable of transmitting data via a frequency channel
  • a “receiving entity” is an independently operated apparatus or device capable of receiving data via a frequency channel.
  • the subscript "dn” denotes the downlink
  • the subscript "up” denotes the uplink
  • N up user terminals are selected for simultaneous transmission on the uplink
  • N dn user terminals are selected for simultaneous transmission on the downlink
  • N up may or may not be equal to N dn
  • N up and N dn may be static values or can change for each scheduling interval. Beam-steering or some other spatial processing technique may be used at the access point and user terminal.
  • a TX data processor 288 receives traffic data from a data source 286 and control data from a controller 280.
  • TX data processor 288 processes (e.g., encodes, interleaves, and modulates) the traffic data ⁇ d up ⁇ for the user terminal based on the coding and modulation schemes associated with the rate selected for the user terminal and provides a data symbol stream ⁇ s up ⁇ for one of the N ut,m antennas.
  • a transceiver front end (TX/RX) 254 receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) a respective symbol stream to generate an uplink signal.
  • the transceiver front end 254 may also route the uplink signal to one of the N ut,m antennas for transmit diversity via an RF switch, for example.
  • the controller 280 may control the routing within the transceiver front end 254.
  • a number N up of user terminals may be scheduled for simultaneous transmission on the uplink.
  • Each of these user terminals transmits its set of processed symbol streams on the uplink to the access point.
  • N ap antennas 224a through 224ap receive the uplink signals from all N up user terminals transmitting on the uplink.
  • a transceiver front end 222 may select signals received from one of the antennas 224 for processing.
  • a combination of the signals received from multiple antennas 224 may be combined for enhanced receive diversity.
  • the access point's transceiver front end 222 also performs processing complementary to that performed by the user terminal's transceiver front end 254 and provides a recovered uplink data symbol stream.
  • the recovered uplink data symbol stream is an estimate of a data symbol stream ⁇ s up ⁇ transmitted by a user terminal.
  • An RX data processor 242 processes (e.g., demodulates, deinterleaves, and decodes) the recovered uplink data symbol stream in accordance with the rate used for that stream to obtain decoded data.
  • the decoded data for each user terminal may be provided to a data sink 244 for storage and/or a controller 230 for further processing.
  • a TX data processor 210 receives traffic data from a data source 208 for N dn user terminals scheduled for downlink transmission, control data from a controller 230 and possibly other data from a scheduler 234. The various types of data may be sent on different transport channels. TX data processor 210 processes (e.g., encodes, interleaves, and modulates) the traffic data for each user terminal based on the rate selected for that user terminal. TX data processor 210 may provide a downlink data symbol streams for one of more of the N dn user terminals to be transmitted from one of the N ap antennas.
  • the transceiver front end 222 receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) the symbol stream to generate a downlink signal.
  • the transceiver front end 222 may also route the downlink signal to one or more of the N ap antennas 224 for transmit diversity via an RF switch, for example.
  • the controller 230 may control the routing within the transceiver front end 222.
  • N ut,m antennas 252 receive the downlink signals from access point 110.
  • the transceiver front end 254 may select signals received from one of the antennas 252 for processing.
  • a combination of the signals received from multiple antennas 252 may be combined for enhanced receive diversity.
  • the user terminal's transceiver front end 254 also performs processing complementary to that performed by the access point's transceiver front end 222 and provides a recovered downlink data symbol stream.
  • An RX data processor 270 processes (e.g., demodulates, deinterleaves, and decodes) the recovered downlink data symbol stream to obtain decoded data for the user terminal.
  • FIG. 3 is a block diagram of an exemplary transceiver front end 300, such as transceiver front ends 222, 254 in FIG. 2 , in accordance with certain embodiments of the present disclosure.
  • the transceiver front end 300 includes a transmit (TX) path 302 (also known as a transmit chain) for transmitting signals via one or more antennas and a receive (RX) path 304 (also known as a receive chain) for receiving signals via the antennas.
  • TX transmit
  • RX receive
  • the paths may be connected with the antenna via an interface 306, which may include any of various suitable RF devices, such as a duplexer, a switch, a diplexer, surface acoustic wave (SAW) filters, and the like.
  • RF devices such as a duplexer, a switch, a diplexer, surface acoustic wave (SAW) filters, and the like.
  • SAW surface acoustic wave
  • Exemplary transceiver front ends may be found in U.S. Patent Application No. 14/465,442, filed August 21, 2014 and entitled “Quadrature Combining and Adjusting”.
  • SAW-less receiver SAW filter
  • the removal of the input SAW filter causes jammers with high input levels to be present at the low noise amplifier (LNA) input.
  • LNA low noise amplifier
  • the removal of the input SAW filter increases the dynamic range requirement up to 110 dB.
  • the TX path 302 may include a baseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, and a power amplifier 316.
  • the BBF 310, the mixer 312, and the DA 314 may be included in a radio frequency integrated circuit (RFIC), while the PA 316 is often external to the RFIC.
  • the BBF 310 filters the baseband signals received from the DAC 308, and the mixer 312 mixes the filtered baseband signals with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to RF).
  • LO transmit local oscillator
  • This frequency conversion process produces the sum and difference frequencies of the LO frequency and the frequency of the signal of interest.
  • the sum and difference frequencies are referred to as the beat frequencies.
  • the beat frequencies are typically in the RF range, such that the signals output by the mixer 312 are typically RF signals, which are amplified by the DA 314 and by the PA 316 before transmission by the antenna 303.
  • the RX path 304 includes a low noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326.
  • the LNA 322, the mixer 324, and the BBF 326 may be included in a radio frequency integrated circuit (RFIC), which may or may not be the same RFIC that includes the TX path components.
  • RFIC radio frequency integrated circuit
  • RF signals received via the antenna 303 may be amplified by the LNA 322, and the mixer 324 mixes the amplified RF signals with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (i.e., downconvert).
  • the baseband signals output by the mixer 324 may be filtered by the BBF 326 before being converted by an analog-to-digital converter (ADC) 328 to digital I or Q signals for digital signal processing.
  • ADC analog-to-digital converter
  • the transmit LO is typically produced by a TX frequency synthesizer 318, which may be buffered or amplified by amplifier 320 before being mixed with the baseband signals in the mixer 312.
  • the receive LO is typically produced by an RX frequency synthesizer 330, which may be buffered or amplified by amplifier 332 before being mixed with the RF signals in the mixer 324.
  • the transmit LO (and/or the receive LO) may be generated, for example, by frequency dividing the VCO signal by an integer value or by using an LO generating circuit which translates the VCO frequency to the LO frequency.
  • Exemplary LO generating circuits may be found in U.S. Patent No. 6,960,962 to Peterzell et al., filed December 10, 2001 and entitled "Local Oscillator Leakage Control in Direct Conversion Precesses".
  • the transmit LO (or receive LO) frequency dividing or generating circuit occurs inside the TX frequency synthesizer 318 (or RX frequency synthesizer 330).
  • Wireless communication systems transmitting radio frequency (RF) signals typically utilize in-phase (I) and quadrature (Q) components, where the Q component is approximately 90° out of phase with the I component.
  • I in-phase
  • Q quadrature
  • This ideal situation is illustrated in the vector diagram 400 of FIG. 4A , where "P" and "M” represent the positive and negative differential signals.
  • vector QP represents the gain and phase of the +Q signal of a differential Q signal
  • vector QM represents the gain and phase of the -Q signal.
  • vector IP represents the gain and phase of the +1 signal of a differential I signal
  • IM represents the gain and phase of the -I signal.
  • phase imbalance there is some phase imbalance (more or less than the ideal 90°) between the I and Q components as illustrated in the vector diagram 410 of FIG. 4B , such that there is increased residual sideband (RSB) (i.e., the image rejection suffers).
  • RSB residual sideband
  • phase imbalance is very common in real-world RF circuits and occurs when the circuit components (e.g., transistors, resistors, and capacitors) are not perfectly matched between I and Q paths.
  • either the I or Q local oscillator (LO) and/or baseband (BB) may be phase shifted (e.g., by introducing an intentional delay into the I or Q baseband signal generated by the mixers) in a simplex phase imbalance correction, as illustrated in the vector diagram 420 of FIG. 4C where the IP/IM signals, for example, are adjusted from the solid line 422 to the dotted line 424.
  • this simplex correction may introduce an amplitude error, as illustrated by the dotted line 424, where the adjusted IP/IM signals have a smaller amplitude than the QP/QM signals.
  • Certain embodiments of the present disclosure perform phase imbalance adjustment at outputs of the I and Q mixers in the RFFE of a wireless communication device in an effort to correct the phase imbalance at the baseband (BB) I and Q components.
  • this adjustment may be performed using auxiliary mixers in conjunction with the conventional I and Q mixers.
  • FIG. 5 is a block diagram of an exemplary phase imbalance adjusting circuit 500 using auxiliary mixers 502, 504, according to an embodiment of the present disclosure. From top to bottom, FIG. 5 illustrates an I auxiliary mixer 502, an I mixer 506, a Q mixer 508, and a Q auxiliary mixer 504. The two auxiliary mixers 502, 504 are used to combine (e.g., current combine) a partial Q output (e.g., a fraction of the gain of the signal output by the Q auxiliary mixer) with the I output and combine a partial I output with the Q output.
  • a partial Q output e.g., a fraction of the gain of the signal output by the Q auxiliary mixer
  • 1/16 the output of the I auxiliary mixer 502 is combined (e.g., via current summing) with the output of the Q mixer 508, and 1/16 the output of the Q auxiliary mixer 504 is combined with the output of the I mixer 506.
  • Certain embodiments of the present disclosure may use any suitable portion of the outputs of the auxiliary mixers 502, 504 and are not limited to a fraction of 1/16.
  • FIG. 6A is a schematic diagram of an exemplary implementation of the phase imbalance adjusting circuit 500 of FIG. 5 using differential signals, according to an embodiment of the present disclosure.
  • the normal I and Q mixers 606, 608 are illustrated by the bolded mixing stages, while the auxiliary I and Q mixers 602, 604 are represented by the thin, stacked mixing stages.
  • the normal I and Q mixers 606, 608 and the auxiliary I and Q mixers 602, 604 may be single-balanced or double-balanced mixers.
  • the normal I and Q mixers 606, 608 and the auxiliary I and Q mixers 602, 604 may be implemented with any mixer structure that allows for scaling the mixer output signals, such as the mixers described herein and the mixers described in U.S. Patent No.
  • the normal I and Q mixers 606, 608 and the auxiliary I and Q mixers 602, 604 may receive LO signals with any suitable duty cycle, such as a duty cycle that provides acceptable noise and conversion gain.
  • the mixers may be implemented with nominally 25%, nominally slightly larger than 25%, or nominally 50% duty cycle I and Q LO signals.
  • the "X" boxes represent polarity and/or gain control circuits 610, such that the differential outputs of the auxiliary I and Q mixers 602, 604 may be amplitude adjusted and/or phase inverted (by effectively swapping the two differential signal lines).
  • the exploded view of the polarity and/or gain control circuits 610 illustrates exemplary devices (e.g., switches, which may be combined with variable resistances or which may be combined or implemented with transistors 612 operated in the triode region) and connections for implementing the polarity and/or gain control. More detailed examples of the polarity and/or gain control circuits 610 are described below.
  • An input RF signal may be amplified, buffered, or attenuated by a low noise amplifier (LNA) 622.
  • the LNA 622 may be a transconductance amplifier configured to receive an input voltage and generate an output current.
  • the LNA 622 may output a single-ended signal or differential signals. If the output of the LNA 622 is a differential signal as depicted in FIG. 6A , the normal I and Q mixers 606, 608 and the auxiliary I and Q mixers 602, 604 may most likely be double-balanced mixers. If the output of the LNA 622 is a single-ended signal, however, the normal and auxiliary I and Q mixers may most likely be single-balanced mixers.
  • the output signal from the LNA 622 may be mixed by the normal I mixer 606 with an in-phase LO (LO_I) to produce an output in-phase signal (I_out) having frequency components at the sum and difference of the two signals input to the normal I mixer 606.
  • the output signal from the LNA 622 may also be mixed by the normal Q mixer 608 with a quadrature LO (LO_Q, which is 90° out of phase with LO_I) to produce an output quadrature signal (Q_out) having frequency components at the sum and difference of the two signals input to the normal Q mixer 608.
  • LO_Q quadrature LO
  • the auxiliary I mixer 602 may mix the output signal from the LNA 622 with the LO_I, and the output mixed signal is combined with the output of the normal Q mixer 608 to form Q_out.
  • a polarity and/or gain control circuit 610 may be used to invert and/or attenuate the output signal from the auxiliary I mixer 602 before combining with the output of the normal Q mixer 608.
  • the auxiliary Q mixer 604 may mix the output signal from the LNA 622 with the LO_Q, and this output mixed signal is combined with the output of the normal I mixer 606 to form I_out.
  • a polarity and/or gain control circuit 610 may be used to invert and/or attenuate the output signal from the auxiliary Q mixer 604 before combining with the output of the normal I mixer 606.
  • the auxiliary mixers 602, 604 may be used to accomplish duplex phase imbalance adjustment as illustrated in FIG. 4D .
  • the combining of signals from the normal and auxiliary mixers may occur at summing nodes 614 for current summing the respective signals.
  • the auxiliary mixers 602, 604 shown in FIG. 6A may comprise fixed and variable auxiliary mixers, as illustrated in FIG. 6B .
  • the fixed auxiliary I and Q mixers 602a, 604a may add a constant phase shift to the Q and I baseband signals (e.g., Q_out and I_out), respectively, generated by the normal Q and I mixers 608, 606.
  • the variable auxiliary I and Q mixers 602b, 604b are adjustable, such that the RSB may be corrected (or at least reduced) by varying the gate voltages of transistors in the variable mixers.
  • the fixed auxiliary mixers 602a, 604a have the effect of rotating the phase of the entire I_main and Q_main axis by the same amount.
  • phase shift of IB_fix_aux is equal to the shift of Q_fix_aux and rotates the entire constellation (here, the Q_main vector and the I_main vector) counterclockwise. It should be understood that the magnitude and angular direction of the phase shift of IB_fix_aux and Q_fix_aux are not limited by FIG. 6B .
  • the variable components IB_var_aux and Q_var_aux may be independently controlled and may rotate the I_main and Q_main vectors different amounts to correct (or at least reduce) phase imbalances.
  • FIG. 6B depicts IB_var_aux and Q_var_aux adding to IB_fix_aux and Q_fix_aux, consistent with the mixer output connections in the corresponding circuit of FIG. 6B .
  • IB_var_aux and Q_var_aux may be adjusted in either angular direction with the addition of polarity controls to the variable auxiliary I and Q mixers 602b, 604b.
  • the magnitude of adjustment from IB_var_aux and Q_var_aux is not limited by FIG. 6B and may be set to correct the offsets in the I_main and Q_main signal paths absent the adjustment circuits.
  • FIG. 4D is a more complete example vector representation of the correction possible with the circuit of FIG. 6B .
  • FIG. 7 is a block diagram conceptually illustrating the phase imbalance adjusting using auxiliary mixers and presenting associated signal equations, according to an embodiment of the present disclosure.
  • An RF signal 702 may be provided as input to an I mixer 606 and to a Q mixer 608.
  • the amplitude ( ⁇ /2) of the signal may be a fraction that of the normal mixers' outputs.
  • the auxiliary mixers 602, 604 (or more specifically, the gain control circuits 704, 706 implemented in or connected with the auxiliary mixers) may output a partial signal to combine with the output from another mixer.
  • an output 708 from the Q mixer 608 may be combined (e.g., summed) with the partial output 710 from the auxiliary I mixer 602, and an output 712 from the I mixer 606 may be combined with the partial output 714 from the auxiliary Q mixer 604.
  • These signal combinations 716, 718 may be processed in the Q and I baseband (BB) circuits 720, 722 (e.g., BB filters), respectively, thereby leading to the phase-corrected in-phase output (PCIO) and phase-corrected quadrature output (PCQO) signals with associated equations as shown in FIG. 7 .
  • FIG. 8 illustrates an example of duplex I/Q phase imbalance adjustment corresponding to the implementation in FIG. 6A , according to an embodiment of the present disclosure.
  • PCIO represents a phase-corrected I output
  • PCQO represents a phase-corrected Q output, according to the equations shown in FIG. 8 .
  • FIG. 9 is a schematic diagram of an exemplary RF front end (RFFE) 900 with a phase imbalance adjusting circuit using auxiliary mixers 602, 604, according to an embodiment of the present disclosure.
  • a low noise transconductance amplifier 622 may precede the main and auxiliary mixers and may be used to amplify an RF input.
  • the main and auxiliary mixers may be single balanced mixers or double balanced mixers.
  • the mixer output may be provided to an I-Q combining circuit 902, where the X boxes represent polarity and/or gain control circuits 610 as described above.
  • One or more control lines 903 may be connected with the polarity and/or gain control circuits 610 to control the components therein (e.g., adjust the on-resistance of a transistor 612, modify the resistance of a variable resistor (e.g., a rheostat), or control operation of a switch).
  • current mode filters 904, 906 e.g., baseband filters
  • the current mode filters 904, 906 may be implemented with any suitable combination of resistors, capacitors, and inductors for baseband (low-pass) filtering.
  • the mixed (and optionally filtered) signals may be provided to transimpedance amplifiers 908, 910 to convert the current-mode baseband signals to voltage-mode baseband I and Q signals for additional baseband processing.
  • FIG. 10 is a schematic diagram of an exemplary RFFE 1000 with a phase imbalance adjusting circuit using partial combining of quadrature mixer output signals (e.g., without the auxiliary mixers 602, 604 described above), according to an embodiment of the present disclosure.
  • the functions of the main and auxiliary mixers may be effectively combined in FIG. 10 , such that the normal I and Q mixers 606, 608 receive an RF input, which may be amplified by an optional low noise transconductance amplifier 622.
  • an optional low noise transconductance amplifier 622 may be a single-ended output signal from the amplifier 622 , the output of the amplifier 622 may be a differential signal instead, in which case double-balanced mixers may be used.
  • the mixer outputs may be provided to an I-Q combining circuit 1002 connected as shown, where the X boxes represent polarity and/or gain control circuits 610 as described above. For certain embodiments, one or the other of the polarity and/or gain control circuits 610 may be included (i.e., one of the X boxes is optional).
  • the combined baseband outputs which may be filtered using optional current mode filters 904, 906, may be provided to trans-impedance amplifiers 908, 910 to convert the current-mode signals to voltage-mode signals (e.g., baseband I and Q signals) for additional processing.
  • a polarity and/or gain control circuit 610 may be implemented with four transistors, each drain and source of the transistors connected between a different one of the four combinations of LOIP, LOIM, LOQP, and LOQM. There may be a resistor between each mixer signal line and the drain or source of the transistor, for a total of eight series resistors.
  • FIG. 11 is a block diagram conceptually illustrating the phase imbalance adjusting without using auxiliary mixers and presenting associated signal equations, according to an embodiment of the present disclosure.
  • An RF signal may be provided as input to an I mixer 606 and to a Q mixer 608.
  • a fraction of the amplitude ( ⁇ /2) of one mixer's output signal may be combined with the output signal from another mixer.
  • an output 1102 from the Q mixer 608 may be combined (e.g., summed) with the partial output 1104 from the I mixer 606, and an output 1106 from the I mixer 606 may be combined with the partial output 1108 from the Q mixer 608.
  • FIGs. 12A and 12B are schematic diagrams of exemplary implementations of a phase imbalance adjusting circuit using partial combining of quadrature mixer output signals, according to embodiments of the present disclosure.
  • double-balanced mixers are shown, and the local oscillator signals LO_I and LO_Q are connected with gates of the transistors 1202 in the polarity and/or gain control circuits 610, such that the timing of the partial combining is synchronized.
  • LO_I+ and LO_I- may be interchanged in the polarity and/or gain control circuit 610 from what is shown in FIG. 12A .
  • LO_Q+ and LO_Q- may also be interchanged in the other polarity and/or gain control circuit 610.
  • interchanging the LO_I+ and LO_I- may be accomplished by placing multiplexers (i.e., muxes) between the gates of the transistors 1202 and the various differential quadrature LO signals.
  • muxes By employing muxes, the +/- LO connections may be swapped.
  • the amount of the coupling (i.e., the partial combining) is controlled by activating more or less transistors 1202. If the number of the activated transistors 1202 is greater, the amount of the coupling increases, and vice versa.
  • the activation of each transistor 1202 may be achieved by turning on or off the buffers in the LO driving path. If the buffers are on, the transistors 1202 may be activated, whereas if the buffers are off, the transistors may be deactivated.
  • the circuit in FIG. 12A also includes current buffer biquads (CBBQs) 1204, which may be baseband filters that have low impedance inputs and provide a 2 nd -order baseband transfer function.
  • CBBQs current buffer biquads
  • the CBBQs 1204 may be preceded by optional current mode filtering or may be replaced with transimpedance amplifiers with optional current mode filtering, as illustrated in FIGs. 9 and 10 .
  • FIG. 12B is a schematic diagram of an exemplary implementation with single-balanced mixers.
  • the output of the LNA 622 may be single-ended, and AC coupling capacitors 1206 are used to couple the single-ended output of the LNA 622 to the normal I and Q mixers 606, 608.
  • a single common capacitor may be used instead, since LNA_I+ and LNA_Q+ signals have the same amplitude and phase.
  • I may be coupled to Q (and IB may be coupled to QB) through the combining paths controlled by the ItoQ/IBtoQB control signal.
  • I may be coupled to QB (and IB may be coupled to Q) through the combining paths controlled by the ItoQB/IbtoQ control signal.
  • the coupling paths are implemented as multiple sets of resistors and transistors in parallel, the strength of the coupling may be modified by controlling the number of transistors which are enabled by the control signals.
  • gain control on the I and Q mixer outputs may be provided by the ItoIB coupling path (which is controlled by the ItoIB control signal) and by the QtoQB coupling path (which is controlled by the QtoQB control signal).
  • the CBBQs 1204 may be optionally preceded by optional current mode filtering or may be replaced by any combination of current mode filtering and transimpedance amplifiers (TIA), as illustrated in FIGs. 9 and 10 .
  • FIG. 13 illustrates an example of possible I-Q corrections that may be performed by a phase imbalance adjusting circuit using partial combining of quadrature mixer output signals, such as in the RFFE 1000 in FIG. 10 or implementations thereof.
  • the angle 1302 between IP/IM and QP/QM may be increased or decreased, where I and Q are adjusted together.
  • I and Q may not be independently controlled in this implementation, in contrast with phase imbalance adjusting circuits using auxiliary mixers, such as the RFFE 900 in FIG. 9 or implementations thereof.
  • FIG. 14 illustrates an exemplary double balanced mixer 1400 that may be used as a mixer in a phase imbalance adjusting circuit, as main or auxiliary mixers, according to embodiments of the present disclosure.
  • the transistors 1402 of the mixer 1400 may mix a differential RF signal (RF InP and RF InM) with a differential LO signal (such as a differential I LO signal composed of LOIP and LOIM).
  • the mixing produces a differential (baseband) output signal (BBIP and BBIM) having frequency components at the sum and difference frequencies of the differential RF and LO signals.
  • the channel width-to-length ratio (W/L) of an auxiliary mixer transistor may be smaller than the W/L of a main mixer transistor.
  • the W/L of an auxiliary mixer transistor can be between 10 and 100 times smaller than that of a main mixer transistor (e.g., W/L of 0.3 to 3 for an auxiliary mixer transistor versus 30 for a main mixer transistor).
  • the auxiliary mixer may be designed to any suitable size (i.e., channel width-to-length ratio (W/L)) to provide a desired phase imbalance correction and is not limited to the previous example.
  • FIGS. 15A-15F illustrate an exemplary mixer implementation with various example polarity and/or gain control circuits 610, according to embodiments of the present disclosure.
  • an auxiliary mixer 1502 provides input to a polarity control circuit 1504 (composed of four transistors 1505) and a digital gain control circuit 1506.
  • the effective auxiliary mixer gain i.e., the overall gain through the auxiliary mixer and the polarity and/or gain control circuit
  • the order of the polarity and gain control circuits 1504, 1506 is interchangeable.
  • FIG. 15B illustrates an auxiliary mixer 1502 providing input to a polarity control circuit 1504 and an analog gain control circuit 1510, in contrast with the digital gain control circuit 1506 of FIG. 15A .
  • the effective auxiliary mixer gain may be controlled, for example, by controlling the gate bias on gain control transistors 1511, which may control the R ds(on) of the gain control transistors.
  • the order of the polarity and gain control circuits 1504, 1510 is interchangeable.
  • the digital gain control circuit 1506 may be cascaded with the analog gain control circuit 1510, in either order.
  • FIG. 15C illustrates an exemplary circuit similar to FIG. 15B , with variable resistors 1521 used in place of the gain control transistors 1511 in the gain control circuit 1520.
  • the variable resistance may be analog or digitally controlled via a control line Vcntrl_res, for example.
  • FIG. 15D illustrates an exemplary circuit 1530 similar to FIG. 15A , with polarity and gain control merged into four groups of selectively enabled parallel transistors 1531 connected with the auxiliary mixer 1502.
  • Digital control lines may be used to select various combinations of the N transistors in each group.
  • Digital logic e.g., logic gates 1535
  • FIG. 15E illustrates an exemplary circuit 1540 similar to that shown in FIG. 15B , but with polarity and gain control merged into four transistors 1541.
  • transmission gates 1545 e.g., an inverter and an analog demultiplexer
  • FIG. 15F illustrates an exemplary circuit 1550 that may be used to implement the variable auxiliary mixers 602b, 604b of FIG. 6B .
  • the polarity here is controlled by selectively swapping the LO signal polarity (using switches or transistors 1552 controlled by the PLUS and MINUS signals), and the gain is controlled by controlling the DC bias 1554 on the gates of the auxiliary mixer transistors 1402 using the control line Vbias_gain.
  • FIG. 16 illustrates an exemplary double balanced mixer 1600 (similar to the mixer 1400 shown in FIG. 14 ) that may be used as an auxiliary mixer in a phase imbalance adjusting circuit according to another embodiment of the present disclosure.
  • the mixer 1600 of FIG. 16 includes a plurality of mixing circuits 1610 and a plurality of combining circuits 1620.
  • the plurality of mixing circuits 1610 includes four mixing circuits 1612, 1614, 1616, 1618, each of which may be configured as an auxiliary mixing circuit 1700 shown in FIG. 17A or as a mixing circuit 1402 shown in FIG. 14 .
  • at least one of the plurality of mixing circuits 1610 will be configured as an auxiliary mixing circuit 1700 shown in FIG. 17A .
  • a combining circuit 1622 or 1624 includes a summing circuit which adds or subtracts two input signals to produce an output signal.
  • the auxiliary mixer 1600 receives a differential LO signal and a differential RF input signal.
  • the differential LO signal comprises a positive in-phase LO signal (LOIP) 1650 and a negative in-phase LO signal (LOIM) 1654.
  • the differential RF input signal comprises a positive RF input signal (RF InP) 1652 and a negative RF input signal (RF InM) 1656.
  • the differential LO signal comprises a positive quadrature LO signal (LOQP) and a negative quadrature LO signal (LOQM).
  • the auxiliary mixer 1600 also receives a plurality of linearity mode control signals including a low linearity mode (LL mode) control signal 1660 and mid-linearity mode (ML mode) control signal 1662.
  • LL mode low linearity mode
  • ML mode mid-linearity mode
  • the auxiliary mixing circuit 1600 generates a differential (baseband) output signal comprising a positive baseband output signal (BBIP) 1630 and a negative baseband output signal (BBIM) 1632.
  • the positive baseband output signal (BBIP) 1630 has its frequency component at the sum frequency of the differential RF and LO signals, while the negative baseband output signal (BBIM) 1632 has its frequency component at the difference frequency of the differential RF and LO signals.
  • the mixing circuit 1612 receives a positive in-phase LO signal (LOIP) 1650 and a positive RF input signal (RF InP) 1652, along with linearity mode control signals 1660, 1662.
  • the mixing circuit 1612 mixes the two input signals 1650, 1652 to generate a first frequency converted signal 1672, which is output to the combining circuit 1622.
  • the mixing circuit 1614 receives a negative in-phase LO signal (LOIM) 1654 and a positive RF input signal (RF InP) 1652, along with linearity mode control signals 1660, 1662.
  • the mixing circuit 1614 mixes the two input signals 1652, 1654 to generate a second frequency converted signal 1674, which is output to the combining circuit 1624.
  • the mixing circuit 1616 receives a negative in-phase LO signal (LOIM) 1654 and a negative RF input signal (RF InM) 1656, along with linearity mode control signals 1660, 1662.
  • the mixing circuit 1616 mixes the two input signals 1654, 1656 to generate a third frequency converted signal 1676, which is output to the combining circuit 1622.
  • the mixing circuit 1618 receives a positive in-phase LO signal (LOIP) 1650 and a negative RF input signal (RF InM) 1656, along with linearity mode control signals 1660, 1662.
  • the mixing circuit 1618 mixes the two input signals 1650, 1656 to generate a fourth frequency converted signal 1678, which is output to the combining circuit 1624.
  • the combining circuit 1622 receives first and third frequency converted signals 1672, 1676 of the mixing circuits 1612, 1616, respectively, and combines the signals 1672, 1676 to generate the positive baseband output signal (BBIP) 1630.
  • the combining circuit 1624 receives second and fourth frequency converted signals 1674, 1678 of the mixing circuits 1614, 1618, respectively, and combines the signals 1674, 1678 to generate the negative baseband output signal (BBIM) 1632.
  • Two output signals 1630, 1632 of the combining circuits 1622, 1624 form the differential baseband output signal which is sent to the baseband filter 1640.
  • FIG. 17A is a schematic diagram of an exemplary implementation of an auxiliary mixing circuit 1700 according to one embodiment of the present disclosure.
  • the auxiliary mixing circuit 1700 shown in FIG. 17A is one embodiment of at least one of the mixing circuits 1612, 1614, 1616, 1618.
  • any one of the mixing circuits 1612, 1614, 1616, 1618 can be configured as a mixing circuit 1402 shown in FIG. 14 , instead of the auxiliary mixing circuit 1700.
  • the auxiliary mixing circuit 1700 comprises a combination of devices such that the size of the auxiliary mixing circuit 1700 is adjustable as a function of the impedance of the baseband filter.
  • the reason for configuring the size of the auxiliary mixing circuit 1700 to be adjustable as a function of the impedance of the baseband filter is that I and Q coupling currents change when the impedance of the baseband filter is changed (e.g., in the presence of jammers).
  • I and Q coupling currents change when the impedance of the baseband filter is changed (e.g., in the presence of jammers).
  • SAW receiver surface acoustic wave
  • the removal of the input SAW filter causes jammers with high input levels to be present at the low noise amplifier (LNA) input. Further, the removal of the input SAW filter increases the dynamic range requirement up to 110 dB.
  • the size of the auxiliary mixing circuit 1700 needs to be adjustable as a function of the impedance of the baseband filter. Since I and Q coupling currents are appropriately mixed in the mixer (as described above in detail) to adjust the phase imbalance, any disturbances of the ratio of the I and Q coupling currents cause increase in the noise figure.
  • the auxiliary mixing circuit 1700 is configured with a plurality of paths 1710, 1720, 1730, wherein each path represents one linearity mode.
  • the disturbances are countered by adjusting the resistance for the path of each linearity mode as a function of the impedance of the baseband filter.
  • MOSFET metal oxide semiconductor field effect transistor
  • MOS resistor metal oxide semiconductor field effect transistor
  • the value of the MOSFET resistor is adjusted by adjusting the current flowing through the MOSFET.
  • the value of MOS resistor 1722 is adjusted as a function of the baseband filter impedance, while MOSFET switch 1724 is turned on and MOSFET switch 1714 is turned off.
  • the value of MOS resistor 1732 is adjusted as a function of the baseband filter impedance. It should be noted that although only three paths are shown in FIG. 17A , any number of linearity mode paths can be configured as a function of the baseband filter impedance. Further, it should also be noted that the linearity mode paths can be combined to provide different resistances for different baseband filter impedances. In FIG. 17A , LO-controlled MOS resistors 1712, 1722, 1732 are grouped and labeled as 1740, while linearity mode switches 1714, 1724 are grouped and labeled as 1742.
  • the size of the auxiliary mixing circuit 1700 is adjusted by placing additional switched series resistors. In yet another embodiment, the size of the auxiliary mixing circuit 1700 is adjusted using a MOS-based programmable resistor.
  • FIG. 17B is a schematic diagram of an exemplary implementation of an auxiliary mixing circuit 1750 according to another embodiment of the present disclosure.
  • the auxiliary mixing circuit 1750 includes a single path such that the LO-controlled MOS resistors 1740 in FIG. 17A are replaced with a single LO-controlled MOS resistor 1760, while the linearity mode switches 1742 in FIG. 17A are replaced with at least one variable resistor 1762, which adjusts the current for a desired linearity mode.
  • the MOS resistor 1760 is driven by a local oscillator and acts as a switching device.
  • the at least one variable resistor 1762 controls the current.
  • the variable resistor 1762 is implemented as a voltage-controlled variable resistor.
  • the variable resistor 1762 is implemented as a bank of switchable resistors.
  • Transceiver chips, LNAs, and mixers described herein may be implemented on an IC, an analog IC, an RFIC, a mixed-signal IC, an ASIC, a printed circuit board (PCB), an electronic device, etc.
  • the receiver chips and LNAs may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.
  • CMOS complementary metal oxide semiconductor
  • NMOS N-channel MOS
  • PMOS P-channel MOS
  • BJT bipolar junction transistor
  • BiCMOS bipolar-CMOS
  • SiGe silicon germanium
  • GaAs gallium arsenide
  • An apparatus implementing the transceiver chips, LNAs, and mixers described herein may be a stand-alone device or may be part of a larger device.
  • a device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.
  • RFR RF receiver
  • RTR RF transmitter/receiver
  • MSM mobile station modem
  • processors such as a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine.
  • a processor can also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Further, circuits implementing the embodiments and functional blocks and modules described herein can be realized using various transistor types, logic families, and design methodologies.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Transceivers (AREA)
  • Transmitters (AREA)
  • Superheterodyne Receivers (AREA)

Claims (15)

  1. Appareil (1600) comprenant :
    une pluralité de circuits mélangeurs (1610, 1710) configurés pour générer une pluralité de signaux convertis en fréquence ;
    au moins un circuit mélangeur (1700) de la pluralité de circuits mélangeurs configuré avec une pluralité de chemins (1710, 1720, 1730), chaque chemin représentant un mode de linéarité,
    la pluralité de chemins comprenant :
    un premier chemin d'un mode de haute linéarité (1730) configuré avec une première résistance semiconductrice à oxyde métallique (1732) ; et
    un deuxième chemin d'un mode à faible linéarité (1710) configuré avec une deuxième résistance semiconductrice à oxyde métallique (1712) et un premier commutateur de mode (1714),
    les première et deuxième résistances semiconductrice à oxyde métallique étant commandées par un signal oscillant local ; et
    une pluralité de circuits de combinaison (1620) configurés pour combiner la pluralité de signaux convertis en fréquence afin de générer un signal de sortie différentiel en bande de base (1630, 1632).
  2. Appareil (1600) selon la revendication 1, dans lequel ledit au moins un circuit mélangeur (1610, 1700) est un mélangeur auxiliaire (1700) d'un émetteur-récepteur SAW-less d'un système global de communications mobiles, GSM.
  3. Appareil (1600) selon la revendication 1, dans lequel le premier commutateur de mode (1714) est un commutateur semiconducteur à oxyde métallique commandé par un signal de mode à faible linéarité.
  4. Appareil (1600) selon la revendication 1, dans lequel la pluralité de chemins comprend en outre :
    un troisième chemin d'un mode de linéarité moyenne (1720) configuré avec une troisième résistance semiconductrice à oxyde métallique (1722) et un deuxième commutateur de mode (1724),
    la troisième résistance semiconductrice à oxyde métallique (1722) étant également commandée par le signal oscillant local.
  5. Appareil (1600) selon la revendication 4, dans lequel le deuxième commutateur de mode (1724) est un commutateur semiconducteur à oxyde métallique commandé par un signal de mode à linéarité moyenne.
  6. Appareil (1600) selon la revendication 1, dans lequel la pluralité de circuits mélangeurs (1610) est configurée pour recevoir un signal d'oscillateur local différentiel et un signal d'entrée RF différentiel,
    le signal d'oscillateur local différentiel comprenant un signal d'oscillateur local différentiel positif (1650) et un signal d'oscillateur local différentiel négatif (1654), et
    le signal d'entrée RF différentiel comprenant un signal d'entrée RF différentiel positif (1652) et un signal d'entrée RF différentiel négatif (1656).
  7. Appareil (1600) selon la revendication 6, dans lequel la pluralité de circuits mélangeurs comprend des premier, deuxième, troisième et quatrième circuits mélangeurs,
    la pluralité de circuits mélangeur étant configurés pour mélanger le signal d'oscillateur local différentiel et le signal d'entrée RF différentiel pour générer la pluralité de signaux convertis en fréquence comprenant des premier, deuxième, troisième et quatrième signaux convertis en fréquence.
  8. Appareil (1600) selon la revendication 7, dans lequel le premier circuit mélangeur (1612) est configuré pour mélanger le signal d'oscillateur local différentiel positif et un signal d'entrée RF différentiel positif pour générer le premier signal converti en fréquence.
  9. Appareil (1600) selon la revendication 7, dans lequel le deuxième circuit mélangeur (1614) est configuré pour mélanger le signal d'oscillateur local différentiel négatif et un signal d'entrée RF différentiel positif pour générer le deuxième signal converti en fréquence.
  10. Appareil (1600) selon la revendication 7, dans lequel le troisième circuit mélangeur (1616) est configuré pour mélanger le signal d'oscillateur local différentiel négatif et un signal d'entrée RF différentiel négatif pour générer le troisième signal converti en fréquence.
  11. Appareil (1600) selon la revendication 7, dans lequel le quatrième circuit mélangeur (1618) est configuré pour recevoir le signal d'oscillateur local différentiel positif et un signal d'entrée RF différentiel négatif pour générer le quatrième signal converti en fréquence.
  12. Appareil (1600) selon la revendication 7, dans lequel la pluralité de circuits de combinaison (1620) comprend des premier et deuxième circuits de combinaison, la pluralité de circuits de combinaison étant configurée pour générer des signaux de sortie en bande de base positif et négatif du signal de sortie différentiel en bande de base.
  13. Appareil (1600) selon la revendication 12, dans lequel le premier circuit de combinaison (1622) est configuré pour combiner le premier signal converti en fréquence et le troisième signal converti en fréquence afin de générer le signal de sortie en bande de base positif, et/ou
    le deuxième circuit de combinaison (1624) est configuré pour combiner le deuxième signal converti en fréquence et le quatrième signal converti en fréquence afin de générer un signal de sortie en bande de base négatif du signal de sortie en bande de base différentiel.
  14. Appareil (1600) selon la revendication 1, ledit au moins un circuit mélangeur (1610) comprend
    une résistance semiconductrice à oxyde métallique (1760) commandée par oscillateur local en série avec au moins une résistance variable commandée en tension (1762).
  15. Appareil (1600) selon la revendication 14, dans lequel chacune des résistances variables commandées en tension (1762) est configurée sous la forme d'un groupe de résistances commutables.
EP15778516.3A 2014-10-29 2015-09-28 Mélangeur déphaseur Active EP3213409B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201462072354P 2014-10-29 2014-10-29
US14/576,013 US9431961B2 (en) 2014-10-29 2014-12-18 Phase shifting mixer
PCT/US2015/052717 WO2016069165A1 (fr) 2014-10-29 2015-09-28 Mélangeur déphaseur

Publications (2)

Publication Number Publication Date
EP3213409A1 EP3213409A1 (fr) 2017-09-06
EP3213409B1 true EP3213409B1 (fr) 2019-01-02

Family

ID=55853780

Family Applications (1)

Application Number Title Priority Date Filing Date
EP15778516.3A Active EP3213409B1 (fr) 2014-10-29 2015-09-28 Mélangeur déphaseur

Country Status (5)

Country Link
US (1) US9431961B2 (fr)
EP (1) EP3213409B1 (fr)
JP (1) JP2017538326A (fr)
CN (1) CN107112951B (fr)
WO (1) WO2016069165A1 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10666305B2 (en) * 2015-12-16 2020-05-26 Kumu Networks, Inc. Systems and methods for linearized-mixer out-of-band interference mitigation
US11031665B2 (en) 2016-07-21 2021-06-08 The Trustees Of Columbia University In The City Of New York Magnetic-free non-reciprocal circuits based on sub-harmonic spatio-temporal conductance modulation
US10050664B1 (en) 2017-03-27 2018-08-14 Kumu Networks, Inc. Enhanced linearity mixer
CN109217977A (zh) 2017-06-30 2019-01-15 株式会社Ntt都科摩 数据发送方法、装置及存储介质
WO2019190500A1 (fr) * 2018-03-28 2019-10-03 Mohammed Alam Architecture de récepteur haute performance
CN109889458B (zh) * 2019-02-28 2021-12-28 深圳市信达珑丰科技有限公司 图书馆信息化管理系统
WO2020183619A1 (fr) * 2019-03-12 2020-09-17 三菱電機株式会社 Mélangeur
US10903867B1 (en) * 2019-08-30 2021-01-26 U-Blox Ag Discrete time superheterodyne mixer
KR20210044365A (ko) 2019-10-14 2021-04-23 삼성전자주식회사 위상 천이 기능을 갖는 믹서 및 이를 포함하는 통신 장치
CN110896340B (zh) * 2019-11-28 2024-05-14 天津七六四通信导航技术有限公司 一种基于dsp的车载全频段干扰仪
US11271597B1 (en) * 2020-09-15 2022-03-08 Swiftlink Technologies Co., Ltd. Wideband transmitter for millimeter-wave wireless communication
US20240106445A1 (en) * 2022-09-22 2024-03-28 Qualcomm Incorporated Symmetrical resistive harmonic rejection mixer (hrm)
CN117728768B (zh) * 2024-02-07 2024-05-03 深圳疆泰科技有限公司 正交有源双平衡混频器、芯片以及物联网设备

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2325102B (en) 1997-05-09 2001-10-10 Nokia Mobile Phones Ltd Down conversion mixer
JP2001274631A (ja) * 2000-03-27 2001-10-05 Mitsubishi Electric Corp 平衡型ｆｅｔミクサおよび通信装置
JP2002246939A (ja) * 2001-02-14 2002-08-30 Mitsubishi Electric Corp Ｄｓｒｃ用車載器
US6891423B2 (en) 2002-04-04 2005-05-10 Telefonaktiebolaget Lm Ericsson (Publ) Quadrature switching mixer with reduced leakage
KR100483848B1 (ko) * 2003-05-29 2005-04-15 삼성전자주식회사 평형 임피던스 소자의 편차 보상회로 및 이를 이용한주파수 혼합회로
EP2136468B1 (fr) 2004-03-12 2012-06-13 RF Magic, Inc. Mélangeur de suppression d'harmoniques et syntoniseur
US7545855B2 (en) 2005-09-08 2009-06-09 Broadcom Corporation Phase shifter and current mode mixer
US8219060B2 (en) 2006-07-28 2012-07-10 Qualcomm Incorporated Dual inductor circuit for multi-band wireless communication device
US7899426B2 (en) * 2007-10-30 2011-03-01 Qualcomm Incorporated Degenerated passive mixer in saw-less receiver
US8072255B2 (en) 2008-01-07 2011-12-06 Qualcomm Incorporated Quadrature radio frequency mixer with low noise and low conversion loss
US8229043B2 (en) * 2008-03-21 2012-07-24 Qualcomm Incorporated Stepped gain mixer
US8571510B2 (en) * 2008-08-18 2013-10-29 Qualcomm Incorporated High linearity low noise receiver with load switching
US8310312B2 (en) 2009-08-11 2012-11-13 Qualcomm, Incorporated Amplifiers with improved linearity and noise performance
US8583049B2 (en) 2009-09-08 2013-11-12 Bae Systems Information And Electronic Systems Integration Inc. Self-optimizing integrated RF converter
US8594603B2 (en) 2009-11-08 2013-11-26 The Trustees Of Columbia University In The City Of New York Systems and methods for cancelling interferers in a receiver
WO2011085027A1 (fr) * 2010-01-05 2011-07-14 Maxlinear, Inc. Architecture radio à gamme dynamique élevée avec suppression de la fréquence image améliorée
US9071243B2 (en) * 2011-06-30 2015-06-30 Silicon Image, Inc. Single ended configurable multi-mode driver
US9287912B2 (en) 2013-03-15 2016-03-15 Mstar Semiconductor, Inc. Multimode receiver with complex filter

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

Also Published As

Publication number Publication date
US9431961B2 (en) 2016-08-30
EP3213409A1 (fr) 2017-09-06
US20160126894A1 (en) 2016-05-05
JP2017538326A (ja) 2017-12-21
WO2016069165A1 (fr) 2016-05-06
CN107112951B (zh) 2021-08-10
CN107112951A (zh) 2017-08-29

Similar Documents

Publication Publication Date Title
EP3213409B1 (fr) Mélangeur déphaseur
US9088471B1 (en) Quadrature combining and adjusting
CN102315856B (zh) 无表面声波接收器
US10033338B2 (en) Switched inductor/transformer for dual-band low-noise amplifier (LNA)
US10033340B1 (en) Low-noise amplifier (LNA) with capacitive attenuator
US10581534B2 (en) Noise cancellation system
US20200106394A1 (en) Reconfigurable broadband and noise cancellation low noise amplifier (lna) with intra-carrier aggregation (ca) capability
US9520846B2 (en) Current-driven baseband filter with reduced adjacent channel leakage ratio (ACLR)
TW201933760A (zh) 用於高線性主動混頻器的大信號gm3消除技術
US9577576B1 (en) Biased passive mixer
WO2020096719A1 (fr) Tampon de signal à large bande
CN109314498A (zh) 具有轨到轨输出摆幅的源极退化的放大级
WO2021056001A2 (fr) Système et procédé de suppression de la distorsion hybride
CN115769489A (zh) 使用rf插值的6相数字辅助谐波抑制收发器
US20240204753A1 (en) Wideband current-mode low-pass filter circuits
US11742839B2 (en) Local oscillator divider with reduced applied current variation
US11296678B1 (en) Complementary current-mode biquad with high linearity
US20240283473A1 (en) Wireless transmitter with bias control
WO2024177742A1 (fr) Émetteur sans fil à commande de polarisation
CN116325491A (zh) 分布式有源功率组合放大器

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20170313

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

INTG Intention to grant announced

Effective date: 20180719

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

Ref country code: AT

Ref legal event code: REF

Ref document number: 1085699

Country of ref document: AT

Kind code of ref document: T

Effective date: 20190115

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602015022865

Country of ref document: DE

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20190102

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1085699

Country of ref document: AT

Kind code of ref document: T

Effective date: 20190102

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190502

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190402

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190402

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190502

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190403

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602015022865

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

26N No opposition filed

Effective date: 20191003

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190930

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190930

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190928

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190928

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20190930

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190930

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20150928

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190102

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20230810

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20230807

Year of fee payment: 9

Ref country code: DE

Payment date: 20230808

Year of fee payment: 9