EP3197095B1 - Dispositif informatique et son procédé de gestion de configuration - Google Patents

Dispositif informatique et son procédé de gestion de configuration Download PDF

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Publication number
EP3197095B1
EP3197095B1 EP15874958.0A EP15874958A EP3197095B1 EP 3197095 B1 EP3197095 B1 EP 3197095B1 EP 15874958 A EP15874958 A EP 15874958A EP 3197095 B1 EP3197095 B1 EP 3197095B1
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EP
European Patent Office
Prior art keywords
pcie
smm
switch
port
cpu
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Active
Application number
EP15874958.0A
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German (de)
English (en)
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EP3197095A1 (fr
EP3197095A4 (fr
Inventor
Dexian Su
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication of EP3197095A4 publication Critical patent/EP3197095A4/fr
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/02—Standardisation; Integration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/34—Signalling channels for network management communication
    • H04L41/344—Out-of-band transfers

Definitions

  • the present invention relates to the field of information technologies, and in particular, to a computer device and a configuration and management method of a computer device.
  • a converged network interface card or a next-generation multi-function network interface card there is more configuration and management communication between the management software or a user and a network interface card (firmware upgrading, physical function configuration, reliability configuration, virtual machine Qos configuration, VLAN configuration, and the like). Configurability and manageability of the network interface card become an important function of a new-generation server.
  • PCIE Peripheral Component Interconnect Express
  • PCIE Peripheral Component Interconnect Express
  • a network interface card such as a network interface card, a converged network adapter (CNA, Converged Network Adaptor), a redundant array of independent disks (RAID, Redundant Arrays of Independent Disks) card, a solid state disk (SSD, Solid-state Drive) card, and a graphics processing unit (GPU, Graphic Processing Unit) card
  • CNA converged network adapter
  • RAID Redundant Arrays of Independent Disks
  • SSD Solid-state Drive
  • GPU Graphic Processing Unit
  • the SMM is connected to a server device over a network, and configures and manages a device such as the CNA/RAID/SSD in two manners.
  • a configuration proxy module is installed on a server system, and the SMM communicates with the configuration proxy module to implement configuration for the device such as the CNA/RAID/SSD.
  • the server needs to configure the peripheral device such as the CNA/RAID/SSD, the server loads a simple operating system from the SMM module, starts it, and then starts a service system locally from the server after the configuration is complete.
  • a configuration proxy tool is installed on an OS of the computer device depends on a type and a version of the OS that are selected by a customer.
  • deployment of an upgrade tool is inconvenient and uncontrollable, a firmware version cannot be checked, and a development workload is heavy as a firmware upgrade tool is strongly associated with the type of the OS system.
  • the simple operating system increases a system startup time.
  • the SMM needs to connect to a server host system by using a network, which increases hardware costs. Management and service are coupled by using a service channel, which is unfavorable for maintenance and isolation.
  • WO 2010/114910 relates a virtualization system that couples host computers and multiple IO devices to provide IO virtualization.
  • a management CPU (MCPU) in an IOV system couples or connects directly to the transport fabric 120 using a fabric-native interface, and the MCPU is used to perform some functions, such as initiating or discovering.
  • US 2010/0281518 relates to method for separating control of a network interface device. Particularly, it discloses that a network interface device includes a management channel for receiving communications from a user through a first port and from a service providers through a second port.
  • the network interface device includes management logic in communication with the management channel.
  • the management logic includes a service provider controller utilized to control operation of the network interface device and a user controller operable to control operation of a partition of the network interface device.
  • Embodiments of the present invention provide a computer device and a configuration and management method of a computer device, so as to resolve a prior-art problem that flexibility is poor and system configuration is complex because the computer device needs to rely on an operating system of the computer device to configure and manage a PCIE device.
  • an embodiment of the present invention provides a computer device, including a Peripheral Component Interconnect Express PCIE Switch, a system management module SMM, a central processing unit CPU, and at least one PCIE device, where
  • the SMM when the SMM configures and manages the at least one PCIE device by using the PCIE link between the SMM and the PCIE Switch, the SMM configures the PCIE port between the PCIE Switch and the SMM as the uplink port by using the management channel.
  • the SMM configures the PCIE port between the PCIE Switch and the CPU as the uplink port by using the management channel.
  • the SMM includes a management central processing unit MCPU, and the MCPU is connected to the PCIE Switch by using the PCIE link and configures and manages the at least one PCIE device.
  • the PCIE Switch is independent of the CPU or the PCIE Switch is located in the CPU.
  • that the MCPU configures and manages the at least one PCIE device includes at least one of the following: upgrading fireware, configuring a parameter, or querying PCIE device information.
  • an embodiment of the present invention further provides a configuration and management method of a computer device, where the computer device includes a Peripheral Component Interconnect Express PCIE Switch, a system management module SMM, a central processing unit CPU, and at least one PCIE device, and the method includes: configuring, by the SMM, a PCIE port between the PCIE Switch and the SMM as an uplink port by using a management channel;
  • the PCIE Switch is independent of the CPU or the PCIE Switch is located in the CPU.
  • a fourth possible implementation manner of the second aspect that the MCPU configures and manages the at least one PCIE device includes at least one of the following: upgrading fireware, configuring a parameter, or querying PCIE device information.
  • an SMM and a CPU are controlled to be connected to a PCIE Switch at different stages of system startup, so that when the SMM is connected to the PCIE Switch, the PCIE Switch disconnects from the CPU, and management of a PCIE device does not rely on involvement of the CPU of the computer device.
  • the PCIE device can be configured and managed without involvement of an operating system of the computer device, and CPU resources are saved.
  • the SMM module implements out-of-band management of the PCIE device, thereby reducing coupling to the computer device, improving manageability of the computer device, and meeting a requirement of a large data center for simplifying computing device management.
  • the PCIE device is connected to the PCIE Switch by using a downlink port, with no need to configure a special interface to connect to the SMM, thereby simplifying system configuration.
  • FIG. 1 is a schematic diagram of a specific implementation structure of a computer device 100 according to an embodiment of the present invention.
  • the computer device includes a system management module 102 (SMM, System Management Module), a PCIE Switch 101, a central processing unit 103 (CPU, Centrol Processing Unit), and PCIE devices (a CAN, a RAID, and an SSD are used as examples for description).
  • the SMM 102 is configured to manage hardware of the computer device, including power-on and power-off control of the computer device, device ambient temperature, board voltage monitoring, configuration and management of the PCIE device such as the CNA/RAID/SSD, Firmware firmware upgrading, and the like.
  • the SMM 102 is connected to the PCIE Switch 101 of the computer device by using a PCIE port provided by a management central processing unit MCPU (Management Central Process Unit) 1021.
  • the PCIE Switch 101 includes two Up Ports, which are respectively connected to the CPU 103 of the computer device and the MCPU 1021 of the SMM 102.
  • the PCIE Switch 101 has multiple Down Ports, which are respectively connected to the PCIE devices such as the CNA/RAID/SSD.
  • the CPU 103 of the computer device accesses the peripheral devices such as the CNA/RAID/SSD by using the PCIE Switch.
  • a PCIE network is in a tree structure.
  • Each PCIE Switch can have only one Up Port and multiple Down Ports at a time. Therefore, for the two Up Ports respectively connected to the CPU 103 of the computer device and the MCPU 1021 of the SMM 102, only one Up Port can work at a time.
  • Different Up Ports are controlled to connect to the PCIE Switch 101 at different stages of system startup, so that the PCIE Switch 101 disconnects from the CPU 103 when the SMM 102 is connected to the PCIE Switch 101. Management of the PCIE devices does not rely on involvement of the CPU 103 of the computer device, thereby saving resources of the CPU 103.
  • Involvement of an operating system of the computer device is not required, thereby implementing effective management of the PCIE devices (such as the CNA/RAID/SSD) by the SMM 102.
  • the PCIE devices such as the CNA are connected to the PCIE Switch 101 by using a Down Port, with no need to configure a special interface to connect to the SMM 102, thereby simplifying system configuration.
  • the SMM 102 may configure and manage different devices by using different device drivers.
  • the SMM 102 may configure and manage different devices by using different device drivers, including but not limited to a PCIE driver, a device driver, and a device manager.
  • the PCIE driver completes basic device information configuration such as basic PCIE device discovery and address space allocation.
  • the device driver is a dedicated driver of various PCIE devices, and mainly completes peripheral device configuration and management for a device management module.
  • the device management completes parameter configuration of a PCIE device according to configuration template information provided by a user. It should be noted that the computer device needs to be restarted after the SMM 102 completes configuration and management, so as to implement configuration of the PCIE device.
  • a procedure of configuring and managing a PCIE device by the MCPU in the SMM module and a system startup procedure of normally using the PCIE device by the CPU include the following steps:
  • a depth-first search algorithm defined in a PCIE standard may be used to progressively discover all PCIE devices mounted to the PCIE Switch. After the PCIE devices are discovered, basic information such as IO space and memory space needs to be configured.
  • Step 205 The SMM configures and manages the PCIE devices connected to the PCIE Switch.
  • That the SMM configures and manages the PCIE devices connected to the PCIE Switch includes but is not limited to upgrading fireware, configuring a parameter (such as a quantity of physical functions, a type, bandwidth, and a RAID algorithm), querying PCIE device information, and so on.
  • a parameter such as a quantity of physical functions, a type, bandwidth, and a RAID algorithm
  • Step 206 Configure a PCIE port connected to a CPU as an uplink port of the PCIE Switch.
  • the uplink port may be changed, by using a management channel between the SMM module and the PCIE Switch, for example, an mChannel management channel, to the PCIE port for connecting to the CPU of the computer device.
  • the mChannel management channel in this embodiment of the present invention may be an Inter-Integrated Circuit (I2C, Inter-Integrated Circuit) channel.
  • I2C Inter-Integrated Circuit
  • Step 207 When the uplink port of the PCIE Switch is switched to the PCIE port between the PCIE Switch and the CPU, power on the CPU of the computer device.
  • Step 208 Start the computer device.
  • the startup of the computer device includes hardware initializing, operating system running, application program running, and the like.
  • FIG. 3 is a schematic diagram of another specific implementation structure of a computer device according to an embodiment of the present invention.
  • an MCPU 1021 of an SMM module 102 is connected to a PCIE Switch 201 in a CPU 203 of a computer device by using a PCIE link and a management channel mChannle, and PCIE devices (such as a CNA/RAID/SSD) are directly connected to the CPU 203 of the computer device by using PCIE links.
  • the PCIE Switch 201 is integrated in the CPU 203 of the computer device.
  • the PCIE Switch 201 may be implemented by using a chip capable of completing functions of the PCIE Switch.
  • the PCIE Switch 201 is further connected to an RC (Root Complex) 204 in the CPU 203.
  • the RC 204 is a root node of a PCIE network.
  • the RC 204 in the CPU 203 is connected to a port (which may be configured as an uplink port) of the PCIE Switch 201.
  • the SMM module 102 changes the uplink port of the PCIE Switch 201 by using the mChannle channel, so as to implement connection control over the PCIE Switch 201.
  • the SMM 102 establishes a connection between the MCPU 1021 and the PCIE Switch 201, and configures a PCIE port between the PCIE Switch and the SMM as the uplink port, or configures a PCIE port between the RC 204 and the PCIE Switch 201 as the uplink port.
  • the MCPU 1021 in the SMM 102 is further connected to the PCIE Switch 201 by using the PCIE link, so as to configure and manage the PCIE devices (such as the CNA/RAID/SSD) without relying on an operating system of the computer device or a specially configured channel provided by the PCIE devices.
  • FIG. 4 is a schematic structural diagram of a computer device 400 according to an embodiment of the present invention, including a Peripheral Component Interconnect Express PCIE Switch 401, a system management module SMM 402, a central processing unit CPU 403, and at least one PCIE device 404.
  • PCIE Switch 401 Peripheral Component Interconnect Express PCIE Switch 401
  • SMM 402 system management module
  • CPU 403 central processing unit
  • the SMM 402 and the CPU 403 are respectively connected to the PCIE Switch 401 by using PCIE ports.
  • the at least one PCIE device 404 is respectively connected to a downlink port of the PCIE Switch 401 by using a PCIE port.
  • the SMM 402 is connected to the PCIE Switch 401 by using a management channel, and controls the PCIE port connected to the SMM 402 or the PCIE port connected to the CPU 403 to be an uplink port of the PCIE Switch 401.
  • the SMM 402 is connected to the PCIE Switch 401 by using a PCIE link, and manages the at least one PCIE device 404 by using the PCIE Switch 401.
  • the PCIE Switch 401 disconnects from the CPU 403 when the SMM 402 is connected to the PCIE Switch 401, so that management of a PCIE device does not rely on involvement of the CPU of the computer device.
  • the PCIE device can be configured and managed without involvement of an operating system of the computer device, and CPU resources are saved.
  • the SMM module implements out-of-band management of the PCIE device, thereby reducing coupling to the computer device, improving manageability of the computer device, and meeting a requirement of a large data center for simplifying computing device management.
  • the PCIE device is connected to the PCIE Switch by using a downlink port, with no need to configure a special interface to connect to the SMM, thereby simplifying system configuration.
  • the SMM 402 when the SMM 402 configures and manages the at least one PCIE device 404 by using the PCIE link between the SMM 402 and the PCIE Switch 401, the SMM 402 configures the PCIE port between the PCIE Switch 401 and the SMM 402 as the uplink port by using the management channel.
  • the SMM 402 configures and manages the at least one PCIE device 404
  • the SMM 402 configures the PCIE port between the PCIE Switch 401 and the CPU 403 as the uplink port by using the management channel.
  • the SMM 402 may further include a management central processing unit MCPU, and the MCPU is connected to the PCIE Switch 401 by using the PCIE link and configures and manages the at least one PCIE device 403.
  • MCPU management central processing unit
  • the PCIE Switch 401 may be located in the PCIE Switch is located in the CPU, and is used as a module or a unit of the CPU 403, as shown in FIG. 3 .
  • that the SMM 402 or the MCPU configures and manages the at least one PCIE device 404 includes at least one of the following: upgrading fireware, configuring a parameter, or querying PCIE device information.
  • FIG. 5 is a schematic flowchart of a configuration and management method of a computer device according to an embodiment of the present invention.
  • the computer device includes a Peripheral Component Interconnect Express PCIE Switch, a system management module SMM, a central processing unit CPU, and at least one PCIE device.
  • the method includes the following steps:
  • a connection between an SMM and a PCIE Switch and a connection between a CPU and the PCIE Switch are controlled at different stages of system startup, so that when the SMM is connected to the PCIE Switch, the PCIE Switch disconnects from the CPU, and management of a PCIE device does not rely on involvement of the CPU of a computer device,
  • the PCIE device can be configured and managed without involvement of an operating system of the computer device, and CPU resources are saved.
  • the SMM module implements out-of-band management of the PCIE device, thereby reducing coupling to the computer device, improving manageability of the computer device, and meeting a requirement of a large data center for simplifying computing device management.
  • the PCIE device is connected to the PCIE Switch by using a downlink port, with no need to configure a special interface to connect to the SMM, thereby simplifying system configuration.
  • the SMM may include a management central processing unit MCPU, and the MCPU is connected to the PCIE Switch by using the PCIE link and configures and manages the at least one PCIE device. That the MCPU configures and manages the at least one PCIE device includes at least one of the following: upgrading fireware, configuring a parameter, or querying PCIE device information.
  • the SMM and the CPU are respectively connected to the PCIE Switch by using the PCIE port, and the at least one PCIE device is respectively connected to a downlink port of the PCIE Switch by using a PCIE port.
  • the PCIE Switch may be independent of the CPU or the PCIE Switch is located in the CPU.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the described apparatus embodiment is merely an example.
  • the unit division is merely logical function division and may be other division in actual implementation.
  • a plurality of units or components may be combined or integrated into another system, or some features may be ignored or not performed.
  • the displayed or discussed mutual couplings or direct couplings or communication connections may be implemented through some interfaces.
  • the indirect couplings or communication connections between the apparatuses or units may be implemented in electronic, mechanical, or other forms.
  • the units described as separate parts may or may not be physically separate. Parts displayed as units may or may not be physical units, and may be located in one position or may be distributed on a plurality of network units. A part or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments of the present invention.
  • functional units in the embodiments of the present invention may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units are integrated into one unit.
  • the integrated unit may be implemented in a form of hardware, or may be implemented in a form of a software functional unit.
  • the integrated unit When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, the integrated unit may be stored in a computer-readable storage medium. Based on such an understanding, the technical solutions of the present invention essentially, or the part contributing to the prior art, or all or a part of the technical solutions may be implemented in the form of a software product.
  • the software product is stored in a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, a server, a network device, or the like) to perform all or some of the steps of the methods described in the embodiments of the present invention.
  • the foregoing storage medium includes: any medium that can store program code, such as a USB flash drive, a removable hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc.
  • program code such as a USB flash drive, a removable hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Stored Programmes (AREA)
  • Hardware Redundancy (AREA)
  • Information Transfer Systems (AREA)
  • Debugging And Monitoring (AREA)

Claims (11)

  1. Dispositif informatique (400), comprenant un commutateur à interconnexion de composants périphériques express (PCIE) (401), un module de gestion de système (SMM) (402), une unité centrale de traitement (CPU) (403) et au moins un dispositif PCIE (404),
    le SMM (402) et la CPU (403) étant respectivement connectés au commutateur PCIE (401) au moyen d'un port PCIE, et l'au moins un dispositif PCIE (404) étant respectivement connecté à un port de liaison descendante du commutateur PCIE (401) au moyen d'un port PCIE ;
    le SMM (402) étant connecté au commutateur PCIE (401) au moyen d'un canal de gestion, et contrôlant un port PCIE connecté au SMM (402) ou un port PCIE connecté à la CPU (403) pour être un port de liaison montante du commutateur PCIE (401) ; et
    le SMM (402) étant connecté au commutateur PCIE (401) au moyen d'une liaison PCIE, et gérant l'au moins un dispositif PCIE (404) au moyen du commutateur PCIE (401).
  2. Dispositif informatique selon la revendication 1, dans lequel :
    quand le SMM (402) configure et gère l'au moins un dispositif PCIE (404) au moyen de la liaison PCIE entre le SMM (402) et le commutateur PCIE (401), le SMM (402) configure le port PCIE entre le commutateur PCIE (401) et le SMM (402) en tant que port de liaison montante au moyen du canal de gestion.
  3. Dispositif informatique selon la revendication 1, dans lequel :
    après que le SMM (402) a configuré et géré l'au moins un dispositif PCIE (404), le SMM (402) configure le port PCIE entre le commutateur PCIE (401) et la CPU (403) en tant que port de liaison montante au moyen du canal de gestion.
  4. Dispositif informatique selon l'une quelconque des revendications 1 à 3, dans lequel :
    le SMM (402) comprend une unité centrale de traitement de gestion (MCPU), et la MCPU est connectée au commutateur PCIE (401) au moyen de la liaison PCIE et configure et gère l'au moins un dispositif PCIE (404).
  5. Dispositif informatique selon la revendication 4, dans lequel :
    le commutateur PCIE (401) est indépendant de la CPU (403) ou le commutateur PCIE (401) est situé dans la CPU (403).
  6. Dispositif informatique selon la revendication 5, dans lequel :
    le fait que la MCPU configure et gère l'au moins un dispositif PCIE (404) consiste à : mettre à niveau un microprogramme et/ou configurer un paramètre et/ou demander une information de dispositif PCIE.
  7. Procédé de configuration et de gestion d'un dispositif informatique, le dispositif informatique comprenant un commutateur à interconnexion de composants périphériques express (PCIE), un module de gestion de système (SMM), une unité centrale de traitement (CPU) et au moins un dispositif PCIE, consistant à :
    configurer (500), par le SMM, un port PCIE entre le commutateur PCIE et le SMM en tant que port de liaison montante au moyen d'un canal de gestion ;
    connecter (502), par le SMM, au commutateur PCIE au moyen d'une liaison PCIE, et configurer et gérer l'au moins un dispositif PCIE au moyen du commutateur PCIE ; et
    configurer (504), par le SMM, un port PCIE entre le commutateur PCIE et la CPU en tant que port de liaison montante au moyen du canal de gestion après que le SMM a terminé de configurer et de gérer l'au moins un dispositif PCIE.
  8. Procédé selon la revendication 7, dans lequel :
    le SMM comprend une unité centrale de traitement de gestion (MCPU), et la MCPU est connectée au commutateur PCIE au moyen de la liaison PCIE et configure et gère l'au moins un dispositif PCIE.
  9. Procédé selon la revendication 7 ou 8, dans lequel :
    le SMM et la CPU sont respectivement connectés au commutateur PCIE au moyen du port PCIE, et l'au moins un dispositif PCIE est respectivement connecté à un port de liaison descendante du commutateur PCIE au moyen d'un port PCIE.
  10. Procédé selon la revendication 7 ou 8, dans lequel :
    le commutateur PCIE est indépendant de la CPU ou le commutateur PCIE est situé dans la CPU.
  11. Procédé selon la revendication 7 ou 8, dans lequel :
    le fait que la MCPU configure et gère l'au moins un dispositif PCIE consiste à : mettre à niveau un microprogramme et/ou configurer un paramètre et/ou demander une information de dispositif PCIE.
EP15874958.0A 2014-12-30 2015-11-02 Dispositif informatique et son procédé de gestion de configuration Active EP3197095B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410853336.2A CN104579772B (zh) 2014-12-30 2014-12-30 计算机设备与计算机设备的配置管理方法
PCT/CN2015/093593 WO2016107273A1 (fr) 2014-12-30 2015-11-02 Dispositif informatique et son procédé de gestion de configuration

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EP3197095A1 EP3197095A1 (fr) 2017-07-26
EP3197095A4 EP3197095A4 (fr) 2017-09-06
EP3197095B1 true EP3197095B1 (fr) 2018-09-12

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US (1) US10318443B2 (fr)
EP (1) EP3197095B1 (fr)
CN (1) CN104579772B (fr)
ES (1) ES2700203T3 (fr)
WO (1) WO2016107273A1 (fr)

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US10318443B2 (en) 2019-06-11
WO2016107273A1 (fr) 2016-07-07
EP3197095A1 (fr) 2017-07-26
EP3197095A4 (fr) 2017-09-06
CN104579772B (zh) 2018-12-14
ES2700203T3 (es) 2019-02-14
US20170300431A1 (en) 2017-10-19

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