EP3159805B1 - Periphere steuereinheit - Google Patents

Periphere steuereinheit Download PDF

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Publication number
EP3159805B1
EP3159805B1 EP15190439.8A EP15190439A EP3159805B1 EP 3159805 B1 EP3159805 B1 EP 3159805B1 EP 15190439 A EP15190439 A EP 15190439A EP 3159805 B1 EP3159805 B1 EP 3159805B1
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Prior art keywords
peripheral
fifo
input
output
data
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English (en)
French (fr)
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EP3159805A1 (de
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Vinod NAHVAL
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NXP BV
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NXP BV
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Priority to US15/262,746 priority patent/US10366043B2/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/067—Bidirectional FIFO, i.e. system allowing data transfer in two directions

Definitions

  • the present specification relates to peripheral controllers and in particular peripheral controllers for half-duplex communication.
  • peripherals are various different types of devices that are auxiliary to a main or central data processing device or system. Peripherals often provide some kind of input and/or output function.
  • the data processing system may be a general purpose computer to which various peripheral devices may be attached to communicate and interact with the general purpose computer.
  • input peripherals may include keyboards, mice, graphics tablets, touch screens, pointer devices, microphones, cameras, controllers and similar.
  • Output peripherals may include displays, printers, plotters, storage devices, loud speakers and similar.
  • Some peripherals may provide input and output functions, such as touch screen devices.
  • data and/or control commands are passed between the system and the peripheral and some form of communications protocol is used to control the communication of data and/ control commands.
  • Various types of communications protocols may be used, but they may be generally classified as providing either full duplex communication or half duplex communication.
  • a full duplex communication protocol permits transmission and reception at the same time.
  • the telephone is a common example of a communications system permitting duplex communication.
  • a half-duplex communication system permits only one of transmission or reception at any time. Hence, data can either be transmitted or received, but not both at the same time.
  • a half-duplex communications protocol is the IIC or I 2 C protocol (the Inter-Integrated Circuit protocol) that provides a serial computer bus, and which may be used, amongst other things, for attaching the integrated circuits of peripherals to processors or microcontrollers of the data processing device.
  • IIC or I 2 C protocol the Inter-Integrated Circuit protocol
  • Other half duplex communications protocols that may be used to communicate between the processor or microcontroller of a data processing system and peripheral devices include UART (Universal asynchronous receiver/transmitter) and SPI (Serial Peripheral Interface) which have half-duplex versions.
  • a peripheral controller may be provided to provide buffering between a system bus, via which a central processing unit, main processor or microcontroller can communicate with other parts of the data processing device, and a peripheral bus to which one or more peripheral devices may be attached. Buffering may be used to accommodate the different rates at which data may be produced by, or consumed by, the system and the peripheral. For example a central processing unit or microcontroller may operate at a much greater speed than an integrated circuit of a peripheral device.
  • BiFIFO bidirectional FIFO
  • the BiFIFO includes a first bidirectional port for receiving or transmitting data and a second bidirectional port for receiving or transmitting data.
  • An input multiplexer can be controlled by control logic to select which of the first or second bidirectional ports will act as the input to the BiFIFO and receives data from the input port.
  • An output multiplexer can be controlled by the control logic to select which of the first or second bidirectional ports will act as the output of the BiFIFO and transmit data to the output port.
  • a computer system supplies most of the control signals to the control logic and the hard disk interface supplies signals necessary for any byte/word conversion.
  • the present specification relates to peripheral controllers and methods of operation for half duplex communication between a system and a peripheral.
  • a peripheral controller for half duplex communication between a system and a peripheral, in which a system clock and a peripheral clock are asynchronous
  • the peripheral controller comprising: a FIFO including a FIFO controller and a FIFO memory and having a plurality of inputs to the FIFO; and a multiplexer circuit having a plurality of electronically controllable switches each controllable by a selection signal, wherein the plurality of controllable switches includes:
  • the first group of signals may include one, or a plurality, or all of a system clock signal, a system write enable signal, a system data in signal, a peripheral clock signal and a peripheral read enable signal.
  • the second group of signals may include one, or a plurality, or all of a peripheral clock signal, a peripheral write enable signal, a peripheral data in signal, a system clock signal and a system read enable signal.
  • the FIFO memory may include a single data output.
  • the peripheral controller may include a peripheral data output path in communication with the single data output and connectable to a peripheral bus and/or a system data output path in communication with the single data output and connectable to a system bus.
  • the plurality of controllable switches may include a data input signal switch having a system data input, a peripheral data input and an output.
  • the output may be connected to a data input of the FIFO memory.
  • the data input of the FIFO memory may be the only input to the FIFO memory for peripheral data or system data.
  • the multiplexer circuit may provide a write interface of the FIFO and/or a read interface of the FIFO.
  • the write interface When the selection signal has a first value, the write interface may be connected to a system side and the read interface may be connected to a peripheral side.
  • the selection signal When the selection signal has a second value, the write interface may be connected to the peripheral side and the read interface may be connected to the system side.
  • the first value may be or correspond to a logic high value.
  • the second value may be or correspond to a logic low value.
  • the peripheral controller may further include: a peripheral data transmitter having an input in communication with a data output of the FIFO memory and having an output connectable to a peripheral bus; and/or a peripheral data receiver having an output in communication with a data input of the FIFO memory and having an input connectable to a peripheral bus.
  • the peripheral controller may further include an input/output configuration register in communication with the FIFO and connectable to a system bus.
  • the input/output configuration register may include a location for storing a selection data item and may be arranged to supply the selection signal to the multiplexer circuit. A property of the selection signal may depend on a value of the selection data item.
  • a package comprising a lead frame and a semi-conductor integrated circuit, wherein the semi-conductor integrated circuit is configured to provide the peripheral controller of the first aspect.
  • an electronic device including: a processor; a system bus connected to the processor; a peripheral bus; a peripheral connected to the peripheral bus; and the peripheral controller according to the first aspect connected to the system bus and the peripheral bus.
  • the data processing apparatus 100 includes a main data processing system 102 and at least one peripheral device 104. Further peripheral devices 106 may also be provided, as indicated by dashed lines.
  • the peripheral device, or devices, and the main data processing system may be provided as a single integrated data processing apparatus or device, e.g. a mobile phone, laptop, gaming device, tablet, etc.
  • the main or central data processing system 102 includes at least a main data processor 110, which may be in the form of a central processing unit or part of a microcontroller.
  • the data processor 110 is connected to a system bus 112 to which other parts of the main data processing system 102 are attached, as illustrated by dashed box 114.
  • the main data processing system may also include various memory and storage devices, various interfaces and similar, as are generally known in the art and which are not shown in Figure 1 so as not to obscure the disclosure.
  • a peripheral controller 116 is also provided and is in communication with the system bus 112 and also in communication with a peripheral bus 118 to which the one or more peripheral devices 104, 106 are attached.
  • the peripheral controller 116 provides various interfacing operations to permit half duplex communication between the peripheral devices 104, 106 and the data processing system 102.
  • the data processing system 102 has a system clock signal and the peripheral bus 118 has a peripheral clock signal, and the system clock and peripheral clock are asynchronous.
  • the peripheral controller 116 is configured to implement a half-duplex communication protocol between the main data processing part 102 and the peripherals 104, 106, so that system data can be passed to the peripherals, e.g. for output and/or control, and peripheral data can be passed to the data processing system, e.g. as input and/or control.
  • the peripheral controller may implement various half duplex communication protocols, such as, for example the I 2 C protocol or UART or SPI.
  • the peripheral controller 116 includes an IO configuration register 120, a FIFO 122 a data transmitter 124 and a data receiver 126.
  • the peripheral controller provides data buffering to accommodate the differences in rate or speed of the data processing system and peripheral devices by storing data in the FIFO circuitry 122.
  • the IO configuration register 120 may have data written to it by the data processor 110, or using direct memory access (DMA) when present in the data processing system 102, via the system bus 112 to configure the operation of the peripheral controller.
  • the IO configuration register 120 may include Flop or register based memory elements which are used to store configuration and/or control information for the peripheral controller 116.
  • the IO configuration register 120 includes at least one memory element or location for storing a selection data item, the value of which determines a property of a selection signal which is output to the FIFO and used to configure the FIFO 122 to operate in either a transmission mode, in which data is transmitted from the system side to the peripheral side, or a reception mode, in which data is received at the system side from the peripheral side.
  • the selection data item may take various forms. In one embodiment it may be a single bit, and a value of '1' may corresponds to the transmission mode and a value of '0' may correspond to the reception mode.
  • the data transmitter 124 passes data from the FIFO 122 to the peripheral bus 118 and the data receiver 126 receives data from the peripheral bus 118 and passes the data to the FIFO 122.
  • the data transmitter 124 and data receiver 126 may be implemented as finite state machines and are generally known in the art.
  • FIG. 2 shows a schematic block diagram of the FIFO part 122 of the peripheral controller 116 in greater detail.
  • the FIFO 122 includes a FIFO controller 200 and FIFO memory or storage 202.
  • the FIFO controller 200 can assert a write enable control signal on line 204 and can supply a write address data item on data connection 206 and a read address data item on data connection 208 to the FIFO memory 202.
  • FIFO controller 200 has a write clock input 210, a write enable input 212, a read clock input 214, a read enable input 216, a FIFO full output 218 and a FIFO empty output 220.
  • the FIFO memory 202 has a write clock input 222, a data input 224 and a data output 226.
  • FIFO 122 also has a multiplexer circuit, illustrated by dashed line 229, and including a plurality of multiplexers or controllable switches connected to the various inputs of the asynchronous FIFO 228 and which are operable by a common selection signal, "sel", 240 input to the multiplexer circuit 229 and output by the IO configuration register 120 to select to supply different combinations of system side and peripheral side signals to the FIFO 228 depending on whether it is operating in transmission or reception mode.
  • the switches may be implemented in a number of different ways. Depending on the value of the selection data bit, the selection signal takes a first or second value, and the FIFO 228 may obtain input signals from the different inputs of the individual multiplexers.
  • the multiplexer circuit 229 includes a write clock signal switch 230, a write enable signal switch 232, a read clock signal switch 234, a read enable signal switch 236 and a data input signal switch 238 each operable by the same selection signal, sel, e.g., input 241 to write clock signal switch 230.
  • the write clock signal switch 230 is connected to the write clock input 210 of FIFO controller 200, and also to the write clock input 222 of FIFO memory 220, and has the system clock signal and peripheral clock signal as inputs.
  • the write enable signal switch 232 is connected to the write enable input 212 of FIFO controller 200 and has the system write enable signal and peripheral write enable signal as inputs.
  • the read clock signal switch 234 is connected to the read clock input 214 of FIFO controller 200 and has the peripheral clock signal and system clock signal as inputs.
  • the read enable signal switch 236 is connected to the read enable input 216 of FIFO controller 200 and has the peripheral read enable signal and system read enable signal as inputs.
  • the data in signal switch 238 is connected to the single data input 224 of the FIFO memory 202.
  • the single data output 226 of the FIFO memory communicates with both the system bus 112 and the peripheral bus 118 and provides a system data output signal 242 and a peripheral data output signal 244.
  • the read interface and write interface of the asynchronous FIFO 228 may be connected to different combinations of system and peripheral signals by the multiplexer circuit 229 depending on the value of the selection signal, e.g. 240, used to operate the switches.
  • the selection signal may be logic high or '1' when operating in a transmitter mode and low or '0' when operating in a receiver mode. 2.
  • the selection signal is 1, and the write interface of the asynchronous FIFO 228 is connected to the system side and the read interface of FIFO 228 is connected to the peripheral side.
  • system data can be read from the system bus into FIFO memory 202 and then output to the peripheral bus.
  • the selection signal is 0, and the read interface of the asynchronous FIFO 228 is connected to the system side and the write interface of the FIFO 228 is connected to peripheral side.
  • peripheral data can be read from the peripheral bus into FIFO memory 202 and then output to the system bus.
  • a single asynchronous FIFO 228 can be used for both the transmission and reception paths for half duplex peripheral communication and asynchronous clock signals. This may reduce the gate count used to implement the peripheral controller as a semiconductor integrated circuit.
  • the plurality of switches of the multiplexer circuit 229 are controlled by the selection signal 240 which is output by the IO configuration register and the value of which depends on the selection signal data item currently stored in the IO configuration register 120.
  • Figure 3 shows a flow chart illustrating a method of operation 300 of the peripheral controller 116 including the asynchronous FIFO 122.
  • it is determined at the software level whether any data transfer between the system side and peripheral side is required. If not then then then processing proceeds to 304 and the system waits until some data transfer is determined to be needed at 302.
  • it is determined at 302 that data transfer is required, then at 306 it is determined at a software level whether the data is to be transferred from the system side to the peripheral, corresponding to the transmission mode of operation, or whether the data is to be transferred from the peripheral side to the system, corresponding to the reception mode of operation.
  • the processor 110 If system transmission is determined at 306, then at 308 the processor 110 writes a '1' to the selection data item address or location in the IO configuration register 120 via the system bus 112. Consequently the selection signal 240 is set to a high value and at 310 the 'high' selection signal is applied to the multiplexer circuit 229 and the write and read interfaces of the FIFO 228 are configured by operating the plurality of switches to allow system data to be transmitted to the peripheral.
  • the system clock signal is supplied to the write clock inputs of the FIFO controller and FIFO memory
  • the system write enable signal is supplied to the write enable input of the FIFO controller
  • the system data input signal is supplied to the data input of the FIFO memory
  • the peripheral clock signal is supplied to the read clock input of the FIFIO controller
  • the peripheral read enable signal is supplied to the read enable input of the FIFO controller.
  • the data output of the FIFO memory 226 is supplied to the peripheral bus and system bus.
  • system data received from the system bus 112 is input to, and buffered by, FIFO memory 202.
  • the system data is read from the FIFO memory 202 by the data transmitter 124 and passed to the peripheral bus and the system bus.
  • the data is only read from the peripheral bus as only the peripheral device is currently expecting to receive data.
  • the fifo_full and fifo_empty signals may be used to manage the buffering of data by the FIFO 228 in a conventional way as is generally known in the art. It will be understood that as used herein, unless indicated otherwise, data is used generally to refer to command, control or addressing data as well as actual content or payload data.
  • processing proceeds to 318 and processor 110 writes a '0' to the selection data item address or location in the IO configuration register 120 via the system bus 112. Consequently, the selection signal 240 output by the IO configuration register 120 is set to a low value and supplied to the multiplexer circuit 229 at 320 so that the write and read interfaces of the FIFO 122 are configured by operating the plurality of switches to allow peripheral data to be received from the peripheral.
  • the peripheral clock signal is supplied to the write clock inputs of the FIFO controller and FIFO memory
  • the peripheral write enable signal is supplied to the write enable input of the FIFO controller
  • the peripheral data input signal is supplied to the data input of the FIFO memory
  • the system clock signal is supplied to the read clock input of the FIFIO controller
  • the system read enable signal is supplied to the read enable input of the FIFO controller.
  • the data output of the FIFO memory 226 is supplied to the system bus and peripheral bus.
  • peripheral data from the peripheral bus 118 is forwarded by the receiver 126 and input to, and buffered by, FIFO memory 202 at 322.
  • the peripheral data is read from the FIFO memory 202 and passed to the system bus and peripheral bus.
  • the data is read from the system bus only and is supplied to the appropriate system side destination, e.g. processor 110.
  • the fifo_full and fifo_empty signals may be used to manage the buffering of data by the FIFO 228 in a conventional way, as is generally known in the art, during the transfer of data from the peripheral side to the system side.
  • this technique may reduce the gate-count of an integrated circuit implementation of the peripheral controller 116 by sharing a single asynchronous FIFO 128 for half-duplex peripheral communication, as used for example by i2c and similar, and with peripheral and system clocks which are asynchronous.
  • the peripheral controller 116 may be provided as a package comprising a lead frame and die comprising a semi-conductor integrated circuit.
  • the semi-conductor integrated circuit may be configured to provide the peripheral controller as illustrated in Figures 1 and 2 above.

Claims (10)

  1. Peripheriesteuereinheit (116) für eine Halb-Duplex-Kommunikation zwischen einem System und einem Peripheriegerät, wobei ein Systemtakt und ein Peripherietakt nicht synchron sind, wobei die Peripheriesteuereinheit Folgendes umfasst:
    einen FIFO (228), der eine FIFO-Steuereinheit (200) und einen FIFO-Speicher (202) enthält und mehrere Eingänge des FIFO besitzt; und
    eine Multiplexerschaltung (229) mit mehreren elektronisch steuerbaren Schaltern, die jeweils durch ein Auswahlsignal steuerbar sind, wobei die mehreren steuerbaren Schalter Folgendes enthalten:
    einen Taktsignalschalter (230) mit einem Systemtakteingang, einem Peripherietakteingang und einem Ausgang, wobei der Ausgang mit einem Schreibtakteingang (210) der FIFO-Steuereinheit (200) und einem Schreibtakteingang (222) des FIFO-Speichers (202) verbunden ist;
    einen Schreibaktivierungssignalschalter (232) mit einem Systemschreibaktivierungseingang, einem Peripherieschreibaktivierungseingang und einem Ausgang, wobei der Ausgang mit einem Schreibaktivierungseingang (212) der FIFO-Steuereinheit (200) verbunden ist;
    einen Lesetaktsignalschalter (234) mit einem Peripherietakteingang, einem Systemtakteingang und einem Ausgang, wobei der Ausgang mit einem Lesetakteingang (214) der FIFO-Steuereinheit (200) verbunden ist; und
    einen Leseaktivierungssignalschalter (236) mit einem Peripherieleseaktivierungseingang, einem Systemleseaktivierungseingang und einem Ausgang, wobei der Ausgang mit einem Leseaktivierungseingang (216) der FIFO-Steuereinheit (200) verbunden ist,
    wobei die Multiplexerschaltung durch das Auswahlsignal (240) betreibbar ist, entweder eine erste Gruppe von System- und Peripheriesignalen oder eine zweite Gruppe von System- und Peripheriesignalen, die von der ersten Gruppe verschieden sind, an den FIFO (228) zu senden, um den FIFO zu betreiben, um Daten von dem System an das Peripheriegerät zu senden oder Daten von dem Peripheriegerät bei dem System zu empfangen.
  2. Peripheriesteuereinheit (116) nach Anspruch 1, wobei die erste Gruppe von Signalen ein Systemtaktsignal, ein Systemschreibaktivierungssignal, ein Systemeingangsdatensignal, ein Peripherietaktsignal und ein Peripherieleseaktivierungssignal enthält.
  3. Peripheriesteuereinheit (116) nach Anspruch 1 oder 2, wobei die zweite Gruppe von Signalen ein Peripherietaktsignal, ein Peripherieschreibaktivierungssignal, ein Peripherieeingangsdatensignal, ein Systemtaktsignal und ein Systemleseaktivierungssignal enthält.
  4. Peripheriesteuereinheit (116) nach einem der Ansprüche 1 bis 3, wobei der FIFO-Speicher (202) einen einzigen Datenausgang (226) enthält und wobei die Peripheriesteuereinheit einen Peripheriedatenausgangsweg in Kommunikation mit dem einzigen Datenausgang und verbindbar mit einen Peripheriebus und einen Systemdatenausgangsweg in Kommunikation mit dem einzigen Datenausgang und verbindbar mit einem Systembus enthält.
  5. Peripheriesteuereinheit (116) nach einem der Ansprüche 1 bis 4, wobei die mehreren steuerbaren Schalter einen Dateneingangssignalschalter (238) mit einem Systemdateneingang, einem Peripheriedateneingang und einem Ausgang enthalten und wobei der Ausgang mit einem Dateneingang (224) des FIFO-Speichers (202) verbunden ist und wobei der Dateneingang des FIFO-Speichers der einzige Eingang zu dem FIFO-Speicher für Peripheriedaten oder Systemdaten ist.
  6. Peripheriesteuereinheit (116) nach einem der Ansprüche 1 bis 5, wobei die Multiplexerschaltung (229) eine Schreibschnittstelle des FIFO (228) und eine Leseschnittstelle des FIFO (228) bereitstellt und wobei dann, wenn das Auswahlsignal (240) einen ersten Wert besitzt, die Schreibschnittstelle mit einer Systemseite verbunden ist und die Leseschnittstelle mit einer Peripherieseite verbunden ist und dann, wenn das Auswahlsignal (240) einen zweiten Wert besitzt, die Schreibschnittstelle mit der Peripherieseite verbunden ist und die Leseschnittstelle mit der Systemseite verbunden ist.
  7. Peripheriesteuereinheit nach einem der Ansprüche 1 bis 6 und die ferner ein Eingangs-/Ausgangskonfigurationsregister (120) in Kommunikation mit dem FIFO und verbindbar mit einem Systembus enthält, wobei das Eingangs-/Ausgangskonfigurationsregister einen Ort zum Speichern eines Auswahldatenelements enthält und ausgelegt ist, das Auswahlsignal an die Multiplexerschaltung zu liefern, und wobei eine Eigenschaft des Auswahlsignals von einem Wert des Auswahldatenelements abhängt.
  8. Baugruppe, die einen Leiterrahmen und eine integrierte Halbleiterschaltung umfasst, wobei die integrierte Halbleiterschaltung konfiguriert ist, eine Peripheriesteuereinheit nach einem der Ansprüche 1 bis 7 bereitzustellen.
  9. Elektronische Vorrichtung, die Folgendes enthält:
    einen Prozessor;
    einen Systembus, der mit dem Prozessor verbunden ist;
    einen Peripheriebus;
    ein Peripheriegerät, das mit dem Peripheriebus verbunden ist; und
    die Peripheriesteuereinheit nach einem der Ansprüche 1 bis 7, die mit dem Systembus und dem Peripheriebus verbunden ist.
  10. Verfahren zum Betrieben einer Peripheriesteuereinheit, um eine Halb-Duplex-Kommunikation zwischen einem Systembus und einem Peripheriebus unter Verwendung eines FIFO mit einer Multiplexerschaltung, die durch ein Auswahlsignal betreibbar ist und mit mehreren Eingängen des FIFO verbunden ist, bereitzustellen, wobei die Multiplexerschaltung eine Schreibschnittstelle des FIFO und eine Leseschnittstelle des FIFO bereitstellt, wobei die Multiplexerschaltung mehrere elektronisch steuerbare Schalter besitzt, die jeweils durch das Auswahlsignal steuerbar sind, wobei die mehreren steuerbaren Schalter Folgendes enthalten:
    einen Taktsignalschalter (230) mit einem Systemtakteingang, einem Peripherietakteingang und einem Ausgang, wobei der Ausgang mit einem Schreibtakteingang (210) der FIFO-Steuereinheit (200) und einem Schreibtakteingang (222) des FIFO-Speichers (202) verbunden ist;
    einen Schreibaktivierungssignalschalter (232) mit einem Systemschreibaktivierungseingang, einem Peripherieschreibaktivierungseingang und einem Ausgang, wobei der Ausgang mit einem Schreibaktivierungseingang (212) der FIFO-Steuereinheit (200) verbunden ist;
    einen Lesetaktsignalschalter (234) mit einem Peripherietakteingang, einem Systemtakteingang und einem Ausgang, wobei der Ausgang mit einem Lesetakteingang (214) der FIFO-Steuereinheit (200) verbunden ist; und
    einen Leseaktivierungssignalschalter (236) mit einem Peripherieleseaktivierungseingang, einem Systemleseaktivierungseingang und einem Ausgang, wobei der Ausgang mit einem Leseaktivierungseingang (216) der FIFO-Steuereinheit (200) verbunden ist,
    wobei das Verfahren Folgendes umfasst:
    Einstellen des Auswahlsignals auf einen ersten Wert, um die Schreibschnittstelle mit einer Systemseite und die Leseschnittstelle mit einer Peripherieseite zu verbinden und eine erste Gruppe von System- und Peripheriesignalen an den FIFO über den Multiplexer zu liefern, um den FIFO zu betreiben, um Daten von dem Systembus zu dem Peripheriebus zu übermitteln; und
    Einstellen des Auswahlsignals auf einen zweiten Wert, um die Schreibschnittstelle mit der Peripherieseite und die Leseschnittstelle mit der Systemseite zu verbinden und eine zweite Gruppe von System- und Peripheriesignalen, die von der ersten Gruppe verschieden sind, an den FIFO über den Multiplexer zu liefern, um den FIFO zu betreiben, um Daten von dem Peripheriebus an den Systembus zu übermitteln.
EP15190439.8A 2015-10-19 2015-10-19 Periphere steuereinheit Active EP3159805B1 (de)

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Application Number Priority Date Filing Date Title
EP15190439.8A EP3159805B1 (de) 2015-10-19 2015-10-19 Periphere steuereinheit
US15/262,746 US10366043B2 (en) 2015-10-19 2016-09-12 Peripheral controller

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EP15190439.8A EP3159805B1 (de) 2015-10-19 2015-10-19 Periphere steuereinheit

Publications (2)

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EP3159805A1 EP3159805A1 (de) 2017-04-26
EP3159805B1 true EP3159805B1 (de) 2020-04-15

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US20170109314A1 (en) 2017-04-20
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