EP3098807B1 - Tiled-viewport-anordnung - Google Patents

Tiled-viewport-anordnung Download PDF

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Publication number
EP3098807B1
EP3098807B1 EP16179806.1A EP16179806A EP3098807B1 EP 3098807 B1 EP3098807 B1 EP 3098807B1 EP 16179806 A EP16179806 A EP 16179806A EP 3098807 B1 EP3098807 B1 EP 3098807B1
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EP
European Patent Office
Prior art keywords
buffer
application image
viewport
tiles
tile
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EP16179806.1A
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English (en)
French (fr)
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EP3098807A1 (de
Inventor
Etienne Belanger
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2236008 Ontario Inc
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2236008 Ontario Inc
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Priority to EP16179806.1A priority Critical patent/EP3098807B1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Definitions

  • This disclosure relates to graphics and, in particular, to graphics buffers.
  • GUI Graphical user interfaces
  • PiP Picture in Picture
  • other types of graphical images may be composited from multiple independently rendered images.
  • a GUI may contain a background image and one or more rendered graphic layers on top of the background image.
  • the graphic layers may comprise applications, task bars, or other type of graphic elements.
  • Each of the graphic layers may be rendered in an application buffer independently of the other graphic layers by individual software applications.
  • the graphic layers may be composited together into a single composite image in a display buffer, which may be presented on a display device, transmitted over a network, or otherwise processed.
  • the application buffer may represent an image that is larger than the corresponding graphic layer composited into the single composite image.
  • EP 0 312 720 A2 describes a graphic display system comprising a video display controller including two similar frame buffer memories for alternatively receiving and storing incoming pixel data and for periodically refreshing a display on a screen selectively in accordance with pixel data stored by either one of the two frame buffer memories. While the video display controller periodically refreshes the screen display in accordance with the pixel data stored in a first of the frame buffer memories, incoming pixel data is stored in the second frame buffer memory. The video display controller begins periodically refreshing the screen display in accordance with the pixel data stored in the second frame buffer memory. Updated pixel data stored in the second frame buffer memory is then copied into the first frame buffer memory.
  • WO2005/069271 A1 describes a secondary frame buffer for use by classic applications designed to paint directly to a frame buffer.
  • US5877762 describes methods and apparatus for capturing images on screens which display multiple windows.
  • US20040179019 A1 describes tile buffers in a graphics processing system that are managed using "copy-on-write" semantics, in which tile data stored in a memory location is not transferred to another location until the tile data for one of the buffers is modified.
  • US 2010/0281402 relates to software-based asynchronous backing stores, including a backing store and a display buffer.
  • US5933155 relates to a system and method for buffering multiple frames by controlling and bounding render- 2 display latency.
  • a system for buffering an application image may include a composition manager and a memory comprising a front buffer and a back buffer.
  • the application image may be logically divided or separated into tiles. Each of the tiles may identify a corresponding area of the application image.
  • the composition manager may determine which of the tiles are overlapped by a viewport.
  • the viewport may identify a visible portion of the application image. The visible portion may be smaller than the application image. For example, the visible portion may be a portion of a map that is displayed on a display device in a navigation system.
  • the composition manager (or an application that renders the application image) may double buffer (or more generally, multiple buffer) the tiles that the viewport overlaps.
  • the composition manager (or the application) may not double buffer (or multiple buffer) the tiles that the viewport does not overlap. Reducing the amount of memory that is multiple buffered may reduce bandwidth requirements for accessing the memory.
  • Double buffering may prevent visual tearing artifacts caused when one process writes to a buffer while another process reads from the same buffer.
  • the application may render the application image in the back buffer while another process, such as the composition manager, reads the application image from the front buffer.
  • a buffer that the system writes to in order to construct a frame of the application image may be the back buffer.
  • a buffer that the system reads the completed frame from may be the front buffer.
  • the system may include and use multiple back buffers.
  • the front buffer and the back buffer may be switched such that the back buffer becomes the front buffer, and the front buffer becomes the back buffer.
  • the buffer switch may also be referred to as a buffer flip.
  • the back buffer may include the contents of frame n
  • the front buffer may include the contents of frame n+1. If the entire contents of the front buffer (frame n+1) is copied to the back buffer (frame n), then the back buffer may have the most recent contents (frame n+1), and the application may begin rendering a new frame, n+2 in the back buffer. The process of rendering, flipping, and displaying may be repeated.
  • the composition manager and/or the application may skip double buffering (or multiple buffering) of the tiles that the viewport does not overlap.
  • the composition manager and/or the application may buffer the tiles that are overlapped by the viewport in both the front and back buffers, and buffer the tiles that are not overlapped by the viewport in the back buffer but not in the front buffer.
  • Each of the tiles may be buffered in a corresponding tile buffer.
  • the tile buffers may be noncontiguously arranged in memory. Two buffers may be noncontiguous if the buffers are not adjacent to each other in the memory address space of the memory that the buffers are in.
  • the composition manager may copy a buffered visible portion of the application image directly from the noncontiguous tile buffers based on the composition manager having knowledge of the viewport and the tile buffers.
  • the application does not need to create an intermediate buffer that contains the buffered visible portion of application image in contiguous memory so that the composition manager may copy the visible portion from the contiguous memory. Avoiding the creation of the intermediate buffer reduces the bandwidth requirements for accessing memory.
  • the composition manager may generate a composite image from the visible portion of the application image and one or more additional application images.
  • FIG. 1 illustrates a tiled viewport composition system 100.
  • the system 100 may include an application 102, application buffers 104, a display buffer 106, and a composition manager 108.
  • the tiled viewport composition system 100 is a system for buffering an application image 110.
  • the application 102 may render the application image 110.
  • the application image 110 may include a window generated by a windows based operating system, such an operating system for a mobile electronic device, a desktop computer, or a server.
  • windows based operating system may include MICROSOFT WINDOWS®, which is a registered trademark of Microsoft Corporation of Redmond, Washington; LINUX®, which is a registered trademark of Linus Torvalds of Finland; and ANDROIDTM, which is a trademark of Google, Inc. of Mountain View, California.
  • the application image 110 may include a Graphical User Interface (GUI), a Picture in Picture (PiP), a task bar, a background picture, a frame in a sequence of frames that may be part of a video, or any other type of digital image.
  • GUI Graphical User Interface
  • PiP Picture in Picture
  • a task bar a background picture
  • background picture a frame in a sequence of frames that may be part of a video
  • any other type of digital image may be any other type of digital image.
  • Examples of the application 102 may include a word processing program, a mail program, a web browser, a mobile application, or other types of software program or hardware component that may render the application image 110.
  • the application buffers 104 may be one or more areas of memory that represent the application image 110 and/or portions thereof.
  • the memory may include contiguous and/or noncontiguous areas of memory.
  • the display buffer 106 may comprise an area of memory that represents a composite image 112 assembled from individual images generated by one or more applications, such as the application 102 illustrated in FIG. 1 .
  • the composite image 112 may be presented on a display device, transmitted over a network, or locally or remotely processed.
  • the composition manager 108 may composite or direct the composition of the individual images into the composite image 112.
  • the individual images may include all or a portion of application images.
  • Examples of the composition manager 108 include a hardware compositor, a window manager, or any other component that composites individual images into the composite image 112.
  • the composition manager 108 may render the composite image 112 from a visible portion of the application image 110 identified by a viewport 114.
  • the visible portion identified by the viewport 114 may be smaller than the entire application image 110.
  • the composition manager 108 may render the composite image 112 from the visible portion of the application image 110 and from one or more additional images.
  • the application 102 may move the viewport 114 around the application image 110 as the visible portion of the application image 110 changes over time.
  • the application image 110 may be a map image, and the viewport 114 identifies the portion of the map image that is to be displayed in a navigation system. As the location of the navigation system changes, the portion of the map image displayed in the navigation system may also change.
  • the application image 110 may be an image of a level in a video game, and the viewport 114 may identify the portion of an image of the level that is to be displayed on a screen. As a game character moves around the level, the portion of the image of the level displayed on the screen changes.
  • a webpage viewer may render more content than may be shown on the display.
  • the composite image 112 may update more quickly, or produce a visibly smoother transition appearance, when the application 102 uses the viewport 114 to update the visible portion of the application image 110.
  • the application 102 may logically divide or partition the application image 110 into tiles 116.
  • Each of the tiles 116 may identify a corresponding area of the application image 110.
  • the tiles 116 may be uniform in size and shape throughout the application image 110. Alternatively, the size and the shape of the tiles 116 may vary throughout the application image 110. The size and shape of the tiles 116 may be different in different examples.
  • the tiles 116 may be represented in corresponding tile buffers 118.
  • the tiles 116 that are individually designated T1-T4 in FIG. 1 may be represented in the tile buffers 118 that are individually designated A1-A4.
  • the tile buffers 118 may be included in the application buffers 104.
  • the composition manager 108 may determine which of the tiles 116 are overlapped by the viewport 114. Each of the tiles 116 that are overlapped or intersected by the viewport 114 may contain at least part 120 of the visible portion of the application image 110. In contrast, the tiles 116 that are not overlapped by the viewport 114 may not contain any visible part 120 of the application image 110.
  • the composition manager 108 may double buffer the tiles 116 that are overlapped by the viewport 114, but not the remaining tiles 116.
  • a front buffer 122 may include the tile buffers 118 (A3 and A4) representing the tiles 116, (T3 and T4) overlapped by the viewport 114. Accordingly, the tile buffers 118 (A3 and A4) in the front buffer 122 include a buffered visible portion 124 of the application image 110.
  • a back buffer 126 may include the tile buffers 118 (A1 and A2) representing the tiles 116 (T1 and T2) not overlapped by the viewport 114.
  • the back buffer 126 may include the tile buffers 118 (B3 and B4) that correspond to the tile buffers 118 (A3 and A4) that are in the front buffer 122 and that represent the tiles 116 overlapped by the viewport 114.
  • the composition manager 108 may extract the buffered visible portion 124 of the application image 110 from the tile buffers 118 (A3 and A4) that are in the front buffer 122.
  • the buffered visible portion 124 may be of frame n of the application image 110.
  • the application 102 may render frame n+1 of the application image 110 in the back buffer 126 by modifying the tile buffers 118 (A1, A2, B3, and B4) that are in the back buffer 126.
  • the composition manager 108 may copy the contents of a subset of the tile buffers 118 that are in the back buffer 126 to the front buffer 122.
  • the subset of the tile buffers 118 may be the tile buffers 118 (B3 and B4) that correspond to the tile buffers 118 (A3 and A4) that are in the front buffer 122.
  • the composition manager 108 may skip copying tile buffers 118 (A1 and A2) representing the tiles 116 (T1 and T2) not overlapped by the viewport 114 to the front buffer 122.
  • the composition manager 108 may change an association between the tile buffers 118 and the front and back buffers 122 and 126.
  • the composition manager 108 may track, in a data structure, which of the tile buffers 118 are associated with the front buffer 122, and which of the tile buffers 118 are associated with the back buffer 126.
  • the associations between the tile buffers 118 and the front and back buffers 122 and 126 indicate which of the tile buffers 118 are included in each of the front and back buffers 122 and 126.
  • the composition manager 108 may disassociate the subset of the tile buffers 118 (B3 and B4) from the back buffer 126, and associate the subset of the tile buffers 118 (B3 and B4) with the front buffer 122.
  • the composition manager 108 may change the tile buffers 118 (A3 and A4) that were originally associated with the front buffer 122 to be associated with the back buffer 126.
  • the composition manager 108 in response to the buffer flip, may swap a first set of the tile buffers 118 associated with the front buffer 122 with a second set of the tile buffers 118 associated with the back buffer 126, where the tile buffers 118 that are swapped represent the tiles 116 that the viewport 114 overlaps but not the tiles 116 that the viewport 114 does not overlap.
  • the tile buffers 118 swapped into the back buffer 126 may represent an older frame, such as frame n.
  • the tile buffers 118 swapped into the front buffer 126 may represent frame n+1.
  • the application 102 may render a third frame, such as frame n+2, in the back buffer 126.
  • the composition manager 108 may double buffer the newly overlapped tile 116. Conversely, when the viewport 114 moves and no longer overlaps one of the tiles 116, then the composition manager 108 may stop double buffering the previously overlapped tile 116.
  • the composition manager 108 may adjust which of the tile buffers 118 are in the front buffer 122 so that the tile buffers 118 in the front buffer 122 correspond to the tiles 116 overlapped by the viewport 114. Similarly, when the viewport 114 moves, the composition manager 108 may adjust which of the tile buffers 118 are in the back buffer 126.
  • the tile buffer 118 in the back buffer 126 that corresponds to the newly overlapped tile 116 may be included in the front buffer 122.
  • the tile buffer 118 added to the front buffer does not need to be completely re-rendered because the application 102 may have already rendered the tile buffer 118 in the back buffer 126.
  • the tile buffers 118 may be dynamically allocated and freed as the viewport 114 moves. For example, if the viewport 114 moves and overlaps four of the tiles 116 (T1-T4) illustrated in FIG. 1 instead of two of the tiles 116 (T3 and T4), then the composition manager 108 may dynamically allocate two tile buffers 118 (B1 and B2, which are not shown in FIG. 1 ). The front buffer 122 may then include four of the tile buffers 118 (A1-A4), and the back buffer 126 may include the four corresponding tile buffers 118 (B1-B4).
  • the tile buffers 118 may be allocated in advance. For example, upon an initialization requested by the application 102, the composition manager 108 may allocate enough of the tile buffers 118 to fully represent the application image 110 in both the back buffer 126 and the front buffer 122. The composition manager 108 may dynamically associate the pre-allocated tile buffers 118 to the front and back buffers 122 and 126.
  • the application 102 and the composition manager 108 may have different features than those described.
  • the composition manager 108 (instead of the application 102) may divide or partition the application image 110 into tiles 116.
  • the application 102 may invoke an API (Application Programming Interface) to indicate to the composition manager 108 the size of the application image 110.
  • the composition manager 108 may divide the application image 110 into the tiles 116 and allocate the corresponding tile buffers 118.
  • the application 102 (instead of the composition manager 108) may double buffer the tiles 116 that are overlapped by the viewport 114, but not the remaining tiles 116.
  • one or more components other than the application 102 and the composition manager 108 may execute described functions of the application 102 and the composition manager 108.
  • the composition manager 108 may render the composite image 112 from the visible portion of the application image 110 identified by the viewport 114.
  • the composition manager 108 having knowledge of the tile buffers 118 and the viewport 114, may copy the buffered visible portion 124 directly from the tile buffers 118 in the front buffer 122 to the display buffer 106 even if the buffered visible portion 124 is spread across multiple noncontiguous tile buffers 118. Copying the buffered visible portion 124 from the tile buffers 118 in the front buffer to an intermediate buffer, and then copying from the intermediate buffer to the display buffer 106 may be unnecessary.
  • the application 102 may provide the composition manager 108 with information about the viewport 114 and about the tile buffers 118 in the front buffer 122.
  • the composition manager 108 may use the information provided by the application 102 to copy the buffered visible portion 124 from the tile buffers 118 in the front buffer 122 to the display buffer 106. Alternatively, the composition manager 108 may render the composite image 112 from an intermediate buffer. The intermediate buffer may be populated by the application 102 by copying from the buffered visible portion 124 in the front buffer 122.
  • the frame of the application image 110 represented in the front buffer 122 may be frame n or any other frame.
  • the frame of the application image 110 represented in the back buffer 126 may be frame n+1 or any other frame.
  • the composition manager 108, the application 102, and/or some other component may double buffer the tiles 116 that are overlapped or lie or extend and cover part of by the viewport 114.
  • the composition manager 108 and/or the application 102 may apply multiple buffering to the tiles 116 that are overlapped by the viewport 114, and not to the tiles 116 that are not overlapped by the viewport 114.
  • Multiple buffering may include double buffering, triple buffering, or other buffering processes and/or hardware that includes storing one or more frames of the application image 110 in one or more front buffers for extraction of the application image 110, and storing one or more frames of the application image 110 in one or more back buffers for rendering of the application image 110.
  • FIG. 2 is a hardware diagram of the tiled viewport composition system 100.
  • the tiled viewport composition system 100 may include a processor 204, a memory interface 206, and a memory 208.
  • the tiled viewport composition system 100 may be referred to simply as the system 100.
  • the processor 204 may be hardware that executes computer executable instructions or computer code embodied in the memory 208 or in other memory to perform one or more features of the tiled viewport composition system 100.
  • the processor 204 may include a general processor, a central processing unit, a graphics processing unit, an application specific integrated circuit (ASIC), a digital signal processor, a field programmable gate array (FPGA), a digital circuit, an analog circuit, a microcontroller, any other type of processor, or any combination thereof.
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the memory interface 206 may manage the transportation of data going to and from the memory 208, such as between the processor 204 and the memory 208.
  • the memory interface 206 may include any memory controller, such as a Memory Chip Controller (MCC), a Double Data Rate2 (DDR2) memory controller used to drive DDR2 SDRAM (double data rate synchronous dynamic random-access memory), a Peripheral Component Interconnect (PCI) bus controller, or any other type of memory controller.
  • MCC Memory Chip Controller
  • DDR2 Double Data Rate2
  • PCI Peripheral Component Interconnect
  • the memory interface 206 may communicate with the memory 208 over a bus 214, such as a 64 bit DDR2 bus operating at 400 Megahertz or any other type of bus.
  • the memory 208 may comprise a device for storing and retrieving data or any combination thereof.
  • the memory 208 may include non-volatile and/or volatile memory, such as a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or a flash memory.
  • RAM random access memory
  • ROM read-only memory
  • EPROM erasable programmable read-only memory
  • flash memory Alternatively or in addition, the memory 208 may include an optical, magnetic (hard-drive) or any other form of data storage device.
  • the memory 208 may store computer code, such as the composition manager 108, the application 102, and/or any other application.
  • the computer code may include instructions executable with the processor 204.
  • the computer code may be written in any computer language, such as C, C++, assembly language, shader code, channel program code, and/or any combination of computer languages.
  • the memory 208 may include buffers, such as the application buffers 104 and the display buffer 106.
  • the application buffers 104 may include the tile buffers 118.
  • the system 100 may include more, fewer, or different components than illustrated in FIGS. 1 and 2 .
  • the system 100 may also include a display controller 210 and a display device 212.
  • the display controller 210 may read the composite image 112 from the display buffer 106 through the memory interface 206 and cause the composite image 112 to be displayed in the display device 212.
  • the processor 204 may be in communication with the memory 208 via the memory interface 206.
  • the processor 204 may be in communication with other components, such as the display controller 210 and/or a network controller (not shown).
  • each one of the components of system 100 may include more, fewer, or different elements than is illustrated in FIGS. 1 and 2 .
  • the memory 208 may include more, fewer, or different modules, graphics buffers, and applications.
  • the application 102 and/or the composition manager 108 may include various modules. Flags, data, databases, tables, entities, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be distributed, or may be logically and physically organized in many different ways.
  • the components may operate independently or be part of a same program or hardware.
  • the components may be resident on separate hardware, such as separate removable circuit boards, or share common hardware, such as a same memory and processor for implementing instructions from the memory. Programs may be parts of a single program, separate programs, or distributed across several memories and processors.
  • one or more of the components of the system 100 may be included in a System on a Chip (SOC) 216.
  • the SOC 216 may include the processor 204, the memory interface 206 and the display controller 210.
  • the SOC 216 may include additional components, such as memory.
  • the system 100 may be implemented in many processes and/or systems. For example, although some features are shown stored in computer-readable memories as logic implemented as computer-executable instructions or as data structures in memory, portions of the system 100 and its logic and data structures may be stored on, distributed across, or read from any other machine-readable storage media. Examples of the storage media may include memories, a cache, a buffer, RAM, a removable media, a hard drive, a hard disk, a floppy disk, a CD-ROM, or any other type of machine-readable or computer-readable storage medium. The media may include any non-transitory computer-readable storage media, such as volatile or non-volatile memory, RAM, ROM, CD-ROM, any other suitable storage device or any combination thereof. Alternatively or in addition, features and/or modules described as logic implemented as computer-executable instructions or as data structures in memory may be implemented in hardware or in a combination of hardware and software, such as in a field programmable gate array (FPGA).
  • FPGA field programmable gate array
  • the functions, acts or tasks illustrated in the figures or described may be executed in response to one or more sets of logic or instructions stored in or on computer readable media.
  • the functions, acts or tasks are independent of the particular type of instructions set, storage media, processor or processing strategy and may be performed by software, hardware, integrated circuits, firmware, micro code and the like, operating alone or in combination.
  • processing strategies may include multiprocessing, multitasking, parallel processing, distributed processing, and/or any other type of processing.
  • the instructions are stored on a removable media device for reading by local or remote systems.
  • the logic or instructions are stored in a remote location for transfer through a computer network or over telephone lines.
  • the logic or instructions may be stored within a given computer, central processing unit (“CPU"), graphics processing unit (“GPU”), or system.
  • the processing capability of the system 100 may be distributed among multiple entities, such as among multiple processors and memories, optionally including multiple distributed processing systems. Parameters and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented with different types of data structures such as linked lists, hash tables, or implicit storage mechanisms. Logic, such as programs or circuitry, may be combined or split among multiple programs, distributed across several memories and processors.
  • FIG. 3 is a flow diagram of the logic of the tiled viewport composition system 100.
  • the application image 110 may be provided as logically divided into the tiles 116.
  • the tile buffers 118 may be in the memory 208 and represent the tiles 116.
  • the logic may determine (310) which of the tiles 116 are overlapped by the viewport 114.
  • the viewport 114 may identify the visible portion of the application image 110, and the visible portion may be smaller than the application image 110.
  • the tiles 116 that are overlapped by the viewport 114 may be buffered (320) in the front buffer 122 and the back buffer 126, where the visible portion of the application image 110 is extracted from the front buffer 122, and the application image 110 is modified in the back buffer 126.
  • the front buffer 122 may buffer frame n
  • the back buffer 126 may buffer frame n+1.
  • the tiles 116 not overlapped by the viewport 114 may be buffered (330) in the back buffer 126 in which the application image 119 is modified but not in the front buffer 122 from which the visible portion of the application image 110 is extracted.
  • the logic may end, for example, by the composition manager 108 extracting the buffered visible portion 124 of the application image 110 from the front buffer 122.
  • the logic may include additional, different, or fewer operations.
  • the logic may include dividing the application image 110 into the tiles 116 by allocating the tile buffers 118.
  • the operations may be executed in a different order than illustrated in FIG. 3 .
  • the phrases "at least one of ⁇ A>, ⁇ B>, ... and ⁇ N>” or “at least one of ⁇ A>, ⁇ B>, ... ⁇ N>, or combinations thereof or " ⁇ A>, ⁇ B>, ... and/or ⁇ N>” are defined by the Applicant in the broadest sense, superseding any other implied definitions herebefore or hereinafter unless expressly asserted by the Applicant to the contrary, to mean one or more elements selected from the group comprising A, B, ... and N, that is to say, any combination of one or more of the elements A, B, ... or N including any one element alone or in combination with one or more of the other elements which may also include, in combination, additional elements not listed.

Claims (8)

  1. System (100) zum Zwischenspeichern einer auf einem Anzeigegerät (212) anzuzeigenden Anwendungsabbildung (110);
    wobei das System Folgendes umfasst:
    einen Prozessor (204), der zum Verbinden mit dem Anzeigegerät (212) konfiguriert und dafür ausgelegt ist, die Anwendungsabbildung (110) in mehrere Kacheln (116) aufzuteilen, wobei jede der Kacheln (116) einen entsprechenden Bereich der Anwendungsabbildung (110) identifiziert; und
    einen computerlesbareren Speicher (208), der Folgendes umfasst:
    einen Satz Kachelzwischenspeicher (118);
    einen Zusammensetzungsmanager (108), der dafür ausgelegt ist, jedem Kachelzwischenspeicher (118) entweder einen Vordergrundzwischenspeicher (122) oder einen Hintergrundzwischenspeicher (126) zuzuordnen;
    wobei der Zusammensetzungsmanager (108) ferner dafür ausgelegt ist, zu bestimmen, welche der Kacheln (116) der Anwendungsabbildung (110) von einem Darstellungsfeld (114) überlagert sind, wobei das Darstellungsfeld (114) einen sichtbaren Teil der Anwendungsabbildung (110) identifiziert, wobei der sichtbare Teil kleiner als die gesamte Anwendungsabbildung ist,
    wobei der Zusammensetzungsmanager dafür ausgelegt ist, den Hintergrundzwischenspeicher (126) so zu belegen, dass er geeignet ist, die durch das Darstellungsfeld (114) überlagerten Kacheln (116) der Anwendungsabbildung (110) und die nicht vom Darstellungsfeld (114) überlagerten Kacheln (116) der Anwendungsabbildung (110) in den dem Hintergrundzwischenspeicher (126) zugeordneten Kachelzwischenspeichern (118) zu speichern und dass jeder dem Hintergrundzwischenspeicher (126) zugeordnete Kachelzwischenspeicher (118) geeignet ist, eine entsprechende Kachel (116) der Anwendungsabbildung (110) zu speichern; und
    wobei der Zusammensetzungsmanager dafür ausgelegt ist, den Vordergrundzwischenspeicher (122) so zu belegen, dass jeder dem Vordergrundzwischenspeicher (112) zugeordnete Kachelzwischenspeicher (118) geeignet ist, eine entsprechende Kachel (116) der Anwendungsabbildung (110) zu speichern und dass der Vordergrundzwischenspeicher (122) geeignet ist, nur die entsprechenden vom Darstellungsfeld (114) überlagerten Kacheln (116) der Anwendungsabbildung (110) zu speichern;
    und wobei das System ferner zum Lesen des sichtbaren Teils aus dem Vordergrundzwischenspeicher (122) zum Anzeigen konfiguriert ist;
    wobei der Zusammensetzungsmanager (108) ferner konfiguriert ist, als Antwort auf ein Zwischenspeicherumschalten den Satz dem Vordergrundzwischenspeicher (122) zugeordneter Kachelzwischenspeicher (118) mit einigen Kachelzwischenspeichern (118) des Satzes dem Hintergrundzwischenspeicher (126) zugeordneter Kachelzwischenspeicher (118) zu tauschen, wobei die getauschten Kachelzwischenspeicher (118) die vom Darstellungsfeld (114) überlagerten Kacheln (116) der Anwendungsabbildung (110) speichern, nicht jedoch die nicht vom Darstellungsfeld (114) überlagerten Kacheln (116) der Anwendungsabbildung (110);
    wobei das System dafür ausgelegt ist, die Anwendungsabbildung vor jedem Zwischenspeichertausch in den Hintergrundzwischenspeicher (126) zu rendern.
  2. System nach Anspruch 1, wobei der Zusammensetzungsmanager ferner konfiguriert ist, festzustellen, dass sich mindestens zwei nicht aneinandergrenzende dem Vordergrundzwischenspeicher zugeordnete Kachelzwischenspeicher (118) mit dem Darstellungsfeld überschneiden, und wobei der Zusammensetzungsmanager ferner konfiguriert ist, den sichtbaren Teil der ersten Anwendungsabbildung direkt aus den mindestens zwei nicht aneinandergrenzenden Kachelzwischenspeichern zu lesen, wobei die mindestens zwei nicht aneinandergrenzenden Kachelzwischenspeicher (118) nicht nebeneinander in einem Speicheradressraum des computerlesbaren Speichers liegen.
  3. System nach Anspruch 1 oder 2, wobei der Zusammensetzungsmanager (108) ferner konfiguriert ist, als Antwort auf eine Anfrage einer Anwendung die Anwendungsabbildung in die Kacheln (116) aufzuteilen.
  4. Verfahren zum Betreiben des Systems nach Anspruch 1, wobei das Verfahren die folgenden Schritte umfasst:
    Bereitstellen der in mehrere Kacheln (116) aufgeteilten Anwendungsabbildung (110) durch den Prozessor, wobei jede der Kacheln (116) einen entsprechenden Bereich der Anwendungsabbildung (110) identifiziert;
    Rendern der Anwendungsabbildung (110) in den Hintergrundzwischenspeicher (126) durch das System;
    Bestimmen durch den Zusammensetzungsmanager (108), welche der Kacheln (116) der Anwendungsabbildung (110) durch ein Darstellungsfeld (114) überlagert sind;
    Tauschen durch den Zusammensetzungsmanager (108) als Antwort auf ein Zwischenspeicherumschalten des Satzes dem Vordergrundzwischenspeicher (122) zugeordneter Kachelzwischenspeicher (118) mit einigen Kachelzwischenspeichern (118) des Satzes dem Hintergrundzwischenspeicher (126) zugeordneter Kachelzwischenspeicher (118), wobei die getauschten Kachelzwischenspeicher (118) die vom Darstellungsfeld (114) überlagerten Kacheln (116) der Anwendungsabbildung (110) speichern, nicht jedoch die nicht vom Darstellungsfeld (114) überlagerten Kacheln (116) der Anwendungsabbildung (110); und nach dem Zwischenspeicherumschalten Rendern eines weiteren Einzelbildes der Anwendungsabbildung in den Hintergrundzwischenspeicher (126) durch das System und Lesen des sichtbaren Teils der zwischengespeicherten Anwendungsabbildung aus dem Vordergrundzwischenspeicher (122); und
    dann, wenn sich das Darstellungsfeld (114) bewegt, Anpassen durch den Zusammensetzungsmanager (108), welche von mehreren Kachelzwischenspeichern (118) im Vordergrundzwischenspeicher (122) sind, mittels des Aufnehmens der den Kacheln (116) der Anwendungsabbildung (110) entsprechenden dem Hintergrundzwischenspeicher (126) zugeordneten Kachelzwischenspeicher (118), die vom Darstellungsfeld (114) neu überlagert sind, in den Vordergrundzwischenspeicher (122).
  5. Verfahren nach Anspruch 4, das ferner das Lesen eines zwischengespeicherten sichtbaren Teils (124) der Anwendungsabbildung direkt aus den mindestens zwei nicht aneinandergrenzenden Kachelzwischenspeichern mit einem Zusammensetzungsmanager (108) umfasst, der Kenntnis des Darstellungsfelds und mindestens zweier nicht aneinandergrenzender, dem Vordergrundzwischenspeicher zugeordneter Kachelzwischenspeicher (118) besitzt, wobei die mindestens zwei nicht aneinandergrenzenden Kachelzwischenspeicher (118) nicht nebeneinander in einem Speicheradressraum des computerlesbaren Speichers liegen.
  6. Computerlesbares Speichermedium, das mit computerausführbaren Anweisungen codiert ist, wobei die computerausführbaren Anweisungen mit einem Prozessor (204) ausführbar sind, um eine Anwendungsabbildung (110) zwischenzuspeichern, wobei das computerlesbare Speichermedium Folgendes umfasst:
    Anweisungen, die ausführbar sind, um das Verfahren nach Anspruch 4 oder 5 zu implementieren.
  7. Computerlesbares Speichermedium nach Anspruch 6, wobei die durch das Darstellungsfeld (114) überlagerten Kacheln (116) mehrfach mit dem Vordergrundzwischenspeicher und mehreren Hintergrundzwischenspeichern einschließlich des Hintergrundzwischenspeichers zwischengespeichert werden und wobei die nicht vom Darstellungsfeld überlagerten Kacheln nicht mehrfach zwischengespeichert werden.
  8. Computerlesbares Speichermedium nach Anspruch 6 oder 7, das ferner Anweisungen umfasst, die ausführbar sind, um als Antwort auf die Bewegung des Darstellungsfeldes den Satz von dem Vordergrundzwischenspeicher (122) zugeordneten Kachelzwischenspeichern (118) mit einigen Kachelzwischenspeichern (118) des Satzes von dem Hintergrundzwischenspeicher (122) zugeordneten Kachelzwischenspeichern (118) zu tauschen.
EP16179806.1A 2012-06-08 2012-06-08 Tiled-viewport-anordnung Active EP3098807B1 (de)

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EP2672480B1 (de) * 2012-06-08 2016-11-16 2236008 Ontario Inc. Tiled-Viewport-Anordnung
KR102275712B1 (ko) 2014-10-31 2021-07-09 삼성전자주식회사 렌더링 방법, 렌더링 장치 및 전자 장치
KR101717355B1 (ko) * 2015-07-29 2017-03-16 엘에스산전 주식회사 에너지 관리 시스템의 디스플레이 장치 및 방법

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CN103489150B (zh) 2017-03-01
CN103489150A (zh) 2014-01-01
CA2817492A1 (en) 2013-12-08

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