EP3095195A1

EP3095195A1 - Delta-sigma modulator

Info

Publication number: EP3095195A1
Application number: EP15700313.8A
Authority: EP
Inventors: Matthias Völker; Johann Hauer
Original assignee: Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Current assignee: Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority date: 2014-01-17
Filing date: 2015-01-14
Publication date: 2016-11-23
Also published as: DE102014200856B3; WO2015107091A1

Abstract

Embodiments provide a delta-sigma modulator for delivering an output signal on the basis of an input signal, comprising an integrator circuit, a first digital-analogue converter, a second digital-analogue converter, an analogue-digital converter and a control circuit. The integrator circuit is designed to deliver the output signal to an integrator output. The first digital-analogue converter (DAC) is coupled to an integrator input and designed to deliver a current on the basis of a first digital signal. The second digital-analogue converter (DAC) is coupled to an integrator output and designed to deliver a current on the basis of a second digital signal. The analogue-digital converter is coupled to the integrator output and designed to deliver the output signal in a digital form. The control circuit is coupled to the analogue-digital converter and designed to generate the first digital signal and the second digital signal on the basis of the digital output signal. The first digital signal describes pulses, and between the pulses the digital signal reverts to a zero value. The second digital signal describes an overlaying of pulses and a variable offset that follows the input signal.

Description

Delta sigma modulator

description

Embodiments of the present invention relate to a delta-sigma modulator for providing an output signal based on an input signal. Further embodiments of the present invention relate to a method for providing an output signal based on an input signal and to a computer program.

PRIOR ART In the case of continuous-time delta-sigma modulators (continuous-time delta-sigma modulators), the sum of an input signal (1 _{! N} ) and a feedback signal (IDAC) is integrated. Typically, the frequency components in the input signal are significantly lower than the used clock frequency of the feedback signal. The output voltage of the integrator is converted to a digital representation (D _A DC) by an analog-to-digital converter (ADC). A digital-to-analogue converter (DAC) is controlled with the aid of an algorithm in such a way that the current I _DAC provided by the DAC corresponds as well as possible to the input current I _{! N} , ie approximates it. An amplifier of the sigma-delta modulator provides an output current (I GAIN AMPLIFIER _Ä), the difference between the _DAC and l l | _N corresponds to, as shown in FIG. 8.

The output current can be expressed by the following relationship:

IVERSTÄRKER ⁼ iDAcHl (1)

A schematic representation of a resulting curve of the amplifier current I VER _¬ STARKER is shown in FIG. 2b. FIG. 2a shows underlying profiles of the input signal l | _N and l _DAC . Demands on the amplifier can be reduced as the resolutions of the DAC and ADC are increased. This is possible if the DAC is continuously ierlich works, that is, so-called non-return-to-zero (NRZ) outputs pulses. A disadvantage of NRZ pulses is that a feedback charge quantity depends on the pulse train of the data stream. Due to the rise and fall times as well as capacitive properties in integrators, the charge quantity varies, for example, between the signal sequence -1, 1, -1, 1, -1, 1 and the sequence 1, 1, 1, -1, -1, -1. This problem can be solved by so-called Return-to-Zero (RZ) pulses. In this case, the pulse duration is reduced, and at the end of a pulse the DAC is turned off, that is, the signal returns to a zero value. The current for providing the amount of charge must be increased accordingly to couple back the same amount of charge as NRZ pulses. Fig. 9 shows a comparison of the pulse shapes NRZ and RZ.

In the case of RZ pulses, the amplifier must deliver a higher current because the difference between the input signal and the feedback signal is greatly increased. The delay of the path from DAC to ADC in Fig. 8 must be minimized as much as possible to ensure the stability of the system.

This means that higher demands are placed on the amplifier for RZ pulses. According to a first variant of the solution, the amplifier can be designed for these higher requirements, which leads to a higher power consumption and an increased space requirement.

According to a second solution variant, as is known, for example, from WO 2010/1 19456 A2, a compensation DAC is connected to the output of the amplifier. As a result, the amplifier need only supply the input current I _{! N} , which changes at a lower frequency than the feedback signal. In addition, errors in the integration of the input current do not lead to instabilities. This variant is shown schematically in FIG. 10.

The disadvantage of this method is that an amplifier output current (I ** GAIN AMPLIFIER _Ä) contract in loading equal to the input current (I | _N) must be. This increases the demands on the amplifier output current.

WO 2010/1 19456 A2 describes one approach to solving this problem for voltage input circuits, but this method can not be applied to current input modulators. A schematic representation of a resulting amplifier current, as made possible by a system according to FIG. 10, is shown in FIG. 11.

Accordingly, it would be desirable to have a delta-sigma modulator which enables a high system stability, a low amplifier current and consequently a low current consumption of the amplifier.

An object of the present invention is to provide delta-sigma modulators which provide reduced demands on the amplifier, e.g. For example, low output current may allow for use of small scale amplifiers, thus providing delta-sigma modulators of smaller size and more energy efficient.

This object is solved by the subject matter of the independent patent claims.

Further advantageous embodiments are the subject of the dependent claims.

Embodiments of the present invention relate to a delta-sigma modulator for providing an output signal based on an input signal. The delta-sigma modulator includes an integrator circuit, a first digital-to-analog converter, a second digital-to-analog converter, an analog-to-digital converter, and a control circuit. The integrator circuit is configured to provide the output signal in an analog form at an integrator output. The first digital-to-analog converter is coupled to an integrator input and configured to provide a current based on a first digital signal that describes pulses and returns to a zero between pulses. The second digital-to-analog converter is coupled to the integrator output and configured to provide a current based on the output signal in the analog form based on a second digital signal that includes a superposition of pulses and a variable offset following the input signal. The analog-to-digital converter is coupled to the integrator output and configured to provide the output signal in a digital form. The control circuit is coupled to the analog-to-digital converter and configured to generate the first digital signal and the second digital signal based on the digital output signal of the analog-to-digital converter. It is advantageous in this exemplary embodiment that the second digital signal can be generated in such a way that a current of the second digital-to-analog converter based on the second digital signal compensates for a current of the amplifier, ie instead of the amplifier, so that The amplifier can provide a lower output current and thus the requirements for the amplifier with respect to the provision of power is reduced.

Further embodiments of the present invention relate to a delta-sigma modulator in which the control circuit is configured to provide the second digital signal such that the offset of the second digital signal at a time when the first digital signal leaves the zero value , is varied.

It is advantageous in this exemplary embodiment that, based on a varying offset, the second digital signal can also be different from zero at times in which the first digital signal has returned to the zero value, and thus over the entire time span a higher charge quantity for compensation of the amplifier current is available. Thus, an increased compensation of the amplifier current and thus a further reduced amplifier current can be achieved. Furthermore, the second digital signal can be differently calculated for times in which the first digital signal has returned to the zero value and for periods in which the pulses of the first digital signal can assume a value other than zero, such as by variable offset.

Further embodiments provide delta-sigma modulators in which the control circuit is configured to determine the offset of the second digital signal to correspond to an estimate of the input signal.

An advantage of this embodiment is that at times when the first digital signal has the zero value by means of the second digital signal can be compensated for the input signal and that this compensation can be done by means of the variable offset, resulting in an amplitude of the current is to be supplied through the amplifier is reduced.

Further embodiments of the present invention provide a delta-sigma modulator further comprising a filter circuit coupled to the second digital-to-analog converter and configured to provide an average of the first digital signal over a number of time increments a resolution of the second digital-to-analog converter is greater than a resolution of the first digital-to-analog converter.

An advantage of this embodiment is that the second digital signal can be generated so that a peak-to-peak value of the amplifier current is further reduced by an amplifier current based on quantization errors of the analog-to-digital converter, by the averaging or Averaging can be reduced.

Further embodiments of the present invention relate to a method and a computer program for providing an output signal based on an input signal.

BRIEF DESCRIPTION OF THE FIGURES Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. Show it:

1 is a schematic block diagram of a delta-sigma modulator for providing an output signal based on an input signal according to an embodiment of the present invention;

Fig. 2a shows the input signals of the integrator circuit in Fig. 1 in a current-time diagram over a time t having five periods. Fig. 2b is a schematic current-time diagram with a profile of an amplifier current of a system belonging to the prior art and having only the first DAC;

FIG. 2c shows a schematic current-time diagram with a profile of the current of the second DAC from FIG. 1 and a resulting amplifier current according to an exemplary embodiment of the present invention; FIG.

Fig. 3a 3b shows a more detailed current-time diagram of the current waveforms of Fig. 2c with the same abscissa as Fig. 3a.

4 is a schematic block diagram of a delta-sigma modulator according to another embodiment of the present invention.

5a shows a schematic current-time diagram of a signal waveform of the current I _DA c and the input signal I _IN according to FIG. 2a. 5b shows a schematic current-time diagram whose ordinate describes a current intensity I and whose abscissa represents the time axis t according to FIGS. 2a-c, 3a, 3b and 5a.

FIG. 6 shows a current-time diagram analogous to FIG. 3b, with exemplary current curves, as can be obtained, for example, with a filtering of the output signal described in FIG. 4; FIG.

7 shows a schematic representation of a graph on whose abscissa the time and on whose ordinate current values are plotted and in which the course of an estimated current ISCHÄTZ is represented, according to an exemplary embodiment of the present invention;

8 shows a delta-sigma modulator according to the prior art; Fig. 9 is a schematic representation of the differences between NRZ and RZ pulses according to the prior art;

10 is a schematic block diagram of another prior art delta-sigma modulator;

FIG. 11 a shows a schematic current-time diagram of the input signals I _DAC and I _{! N} analogous to FIGS. 2 a and 5 a; and

1 1 b shows a schematic current-time diagram over the time t, the courses of DAC currents and a resulting amplifier current according to the delta current.

Sigma modulator of FIG. 10 represents.

Detailed description of embodiments of the present invention Before embodiments of the present invention are explained in more detail in detail with reference to the drawings, it is pointed out that identical, functionally identical or equivalent elements, objects and / or structures in the different figures are provided with the same reference numerals, so that in different Described embodiments of these elements is interchangeable or can be applied to each other.

1 shows a schematic block diagram of a delta-sigma modulator 100 for providing an output signal D _A DC based on an input signal (input) _N. The delta-sigma modulator 100 has an integrator circuit 110 which is designed to provide an analog form A _{ADC of} the output signal D _ADC at an integrator output 1 12.

The delta-sigma modulator 100 further includes an analog-to-digital converter (ADC) 102 coupled to the integrator output 112. The ADC 102 is configured to receive the output signal in an analog form A _ADC , to convert it to a digital form D _AD c, and to provide the output signal in the digital form D _AD c. That is, the ADC 102 is configured to digitize an analog signal provided by the integrator circuit 110 at the integrator output 12. The output signal exists in an analog form A _ADC and / or a digital form D _ADC . Neglecting deviations between the two forms, for example by quantization errors, both signals are referred to as output and are equal in terms of their information content.

The delta-sigma modulator 100 includes a first digital-to-analog converter (DAC) 104 coupled to an integrator input 14. The first DAC 104 is configured to provide a current I _DA c based on a first digital signal D _DAC . In other words, the current I DAC is an analogue or analogized form of the digital signal D _DA c-

The delta-sigma modulator 100 further includes a second DAC 106 coupled to the integrator output 112. The second DAC 106 may be described as a support DAC and is configured to provide a current I _S UPPPORT DAC based on a second digital signal D _S UPPO T_DAC. take. In other words, the stream ISUPPORT_DAC is an analogue or analogized form of the digital signal DSUPPORT_DAC-

The first digital signal D _DA c is a return-to-zero-RZ signal or a signal returning to zero, that is to say it describes pulses, the signal returning to a zero value between the pulses. The second digital signal D _SUPPO PRT_DAC describes a superposition of pulses and a variable offset. The Offs et follows the input signal l | _N. The delta sigma modulator 100 further includes a control circuit 108. The control circuit 108 is coupled to the ADC 102 and configured to receive the digital form D _A DC of the output signal and based on the digital form D _A DC of the output signal, the first digital Signal D _D AC and the second digital signal D _SUP PORT_DAC ZU generate.

The control circuit 108 may be, for example, a hardware circuit. Alternatively, the control circuit 108 may be implemented at least partially in software, for example in the form of a microcontroller which receives the output signal D _A DC in digital form at one input and the first digital signal D _DA c and the second digital signal D at one or more outputs _SU PPORT_DAC provides. Alternatively, the control circuit 108 may be an integrated circuit, a Field Programmable Gate Array (FPGA). The integrator circuit comprises an amplifier circuit 1 16 and an integrator 1 18. The amplifier circuit 16 may be, for example, one or more operational amplifiers, one or more transistors or the like or a combination thereof. The integrator 1 18 may be, for example, a capacitor or a capacitive circuit. The integrator 1 18 is coupled between an input and an output of the amplifier circuit 16 1. If the input signal I _{! N is applied,} for example, to an inverting input of the amplifier circuit 16, if the amplifier circuit 16 is an operational amplifier, then the integration element 118 is also connected to the inverting input of the amplifier circuit 16. The inverting amplifier input has a negligible current consumption. The integrator circuit 110 may be implemented as an integrator which integrates the current based on the difference I _{! N} -I _D AC. The amplifier circuit tion 1 16 is formed on the basis of the circuit to provide or receive the amplifier current I AMPLIFIER, with which the integrator circuit 1 18 is applied, as far as this current, for example expressed by I ERSTÄRKER = IDAC - IIN + ISUPPORT_DAC not from the second DAC or the current ISUPPORT_DAC is balanced.

The control circuit 108 is designed to provide the first digital signal D _DA c such that the resulting current I _DA c the input current I | _N at least partially compensate and to keep an output voltage of the amplifier small. This can lead to a reduced amplifier current IVERST _Ä RKER.

The control circuit 108 is configured to provide the second digital signal D _SU PPORT_DAC SO such that the output current IVERSTÄRKER is reduced or minimized. A current or a charge quantity which is provided by the second DAC 106 per bit of the digital signal D _S UPPORT_DAC can be determined, for example, by the manufacturer or in the course of a calibration routine, so that this value is provided to or stored in the control circuit 108 can, for example, when the control circuit has a memory. Depending on which charge quantities the control circuit 108 determines as being provided at the output of the integrator circuit 110 in the form of the current ISUPPORT_DAC, the control circuit 108 is designed to generate a corresponding bit sequence of the second digital signal D _S UPPORT_DAC ZU.

A schematic profile of the amplifier current IVERST _Ä RKER is shown in FIG. 2c.

The first digital signal D _DA c is an RZ signal. This can be formulated such that a pulse or a duration of a (theoretical) DAC RZ pulse is reduced by means of a factor a, the factor a being in a range of greater than zero or 0% and less than 1 or 100%. is arbitrary. For an RZ pulse that returns to zero after half the pulse duration, this means that the factor a equals 0.5 or 50%.

A back current to be coupled, which permits a compensation of the current amplifier IVER ST _¬ _Ä AMPLIFIER, may, for example from the control circuit 108th by the provision

IDÄC_NRZ * TRER | ODE ⁼ 'DÄC_RZ ^* a ^* Tp _ER | ₀ DE (2) where T _{P ER} I ₀ DE describes a period of the corresponding signal clock or bit. Formed results

This means that the current I DAC_RZ is increased by means of the factor 1 / a with respect to a current! DAC_NRZ which would be required when the first DAC 104 NRZ pulses were received. The control circuit 108 is configured to drive the DAC 104 with the first digital signal DDAC, which is an RZ signal. The RZ signal has a phase 1 in which the first digital signal D _D AC may have a nonzero value, that is, the DAC is active. The control circuit 108 is further configured to provide the second digital signal DSUPPORT_DAC such that the relationship

ISUPPORT_DAC ⁼ -IDAC_RZ ⁺ IDAC_NRZ (4) is essentially met. For example, the relationship may be said to be substantially satisfied when the actual result, that is, the ISUPPORT_DAC current, has a deviation of less than 5%, less than 10% or less than 50% from the result of formula (4) ,

The second digital signal D _S UPPORT_DAC also has a phase 2 in which the first digital signal D _D AC has returned to zero, that is, the first DAC 104 is off or inactive. The control circuit 108 is configured to provide the second digital signal D _S UPPORT_DAC SO such that for phase 2 a relationship

IsUPPORT_DAC ⁼ I DAC. RZ ⁼ 3 1DAC_RZ (5) is substantially satisfied ". The relationship may, for example, as substantially fulfilled be referred to when the actual outcome, i.e., the current iSUPPORT DAC a deviation of less than 5%, less than 10% or less than 50% to the result of the formula (5). Alternatively or additionally, the current ISUPPORT_DAC can also be understood as a combination of the inverted RZ feedback current and an estimate of the input signal. That is, the above equation (4) ISUPPORT_DAC ⁼ -IDAC_RZ ⁺ IDAC_NRZ (4)

For phase 1 as lsUPPORT_DAC ⁼ "IDAC_RZ ⁺ '| N_ABGESCHZZT (6) can be represented.

In the simplest case, for example in the case of a multi-bit delta-sigma modulator, in phase 1, l | N_ABGESCHÄTZT ⁼ I DAC_NRZ can apply. The delta-sigma modulator can be used, for example, as a multi-bit delta-sigma modulator.

In other words, the second DAC 106 may be described as a support digital-to-analog converter for delta-sigma analog-to-digital converters with return-to-zero feedback. The second digital signal D _S UPPORT_DAC describes a drive of the second DAC 106 to support an amplifier. The drive is designed so that the speed and output current of an amplifier can be reduced. Thus, an energy saving is possible. FIGS. 2a-c show various current profiles over a common time axis for the purpose of illustrating different current signals.

Fig. 2a shows the input signals I _DAC and I _{iN of} the integrator circuit I 10 in FIG. 1 over a time t which has five periods, that is to say pulse intervals, Pi-P ₅ . The periods P, - P ₅ are each a clock cycle of the first digital signal and thus the current waveform l _DAC . The amplitude of the current I _DA c decreases as an example with decreasing amplitude of the input signal. Signal l _iN , which means that the first digital signal or an amplitude of the first digital signal follows the input signal. I _IN can be, for example, a sensor signal of a sensor. Based on a measured value of the sensor, l _IN can assume any values. The second digital signal and therefore the current profile ISUPPORT_DAC is isochronous with respect to the first digital signal. Each of the periods has a phase 1 (Ph1) and a phase 2 (Ph2), wherein the respective first phase is characterized in that the first DAC is active, that is, may have a non-zero signal amplitude with a corresponding input signal I _{! N} , In Phase 2, the first DAC is inactive, so the IDAC signal returns to the zero value. The current I, _N has a continuous course, which changes only slowly compared to the current I _D AC.

FIG. 2b shows a profile of an amplifier current I * AMPLIFIER of a system which has only the first DAC but no second DAC and can be described as a delta-sigma modulator without a support DAC. Such a system is exemplified in FIG. Amplifier current I * AMPLIFIER can be calculated according to formula 1. The amplifier current AMPLIFIER has a maximum value _max and a peak-to-peak (pp) value l * _pp . A maximum peak-to-peak value of the amplifier current may be a design basis for a maximum amount of current to be provided by the amplifier.

Fig. 2c shows a profile of the current I SUPPORT_DAC of the second DAC 106 of Fig. 1 and a resulting amplifier current IVERSTÄRKER- The current ISUPPORT_DAC can be calculated for the phase 1 and phase 2 according to the formulas (4) and (5). Offsets Oi, 0 ₂ and 0 ₅ on the ordinate have the respective first and second periods P, and P ₂ the respective variable offset for each period. The offset values OL 0 ₂ and 0 ₅ can be calculated according to formula (5). In one over time falling amplitude of the input signal I _IN, the offset values can Oj - 0 ₅ have decreasing values. In other words, the variable offset of the second digital signal can follow the input signal I _IN , since I _D AC_NRZ or I DAC_RZ also follow the input signal.

In other words, the digital signal D _A DC may be, for example, an estimate of the input signal I _{! N.} Thus, the variable offset may correspond to an estimate of the input current or signal. Alternatively or additionally, the variable offset may also correspond to an estimate of the output signal _{ADC of} the analog-to-digital converter. A corresponding control circuit, such as the control circuit 108, may be configured to generate the second digital signal, based on which the current I SUPPORT_DAC is provided, such that the variable offset is varied at times when the first digital signal compares l _DAC in Fig. 2a, the zero value leaves. The control circuit can also be designed to leave the offset unchanged, that is to say constant, during a period P 1 -P ₅ . Alternatively, it is also conceivable that the control circuit is designed to vary the variable offset also during the periods Pi - P ₅ , for example in order to reduce or avoid current peaks of the amplifier current. With the exception of the period P ₄ , the signal I _S UPPORT_DAC has a sign change during a period P 1 -P ₅ at times at which the first digital signal or the current I _D AC that is thereby induced or generated returns to the zero value. on.

At the beginning of the period P ₄ , the input signal I _{! N is} approximately zero, compare Fig. 2a. Thereby, the current I _D AC may result in a value of zero over this period, such as when I _D AC is an optionally scaled estimate of the input signal _N and having the value of about zero. Consequently, a compensation of the current I _DA c can be omitted, so that the current ISUPPORT_DAC in period 4 can have values of zero. A maximum amplifier current I _{max of} a delta-sigma modulator, as shown, for example, in FIG. 1, may be less than the maximum amplifier current I * _max . A maximum peak-to-peak value l _pp may be less than the peak-to-peak value l * _pp . That is, adding an independent support DAC can reduce the maximum amplifier current I _max, the amplifier current IVER, and / or the peak-peak current I _pp, respectively. A reduced amplifier current allows faster clock cycles of the signals.

The control circuit is configured to provide the second digital signal such that the current ISUPPORT_DAC through the second digital signal at the amplifier output is approximately in sync with the current through the first digital signal. That is, the first and second digital signals are provided by the control circuit such that any time differences between a path "control circuit, first DAC, amplifier" to the amplifier output and a path "control circuit, second DAC" to the amplifier output are negligible. Negligible means that any jitter, and therefore any power fluctuations or spikes, will not affect system stability. An acceptable upper limit of Jitter between the first digital signal and the second digital signal or the resulting currents may be at the amplifier output, for example, at 1%, 5% or 10% of the period. The second digital signal, compare ISUPPORT_DAC, may be considered as having a variable offset Oi _. 2.5 provided, inverted first digital signal, or resulting current can be called. Thus, the second digital signal may be described as following the first digital signal. FIG. 3a shows a detailed illustration of the current I _D AC from FIG. 2a. The abscissa of the graph is a time axis with the time steps t = 0 to t = 10, wherein each two successive time steps form a period P ^ -P ₅ . This means that the period -ι from T = 0 to 1 = 2 and the period P ₂ from T = 2 to T = 4, etc. lasts. The ordinate of the graph shows normalized current values I. In period P-, I _D AC has a normalized amplitude I _D AC1 with a value of 3. In period P ₂ , I _D AC has a normalized amplitude I _DA c2 with a value of 2. In the period P ₃ , l _DA c has a normalized amplitude I _D AC3 with a value of 1. In period P ₄ , I _D AC has a normalized amplitude I _DAC 4 with a value of zero. In period P ₅ , I _D AC has a normalized amplitude I _DA c5 with a value of 1 and a negative sign.

FIG. 3b shows a more detailed representation of the graph from FIG. 2c with the same abscissa as FIG. 3a. The signal ISUPPORT_DAC has a peak, ie a peak-to-peak value of Δ, between +1, 5 and -1, 5, ie a value of 3, in period P, which is the normalized amplitude in FIG. 3 l _DA c1 corresponds. The offset 0 has a value of 1, 5. This can be obtained, for example, based on a pulse width reduced by the factor a = 0.5 multiplied by the normalized amplitude I _DAC 1 = 3. A signal swing Δ ₂ in period P ₂ has a value of 2, which corresponds to the normalized amplitude I _DAC 2 in FIG. 3a. This means that the variable offset of a period P ₍ -P _{5) can be} half the value of the respective normalized amplitude I _DA c -5 taking into account the sign of the current I _{DAC of} first DACs, for example of the _DAC 1 04, and a signal deviation Δ, - Δ ₅ correspond to the signal swing or the normalized amplitude I _D AC1 -5, so that the second digital signal, or the resulting current can follow the first digital signal or the resulting current.

4 shows a schematic block diagram of a delta-sigma modulator 400 according to another exemplary embodiment of the present invention. The delta sigma ^ Modulator 400 includes integrator circuit 110 which is coupled to analog-to-digital converter 102. The delta-sigma modulator 400 has a digital-to-analog converter 404 which is coupled to the integrator input 1 14. The DAC 404 is configured to provide a current I ' _DA c based on a first digital signal D' _DAC . The delta-sigma modulator 400 further includes a digital-to-analog converter 406 coupled to the integrator output 112. The DAC 406 is configured to _ a current I 'SUPPORT_DAC based on a second digital signal D' _SU p _P0RT provide _DAC. The delta-sigma modulator 400 has a control circuit 408 coupled to the ADC 102. The control circuit 408 is configured to generate the first digital signal D ' _D AC and the second digital signal D'SUPPORT DAC. The control circuit 408 is connected to the DAC 404 and the DAC 406. The control circuit 408 includes a filter circuit 409 connected to the ADC 102. The filter circuit 409 is a digital filter circuit and configured to receive the digital version D ' _{ADC of} the output signal D _A DC ZU and to form an average value of the output signal over a number of time steps, that is, pulse durations or periods. For example, the filter circuit 409 may be configured to form an average over two periods, three periods, five periods, or any other number of periods. Alternatively, the filter circuit 409 may also be implemented as an analog filter circuit and connected to an input side of the ADC 102 or an output side of the integrator circuit 110 so that the filter circuit 409 may be configured to provide an analog version of the output signal A ' _AD c receive and form the average over a number or period of analog values.

This allows formula IIN_ABGESCHÄTZT by means of the filtering of D ' _ADC or A' _ADC, an error of the signal, that is, a deviation between the estimated value and the actual input signal l _{! N} , reduced or accuracy can be increased. This allows the use of the delta-sigma modulator as a single-bit delta-sigma modulator.

The DAC 406 has a higher resolution than the DAC 404. For example, if the filter circuit 409 is configured to average the output signal D'ADC over two periods, then the DAC 406 has at least one bit higher resolution than the DAC 404. A higher resolution of the DAC 406 compared to the DAC 404 allows a representation of intermediate values of the value range of the DAC 404 and thus a generation of current amplitudes of the current 1'supportDAc, which are between the quantization levels of the signal D ' _DA c and the current amplitudes of the current I' DAC.

Alternatively, the filter circuit 409 may also be a stand alone component and disposed between the control circuit 408 and the ADC 102. Then, for example, the control circuit 408 may be the control circuit 108. If the DAC 406 has a higher resolution than the DAC 104, the DAC 404 can also be the DAC 104. If the DAC 404 or the DAC 104 has a lower resolution than the DAC 106, the DAC 406 may also be the DAC 106.

In other words, in formula (6), IIN_AUTHORIZED can be formed by averaging over two or more values of D'ADC. Thereby, a reduction of the maximum current or the peak-to-peak value at the amplifier output by a factor, for example 2, can be made possible.

Fig. 5a shows a waveform of the current I _D AC and the input signal _{N of} FIG. 2a.

Fig. 5b shows a schematic representation of a graph whose ordinate a current strength I and whose abscissa the time axis t according to the figures 2a-c, 3 and 5a be written.

A waveform of the amplifier current Γ ERSTÄRKER schematically shows a possible reduction of a maximum peak-to-peak value _ρρ by using a delta-sigma modulator, such as the delta-sigma modulator 400. For the same signals l _DAC and l _{! N} , a peak Peak value Γ _{ρρ of} the amplifier _{current is} smaller than the peak-to-peak value Ipp in FIG. 2c, for example because the negative values of the current IVERSTÄRKER omitted.

The amplifier current I AMP is also described as an output current based on a delta-sigma modulator with support DAC low pass filters in the input signal estimate.

An advantage of the described embodiments is that the requirements for the output current of the amplifier or the amplifier circuit 1 16 in the case of a multi-bit delta-sigma modulator can be greatly reduced. The advantages of the multi-bit delta-sigma method, ie a lower output current, can also be achieved when using "return-to-zero" pulses, which was only possible with "non-return-to-zero" pulses. With RZ Pulse, higher linearity can be achieved, as the influence of turn-on and turn-off times is less or because a number of signal edges are increased, so that synchronization based on the signal edges is simplified. This means that the current consumption of the amplifier can be reduced and / or input currents can be processed, which could not be processed with previous delta-sigma modulators, since, for example, an output current required based on the input current is too large for the respective amplifier or amplifier circuit would. The exemplary embodiments described can be used, for example, as sigma-delta ADCs for a current measurement or for a charge measurement in the form of the input signal.

FIG. 6 shows a current-time diagram analogous to FIG. 3b, with exemplary current profiles I and Γ, as can be obtained, for example, with the filtering of the output signal D described in FIG. 4, over the periods P-P ₅ . The input signal l | _N and the current of the first DAC I are unchanged from FIG. 3b.

As shown by way of example for the period P ₂ , the variable offsets remain unchanged from the unfiltered digital signals as described in FIG. 1. For example, 0 _{2 has} a normalized amplitude of 1, 0 and is unchanged from 0 ₂ in Fig. 3b. Compared to the representation in Fig. 3b, however, the strokes of the signals, such as Δ _'2 are changed. The change may result from the formation of the average of the signal D or the low-pass filtered signal I. Based on the lower value of the compensation current (for example approx. -0.75 in FIG. 6 compared to -1 in FIG. 3b), the resulting residual error in the form of the amplifier current I can be amplified by the value of the reduction, ie approximately 0, 25, be postponed. Compared with the embodiments in FIG. 3b, this means that a current which has to be provided by the amplifier can be reduced from a value between -0.25 and +0.25 to a value between 0 and 0.25, so that the Demands on the amplifier with respect to the maximum current or peak-to-peak current to be provided can be further reduced. Thus, a smaller size of the amplifier can be achieved. The described sigma-delta modulators or the activation of the support DACs can be used for both multi-bit and single-bit delta-sigma ADCs become. An application with a multi-bit ADC can be much more effective compared to a use in a single-bit ADC. The increased resolution compared to single-bit ADC allows a more accurate estimation of the output signals, thus also allowing a more accurate estimation of the amplifier current. A more accurate estimation allows lower errors or deviations, for example quantization errors, so that with multi-bit ADC a lower amplifier current may be required which can then be further reduced by the illustrated embodiments.

In principle, the method of targeted control of the support DAC can also be used for higher-order ADCs. This can apply to all ADCs with a current input.

7 shows a schematic representation of a graph on whose abscissa the time axis and at whose ordinate current amplitudes are plotted. The course of the input signal l | _N is unchanged from the previous embodiments. The course of the current IDAC_NRZ is an estimate of the input signal l | _N. In about half of each period Pi - P ₅ , the value of IDAC_NRZ equals the value of l | _N. A map ISCHÄTZ describes the average value of two consecutive values of the current IDAC_NRZ-ISCHÄTZ each has an amplitude value between the value of IDAC_NRZ the current period, such as period P ₂ and the previous period, such as period Pi.

Fig. 8 shows a delta-sigma modulator. wherein at the input of an integrator circuit 81 0, which may be, for example, the integrator circuit 1 1 0, a DAC 804, such as the DAC 1 04 or 404, is arranged. The DAC 804 is configured to receive the digital signal D _DA c ZU. The integrator circuit 81 0 is configured to provide the amplifier current I "AMPLIFIER An analog-to-digital converter 802 is configured to provide a digital output signal D ^* _A DC based on the amplifier current I * AMPLIFIER.

Fig. 9 shows a schematic representation of the differences between NRZ and RZ pulses. NRZ pulses have during each period P '- P' ₆ to a respective unchanged amplitude. RZ pulses return to zero after one part of the period ΡΊ-P ' ₆ , before a new amplitude value from the corresponding signal is assumed in the next period. A portion of the period ΡΊ, - P ' ₆ in which the Signal can assume a non-zero value can be described as the factor a.

Fig. 10 is a schematic block diagram of a prior art delta-sigma modulator. A second DAC 1002 is connected to an output of an integrator circuit 1010. A DAC 1004 is connected to an input of the integrator circuit 1010. The DAC 1002 is configured to receive the signal D _D AC inverted by means of an inversion 1006, resulting in an amplifier current f ERST _Ä RKER which approximately corresponds to the inverted input current I _tN , as shown in Fig. 1 1.

FIG. 11 a shows the input signals I _D AC and _N analogously to FIGS. 2 a and 5 a. Fig. 1 1 b shows a time axis t, the curves of the currents f _D AC and a resulting amplifier current I ^"VERSTARKER-

Although some aspects have been described in the context of a device, it will be understood that these aspects also constitute a description of the corresponding method, so that a block or a component of a device is also to be understood as a corresponding method step or as a feature of a method step , Similarly, aspects described in connection with or as a method step also represent a description of a corresponding block or detail or feature of a corresponding device.

Depending on particular implementation requirements, embodiments of the invention may be implemented in hardware or in software. The implementation may be performed using a digital storage medium, such as a floppy disk, a DVD, a Blu-ray Disc, a CD, a ROM, a PROM, an EPROM, an EEPROM or FLASH memory, a hard disk, or other magnetic disk or optical memory are stored on the electronically readable control signals, which can cooperate with a programmable computer system or cooperate such that the respective method is performed. Therefore, the digital storage medium can be computer readable. Thus, some embodiments according to the invention include a data carrier having electronically readable control signals capable of interacting with a programmable computer system such that one of the methods described herein is performed. In general, embodiments of the present invention may be implemented as a computer program product having a program code, wherein the program code is operable to perform one of the methods when the computer program product runs on a computer. The program code can also be stored, for example, on a machine-readable carrier.

Other embodiments include the computer program for performing any of the methods described herein, wherein the computer program is stored on a machine-readable medium.

In other words, an embodiment of the method according to the invention is thus a computer program which has a program code for performing one of the methods described herein when the computer program runs on a computer. A further embodiment of the inventive method is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program is recorded for carrying out one of the methods described herein.

A further exemplary embodiment of the method according to the invention is thus a data stream or a sequence of signals which represents or represents the computer program for performing one of the methods described herein. The data stream or the sequence of signals may be configured, for example, to be transferred via a data communication connection, for example via the Internet.

Another embodiment includes a processing device, such as a computer or a programmable logic device, that is configured or adapted to perform one of the methods described herein. Another embodiment includes a computer on which the computer program is installed to perform one of the methods described herein.

In some embodiments, a programmable logic device (eg, a field programmable gate array, an FPGA) may be used to perform some or all of the functionality of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor to perform any of the methods described herein. Generally, in some embodiments, the methods are performed by a any hardware device performed. This may be a universal hardware such as a computer processor (CPU) or hardware specific to the process, such as an ASIC. The embodiments described above are merely illustrative of the principles of the present invention. It will be understood that modifications and variations of the arrangements and details described herein will be apparent to others of ordinary skill in the art. Therefore, it is intended that the invention be limited only by the scope of the appended claims and not by the specific details presented with the description and explanation of the embodiments herein.

Claims

claims

A delta-sigma modulator (100) for providing an output signal (A _ADC ; A'AOCI DADCI D'ADC) based on an input signal ( _IN ), comprising: an integrator circuit (110) adapted to receive the output signal (A _ADC ; A'ADC; D _A DC; D'ADC) to an integrator output (1 12): a first digital-to-analog converter (104; 404) coupled to an integrator input (1 14) and configured is to provide a current (ID _AC ; I'DAC) based on a first digital signal (D _DA c; D ' _0AC ); a second digital-to-analog converter (106; 406) coupled to the integrator output (1 12) and configured to generate a current (ISUPPORT_DAC; TSUPPORT DAC) based on a second digital signal (D _S UPPORT_DAC; D ' SUPPORT DAC); an analog-to-digital converter (102) coupled to the integrator output (1 1 2) and _adapted to receive the output signal (A _ADC ; A ' _A DC; D _A DC ^' , D ' _adc ) in a digital form Providing form (D _A DC! D'ADC); and a control circuit (108; 408) coupled to the analog-to-digital converter (102) and configured to receive the first digital signal. (D _AAC ; D'DAC) and the second digital signal (D _S UPPORT_DAC; D'SUPPORT DAC) based on the digital output signal (D _A DC; D ' _adc ) TO generate; wherein the first digital signal (D _DAC ; D'D _A C) describes pulses and returns to a zero value between the pulses; and wherein the second digital signal (D _SU PPORT_DAC; D'SUPPORTDAC) describes a superposition of pulses as well as a variable offset following the input signal (I _{! N} ).

A delta-sigma modulator according to claim 1, wherein the integrator circuit (1 10) comprises an amplifier circuit (1 16) and an integrator (1 18) coupled to the amplifier circuit (1 16), the amplifier circuit (1 16) is designed to be an amplifier current {IVERSTAR ER; I 'AMPLIFIER) based on the Input signal (l | _N ) and the current (I _D AC; I 'DAC) of the first digital-to-analog converter (104; 404), wherein the integrator (1 1 8) is designed to amplify the amplifier current (I AMPLIFIER * l 'AMPLIFIER) at least partially from an amplifier output side to an amplifier input side, such that the current (l _SUP PORT DAC; I suppoRT_DAc) of the second digital-to-analog converter (106; 406} amplifies the amplifier current (IVERSTÄRKERI I' AMPLIFIER) at least partially compensated.

A delta-sigma modulator according to claim 1 or 2, wherein the control circuit is adapted to provide the second digital signal such that the current through the second digital signal at the amplifier output is isochronous with the current through the first digital signal and Offset of the second digital signal at a time at which the first digital signal returns to the zero value is varied.

A delta-sigma modulator according to any one of the preceding claims, wherein the control circuit is adapted to provide the second digital signal such that the variable offset (d; O ₂ ; Os) of the second digital signal at a time when the first one digital signal (D _D AC; D'DAC) leaves the zero value, is varied, an amplitude of the second digital signal (D _S UPPORT_DAC; D'SUPPORT DAC) remains constant relative to the period of the first or second digital signal.

A delta-sigma modulator according to any one of the preceding claims, wherein the control circuit (108; 408) is arranged to provide the second digital signal such that the current (I _S UPPORT_DAC; I'SUPPORT_DAC) of the second digital-to-analog converter (106; 406) during a period in which the first digital signal has not returned to the zero value, a result of a calculation instruction uPFORT _{DA C} = -I and during a period in which the first digital signal has returned to the zero value Result of a calculation rule

corresponds; ISUPPORT DAC the current of the second digital-to-analog converter (106; 406),

IDAC RZ the inverted current of the first digital-to-analog converter {104; 404), and

! DAC_NRZ denotes the variable offset (O *; 0 _?; 0 ₅ ).

A delta-sigma modulator according to claim 5, wherein the control circuit is arranged to provide the variable offset (Oi; 0 ₂ ; 0 ₅ ) such that the variable offset (d; O ₂ ; O ") of an estimate of the Input current corresponds.

A delta-sigma modulator according to claim 6, wherein the control circuit is arranged to provide the variable offset (O _t ; 0 ₂ ; 0 ₅ ) such that the estimation of the input signal on the output signal of the analog-to-digital converter (ADC ).

A delta-sigma modulator according to any of claims 5-7, wherein the control circuit (108; 408) is adapted to provide the second digital signal (D _SU PPORT_DAC; D'SUPPORT_DAC) such that the current (ISUPPORT_DAC; I'SUPPORT.DAC) of the second digital-to-analog converter (106; 406) during a time period in which the first digital signal (D _DAC ; D ' _DA c) has returned to the zero value, a result of a calculation rule

corresponds; where a is a measure of the time of a period of the first digital signal (D _D Ac; D'DAC) in which the first digital signal {D _DA c; D'DAC) does not return to the zero value.

A delta-sigma modulator according to any one of claims 5 to 8, wherein the control circuit (108; 408) is adapted to provide the first digital signal (D _DA c; D'DAC) SO such that an amplitude of the first digital signal Signal (D _DAC ; D'DAC) follows the input signal (1 _{! N} ) and in which the control circuit (1 08; 408) is further adapted to receive the second digital signal {D _SU PPORT_DAC; D ' _SÜPP ORT_DAC) to provide an amplitude of the current (ISJPPO T DAC; I' SUPPORT_JAC) of the second digital signal Signal (D _S UPPORT_DAC; D ' _S UPPORT_DAC) follows the current (l _DAC ; I) of the first digital signal (DOAC; D'OAC).

A delta-sigma modulator according to any one of the preceding claims, further comprising a filter circuit (409) coupled to the analog-to-digital converter (102) and arranged to provide an average of the output signal (A _AD c; A ' _A DC; D _ADC ; D'ADC) over a number of time steps, wherein a second resolution of the second digital-to-analog converter (106; 406) is greater than a first resolution of the first digital-to-analog converter (104 404).

1 1. A delta-sigma modulator according to claim 10, wherein the filter circuit (409) is part of the control circuit (408).

12. A delta-sigma modulator (100) for providing a digital output signal (DADC) based on an input signal (I _{! N} ) comprising: an integrator circuit (110) configured to provide an analog output to provide nai (A _A DC; A'ACC) at an integrator output (1 12); a first digital-to-analog converter (104; 404) coupled to an integrator input (114) and configured to generate a current (! _D AC; I'DAC) based on a first digital signal (D _DAC ; D _To provide _DAC ); a second digital-to-analog converter (106; 406) coupled to the integrator output (112) and configured to generate a current (ISUPPORT DAC; I 'SUPPORT_DAC) based on a second digital signal (D _S JPPORT DAC! D'siiPPCRT_DAc); and an analog-to-digital converter (102) coupled to the integrator output (112) and configured to provide the digital output signal (D _ADC ; D ' _A DC); a control circuit (108; 408) coupled to the analog-to-digital converter (102) and configured to receive the first digital signal (D _D AC; D'DAC) and the second digital signal (D _S JPPORT_CAC; D'SUPFORT DAC) based on the digital output signal (D _A DC; D'ADC); wherein the first digital signal (D ₀ AC; D ' _DA C) describes pulses and returns to a null value between the pulses; and wherein the second digital signal {D _SUPPO RT_DAC; D'SUPPORT DAC) describes a superposition of pulses as well as a variable offset following the input signal (1 _jN ).

1 3. A method of providing an output signal (AADC; A'ADC; D _A oci D'ADC) based on an input signal (l | _N ) comprising the steps of:

Providing the output signal (A _A DC; A'ADC; D ADC; D'ADC) at an integrator output (1 12);

Providing a current ( _I0AC ; I 'DAC) based on a first digital signal (DOACI D'DAC);

Providing a stream (ISUPPORT.DAC; I'SUPPORT.DAC) based on a second digital signal (DSUPPORTJWC; D'SUPPOHT_L: AC); and

Providing the output signal (A _A DC; _A _ADC ; D _ADC ; D'ADC) in a digital form

Generating the first digital signal (D _D AC; D'DAC) and the second digital signal (DSUPPO T.DAC; D'SUPPORT DAC) based on the digital output signal (D _A DC;

14. A method of providing a digital output signal (D _ADC ) based on an input signal (I _{, K} ), comprising the steps of:

Providing an analog output signal (A _A DC; A'ADC) at an integrator output (1 1 2);

Providing a current (I _D AC; I ' _ÜÄ C) based on a first digital signal (DDAC, D'DAC) describing pulses and returning to a zero value between the pulses;

Providing a stream (iSUPPORT DA.C; I'SUPPORT_OAC) based on a second digital signal (DSUPPORTJMC; D _'SUP po _RT _ _DAC) comprising a superimposition of pulses and a variable offset which the input signal | follows _(N!) , describes; and Providing the digital output signal (D _ADC ; D'ADC); and

Generating the first digital signal (D _DA c; D'DAC) and the second digital signal (DEPORT DAci D 'SUPFORT DAC) based on the digital output signal (DADCI D'ADC).

A computer program comprising program code for carrying out the method of claim 13 or 14 when the program is run on a computer.