DE102017117112B4 - METHOD AND CIRCUIT ARRANGEMENT FOR REDUCING AN EFFECT OF CLOCK JITTER IN A DELTA-SIGMA MODULATOR - Google Patents

Abstract

Method for reducing the influence of a clock jitter in a delta-sigma modulator (1), a circuit arrangement (13) comprising a delta-sigma modulator (1) and a compensation circuit (2), the compensation circuit (2) having a measuring circuit ( 4) and a coupling circuit (3), wherein the measuring circuit (4) comprises a first switch arrangement (6) and a second switch arrangement (8), a second integrator (7), a first delay device (9) and a sample and hold circuit (10 ) comprising the following steps:- generation of a compensation signal Verr for application to an input signal Vin of the delta-sigma modulator (1) by the coupling circuit (3),- wherein a correction voltage VJitter from the measuring circuit (4) and a feedback signal Vfb from the delta-sigma modulator (1) as an input signal for the coupling circuit (3) and- the correction voltage VJitter is proportional to the clock jitter and is used by the measuring circuit (4) i n is determined as a function of reference voltages,- selection between a first reference signal +Vref,int and a second reference signal -Vref.int by the first switch arrangement (6), the first switch arrangement (6) being controllable with the signal Vmess,- forwarding the selected one reference signal to the second integrator (7),- using the selected reference signal as an input signal for the second integrator (7), whereby an integrator output signal Vint is obtained as the output signal of the second integrator (7),- comparing the integrator output signal Vint with the reference signals + Vref,dif and -Vref,dif,- applying a delay to the signal Vmess by the first delay device (9),- passing the difference of the reference signals through the second switch arrangement (8), the second switch arrangement (8) being connected to the delayed signal Vmess can be controlled, - sampling of the difference signal by the sample and hold circuit (10), whereby the correction rspannungs VJitter is obtained as an output signal of the measuring circuit (4).

Description

The invention relates to a method and a circuit arrangement for reducing the influence of a clock jitter in a delta sigma modulator, a circuit arrangement comprising a delta sigma modulator comprising a compensation circuit comprising a measuring circuit and a coupling circuit.

State of the art:

The phenomenon of jitter is well known in the field of data transmission. This term is preferably used to describe temporal clock jitter in the transmission of digital signals or a slight fluctuation in accuracy in the transmission clock of data signals. In English, this transmission cycle is preferably referred to by the term “clock”, which is why the terms “jitter”, “clock jitter” and “clock jitter” are used synonymously in the context of this invention. Jitter-related interference signals interfere with data transmission, which is why their reduction is desirable.

Methods and circuits are known in the prior art that attempt to reduce the negative effects of clock jitter. For example, digital-to-analog converters are known that are equipped with switched capacitors. However, the disadvantage of these converters is that in this case a higher bandwidth of the amplifier is required. Methods and devices are also known in the prior art, which however have the disadvantage that the integrator of the delta-sigma modulator has to be reset periodically (“reset”), which significantly impairs the handling of the delta-sigma modulator.

Tiew and Chen (2005) disclose a time-discrete method for compensating for the non-ideal DAC pulse shape. The non-ideal DAC pulse shape is particularly a problem when using non-return-to-zero (NRZ) DAC pulse shapes. NRZ is often used in particular when a CT modulator is 6 dB less sensitive to clock jitter with NRZ than with return-to-zero (RZ) pulse shapes (cf. bridge paragraph page 3680/3681). On the other hand, RZ has the advantage that the transient behavior of the DAC is always the same and therefore always compensates for positive and negative pulse sequences, so that a correction of the factor (gain) is sufficient. The compensation is based on the detection of the error signal (error signal) by two additional DACs, which are matched to the feedback DAC.

In DE 10 2005 059 277 A1 a compensation circuit for a sigma-delta analog-to-digital converter is disclosed. This converts an analog input signal into a digital output signal and has a digital/analog converter clocked by a clock signal in a feedback signal path. To compensate for a jitter error in the output signal caused by jitter in the clock signal, there is a detection circuit for detecting the output signal. A modeling circuit generates a modeled error signal. The modeled error signal is used to model the jitter error. A compensated digital output signal is generated by means of a subtractor. However, such a procedure is time-discrete and the corresponding compensation circuit requires a high bandwidth.

It is therefore the object of the present invention to provide a method and a circuit arrangement for reducing the influence of a clock jitter in a delta-sigma modulator which do not have the disadvantages and shortcomings of the prior art and which do not require periodic resetting of the integrator . In addition, the amplifier should be able to be operated with the usual bandwidths and the influence of the jitter on the delta-sigma modulator, in particular on its signal-to-noise ratio, should be significantly reduced.

Description of the invention:

• - Erzeugung eines Kompensationssignal Verr zur Anwendung auf ein Eingangssignal Vin des Delta-Sigma-Modulators durch die Einkoppelschaltung,
• - wobei eine Korrekturspannung VJitter aus der Messschaltung und ein Feedbacksignal Vfb aus dem Delta-Sigma-Modulator als Eingangssignal für die Einkoppelschaltung verwendet werden und
• - die Korrekturspannung VJitter proportional zum Taktjitter ist und durch die Messschaltung in Abhängigkeit von Referenzspannungen ermittelt wird,
• - Auswahl zwischen einem ersten Referenzsignal +Vref,int und einem zweiten Referenzsignal -Vref.int durch erste Schalteranordnung, wobei die erste Schalteranordnung mit dem Signal Vmess ansteuerbar ist,
• - Weiterleitung des ausgewählten Referenzsignals an den zweiten Integrator,
• - Verwendung des ausgewählten Referenzsignal als Eingangssignal für den zweiten Integrator, wodurch ein Integratorausgangssignal Vint als Ausgabesignal des zweiten Integrators erhalten wird,
• - Vergleich des Integratorausgangssignals Vint mit den Referenzsignalen +Vref,dif und -Vref,dif,
• - Anwendung einer Verzögerung auf das Signal Vmess durch die erste Verzögerungsvorrichtung,
• - Weiterleitung der Differenz der Referenzsignale durch die zweite Schalteranordnung, wobei die zweite Schalteranordnung mit dem verzögerten Signal Vmess ansteuerbar ist,
• - Abtasten des Differenzsignals durch die Sample&Hold-Schaltung, wodurch die Korrekturspannung VJitter als Ausgabesignal der Messschaltung erhalten wird.

The object is solved by the features of claim 1 and claim 4. Advantageous refinements of the invention are described in the dependent claims. According to the invention, a method for reducing the influence of a clock jitter in a delta-sigma modulator is provided, with a circuit arrangement comprising a delta-sigma modulator, a compensation circuit comprising a measuring circuit and a coupling circuit, the measuring circuit having a first switch arrangement and a second Having switch arrangement, a second integrator, a first delay device and a sample and hold circuit. The procedure includes the following steps:

• - generation of a compensation signal Verr for application to an input signal Vin of the delta-sigma modulator by the coupling circuit,
• - wherein a correction voltage VJitter from the measuring circuit and a feedback signal Vfb from the delta-sigma modulator are used as input signals for the coupling circuit and
• - the correction voltage VJitter is proportional to the clock jitter and is determined by the measuring circuit as a function of reference voltages,
• - Selection between a first reference signal +Vref,int and a second reference signal -Vref.int by a first switch arrangement, the first switch arrangement being controllable with the signal Vmess,
• - forwarding of the selected reference signal to the second integrator,
• - using the selected reference signal as an input signal for the second integrator, whereby an integrator output signal Vint is obtained as the output signal of the second integrator,
• - Comparison of the integrator output signal Vint with the reference signals +Vref,dif and -Vref,dif,
• - application of a delay to the Vmess signal by the first delay device,
• - forwarding of the difference of the reference signals through the second switch arrangement, wherein the second switch arrangement can be controlled with the delayed signal Vmess,
• - Sampling of the difference signal by the Sample&Hold circuit, whereby the correction voltage VJitter is obtained as the output signal of the measurement circuit.

This advantageously provides a method in which the clock jitter is measured, it being possible for a correction voltage VJitter to be derived on the basis of this measured clock jitter and for a compensation signal Verr to be provided. It was totally surprising that in this way a correction method for reducing the effect of jitter can be provided which does not require a periodic reset of the integrator of the delta-sigma modulator.

Using two references -Vref,int and +Vref,int and switching them with Vmess advantageously allows the second integrator to integrate in both directions. In this case, the integration preferably takes place upwards in the case of positive values and downwards in the case of negative values. The correction of the reference values -Vref,int and +Vref,int causes the integrator to work in a stable range for Vint. It was completely surprising that a method for reducing clock jitter in a delta-sigma modulator can be provided, with which single-bit, multi-bit, NRZ and/or RZ-coded feedback signals Vfb can be processed . It is preferred within the meaning of the invention to use the proposed method and the proposed arrangement in particular in time-continuous delta-sigma modulators. It is most preferred in that sense that rectangular feedback signals are used, preferably in the context of both NRZ and RZ coding.

It is preferred within the meaning of the invention that the delta-sigma modulator is also referred to as “modulator” for short. It is also preferred within the meaning of the invention that the delta-sigma modulator is set up to carry out a delta-sigma modulation, i.e. in particular a conversion of digital into analog data and/or vice versa. The circuit arrangement including a delta-sigma modulator includes a compensation circuit, which in turn includes a measuring circuit and a coupling circuit.

The coupling circuit is preferably set up to generate a compensation signal Verr that can be applied to an input signal Vin of the delta-sigma modulator. The signal Verr is preferably formed from the signal VJitter and the delayed signal Vfb by multiplying the two values, with the signal Vfb preferably being delayed by half a period from the signal Vmess. It is preferred within the meaning of the invention that the delay length corresponds to the length of a measurement and/or integration phase. In this way, the compensation signal Verr preferably includes information about the jitter, namely through the preferential inclusion of the signal VJitter, and the feedback signal Vfb during the measurement.

In terms of the invention, it is particularly preferred that the coupling circuit ensures the correct addition of the compensation signal Verr to the input signal Vin. The input signal Vin preferably represents the input signal that is fed to the delta-sigma modulator. This is preferably a voltage. It is preferred within the meaning of the invention that a reference signal Vref is added to this input signal Vin, this addition preferably depending on a Feedback signal Vfb of the delta-sigma modulator takes place. The feedback signal Vfb is preferably equal to the output signal Vout of the delta-sigma modulator, with NRZ and/or RZ coding being applied to the feedback signal Vfb in a preferred embodiment. In the context of the invention, the term “NRZ” preferably stands for non-return-to-zero coding, and the term RZ stands for return-to-zero. In other words, it is preferred within the meaning of the invention that the proposed method can be used for both RZ and NRZ feedback signals. In particular, 1-bit and/or multi-bit coding is also permitted in the context of the invention.

The feedback signal Vfb is preferably subject to undesired fluctuations caused by jitter, these undesired fluctuations causing errors in the delta-sigma modulator.

A compensation circuit is provided, which comprises a measurement circuit and an injection circuit, the injection circuit generating a compensation signal Verr for application to an input signal Vin of the delta-sigma modulator. In this case, the coupling circuit preferably uses two input signals, namely a correction voltage VJitter from the measuring circuit and a feedback signal Vfb from the delta-sigma modulator. It is provided that the correction voltage VJitter is proportional to the clock jitter and can be determined by the measuring circuit as a function of reference voltages. The mode of operation of the coupling circuit is in 4 and the construction of the measuring circuit in 2 shown. It is preferred within the meaning of the invention to also describe the compensation circuit as consisting of two sub-circuits.

It is preferred within the meaning of the invention that the clock jitter can be converted into the correction voltage VJitter with the measuring circuit, the correction voltage VJitter thus obtained preferably being proportional to the clock jitter. This connection is particularly 3 shown.

1. a) Addition eines Spannungswerts Vref zum Eingangssignal Vin in Abhängigkeit von einem Feedbacksignal Vfb des Delta-Sigma-Modulators durch einen ersten Integrator,
2. b) Verwendung des Feedbacksignals Vfb als Eingangssignal für die Einkoppelschaltung, wodurch ein Kompensationssignal Verr als Ausgabesignal der Einkoppelschaltung erhalten wird,
3. c) Verwendung eines Signals Vmess als Eingangssignal für die Messschaltung,
4. d) Umwandlung des Taktjitters in eine Korrekturspannung VJitter durch die Messschaltung, wobei VJitter als zusätzliches Eingangssignal für die Einkoppelschaltung verwendet wird und VJitter eine Funktion des Taktjitters ist,
5. e) Addition des Kompensationssignal Verr zum Eingangssignal Vin durch die Einkoppelschaltung.

In a preferred embodiment of the invention, the method comprises the further steps, which in particular represent specifics of the method presented so far:

1. a) addition of a voltage value Vref to the input signal Vin depending on a feedback signal Vfb of the delta-sigma modulator by a first integrator,
2. b) using the feedback signal Vfb as an input signal for the coupling circuit, as a result of which a compensation signal Verr is obtained as the output signal of the coupling circuit,
3. c) using a signal Vmess as input signal for the measuring circuit,
4. d) conversion of the clock jitter into a correction voltage VJitter by the measuring circuit, with VJitter being used as an additional input signal for the coupling circuit and VJitter being a function of the clock jitter,
5. e) Addition of the compensation signal Verr to the input signal Vin by the coupling circuit.

It is particularly preferred within the meaning of the invention to add a voltage value Vref to an input signal Vin, this addition preferably being carried out by a first integrator which is preferably a component of the delta-sigma modulator. In addition, it is preferred that the addition takes place as a function of a feedback signal Vfb from the delta-sigma modulator. In a further method step, it is preferred that the feedback signal Vfb is used as an input signal for the coupling circuit, as a result of which a compensation signal Verr is obtained as the output signal of the coupling circuit. According to the invention, it is preferred that the signal Vfb, which is preferably exposed to fluctuations caused by jitter, is used by a switch as a feedback signal of the delta-sigma modulator. It is also preferred that Vfb, preferably together with the correction voltage VJitter, is used as the input signal of the coupling circuit. In addition, it is preferred within the meaning of the invention to use a signal Vmeas as the input signal for the measuring circuit. The clock jitter is preferably converted into a correction voltage VJitter by means of the measuring circuit, VJitter being a function of the clock jitter. In terms of the invention, it can be preferred that VJitter is proportional to the clock jitter. For other applications or encodings, however, it can also be preferred that the dependency of the value VJitter on the clock jitter corresponds to a non-linear function, which is required, for example, for DAC signal curve shapes other than rectangular (RZ, NRZ). In addition, the correction voltage VJitter can be used as an additional input signal for the coupling circuit.

It is preferred within the meaning of the invention that the signal Vmess can be derived from the jittering system clock. As a result, the signal Vmeas received is not constant over time, in particular it is subject to small fluctuations. Within the meaning of the invention, such fluctuations and deviations in the signal Vmeas that cannot be attributed to the jittering system clock are not desirable, since they could impair the measurement results.

It is particularly preferred within the meaning of the invention to provide two reference voltages, which are preferably referred to as the first reference signal +Vref,int and as the second reference signal -Vref,int within the meaning of the invention. It is preferred within the meaning of the invention that the values of the reference voltages can be corrected by adders, this correction preferably taking place in accordance with the signs of the reference voltages +Vref,int and -Vref,int. According to the invention, it is preferred that the measuring circuit comprises a first and a second switch arrangement, the first switch arrangement preferably being set up to make a selection between the first reference signal +Vref,int and the second reference signal -Vref,int. The switch arrangements preferably consist of at least one switch, it being possible for the switch arrangements of the measuring circuit to preferably comprise two or more switches. The first switch arrangement can preferably be controlled with the signal Vmeas. In addition, the first switch arrangement is preferably set up to forward the selected reference signal to a second integrator. This second integrator is preferably part of the measuring circuit and is preferably also referred to as the main integrator within the meaning of the invention.

It is preferably provided that the selected reference signal is used as an input signal for the second integrator, as a result of which an integrator output signal Vint is obtained as the output signal of the second integrator. An example curve of an integrator output signal Vint is in 3 shown, the course of the integrator output voltage Vint being given as a function of the time t, given in multiples of the period clock T0. It is preferred within the meaning of the invention that the period duration T0 corresponds to a nominal period of the system clock clk, the term “nominal” preferably meaning in the context of the invention that no jitter fluctuations occur. The vertical dashed lines preferably identify a period of the system clock or its duration. The respective durations are shown below 3 shown, and nominal clock periods that are shortened or lengthened compared to the nominal clock period occur. Any deviations from the nominal length of a period can preferably be recognized by the fact that the corresponding vertical dashed line does not intersect the time axis at integer numbers, but to the right or left of it. For example, the second clock period is shorter than the nominal clock period, while the fifth clock period is longer than the nominal clock period.

It is preferred within the meaning of the invention that a clock period when using NRZ coding corresponds to the duration between a maximum and a minimum of the plot of Vint as a function of the time t. It is preferred that the nominal integration range of the integrator when using NRZ coding is between +Vref,int/2 and -Vref,int/2, where the values +Vref,int and -Vref,int preferably represent the reference voltages that be used for example as input signals of the measuring circuit. The limits +Vref,int/2 and -Vref,int/2 of the integration range preferably correspond to half the values of these reference voltages. In terms of the invention, it is preferred that the integration limits lie at +/-Vref,int/4 in the case of RZ coding. This is preferably due to the fact that in this preferred embodiment of the invention the system clock clk is used as Vmess and the integration period is halved compared to the values for the NRZ coding.

Due to jitter, these limits may not be reached at the end of an integration phase when using NRZ coding, with an integration phase preferably corresponding to one period of the system clock. This failure to reach the limit values +Verf/2 and -Vref/2 of the integration range occurs, for example, at the end of the second or at the end of the fifth clock period, these clock periods being shortened (the second clock period) or lengthened (the fifth clock period) compared to the nominal clock period ) are. At the end of the second clock period, Vint does not quite reach the -Vref/2 limit, rather the integrator output voltage Vint lags behind the -Vref/2 limit by a value VJitter. At the end of the fifth clock period, the integrator output voltage Vint exceeds the limit +Vref/2, preferably by the value VJitter. The inventors have recognized that the corresponding voltage difference VJitter is a measure of the jitter in this clock period itself. By correcting the reference voltages by the value VJitter, preferably by the measuring circuit of the delta-sigma modulator, it is surprisingly achieved that the integrator, after a phase in which jitter occurs, exceeds the integration limits in the next clock period, i.e. in the next integration range , can reach again, especially when the corresponding clock runs nominally again. When using RZ coding, it is preferred that an integration phase is equal to half the period of the system clock.

It is also preferred that the integrator output signal Vint is compared to the reference signals +Vref,dif and -Vref,dif. In other words, the signal Vint is compared against the signals +Vref,dif and -Vref,dif, this comparison preferably taking into account the signs of the reference voltages. In terms of the invention, it is preferred that the values +/-Vref,dif depend on the coding used or the integration range of Vint. For example, the formulation "+Vref/2" designates half the value of the first reference voltage "+Vref". In terms of the invention, it is particularly preferred that the integration range is dependent on the coding or the signal Vfb. It is preferred that the difference determined in this way is preferably routed via the second switch arrangement to a sample and hold circuit. In this case, the second switch arrangement can preferably be controlled with a delayed signal Vmeas. Within the measuring circuit, the signal Vmess is preferably processed further once without a delay and once with a delay. In this case, the undelayed further processing preferably takes place with a first switch arrangement of the measuring circuit and the delayed further processing of the signal Vmeas by the first delay device.

The sample and hold circuit is preferably set up to sample the difference signal at the edges of Vmeas. In other words, the method includes the further method step that the difference signal is sampled by the sample and hold circuit, as a result of which the correction voltage VJitter is preferably obtained as the output signal of the measuring circuit. It is preferred within the meaning of the invention that the differential signal is also referred to as differential signal Δ. A particular advantage of this procedure is that the delay in Vmess advantageously ensures that a sampling point of the sample and hold circuit is not located at the switching time of the switch arrangements. Advantageously, the output signal VJitter of the sample and hold circuit, i.e. the correction voltage, is proportional to the clock jitter. It can also be used advantageously to correct the reference voltages at the summers.

This advantageously provides a method in which the clock jitter is preferably measured using an integrator, a correction voltage VJitter for application to the main integrator of the delta-sigma modulator being derived on the basis of this measured clock jitter. It was totally surprising that in this way a correction method for reducing the effect of jitter can be provided which does not require a periodic reset of the integrator of the delta-sigma modulator.

• m) Verwendung der Korrekturspannung VJitter aus der Messschaltung und des Feedbacksignals Vfb aus dem Delta-Sigma-Modulator als Eingangssignal für die Einkoppelschaltung,
• n) Anwendung einer Verzögerung von einer halben Periode des Signals Vmess auf das Feedbacksignal Vfb durch die zweite Verzögerungsvorrichtung,
• o) Erzeugung des Kompensationssignal Verr durch die Einkoppelschaltung.

In a further preferred embodiment of the invention, the coupling circuit comprises a second delay device, and the method comprises the further steps:

• m) using the correction voltage VJitter from the measuring circuit and the feedback signal Vfb from the delta-sigma modulator as an input signal for the coupling circuit,
• n) applying a delay of half a period of the signal Vmess to the feedback signal Vfb by the second delay device,
• o) Generation of the compensation signal Verr by the coupling circuit.

It is preferred within the meaning of the invention to use the correction voltage VJitter from the measuring circuit and the feedback signal Vfb from the delta-sigma modulator as input signals for the coupling unit. In order to be able to compensate for the jitter correctly, it is preferred to also process the information about the feedback signal Vfb in addition to the compensation signal Vjitter. However, the measuring circuit does not supply this compensation signal Vjitter until an integration phase later, since it is needed for measuring. It is therefore preferred within the meaning of the invention that the feedback signal Vfb is delayed by half a period of the signal Vmess. This advantageously ensures that the compensation signal Verr is added correctly to the input signal Vin of the delta-sigma modulator. In the context of the invention, the term “correct” preferably designates a temporal correctness of the addition, which is advantageously achieved by delaying the feedback signal Vfb. It is preferred within the meaning of the invention that the delay is effected by the second delay device of the coupling circuit. According to the invention, it is particularly preferred that the compensation signal Verr is formed by multiplying the correction voltage VJitter and the delayed feedback signal Vfb.

In a further aspect of the invention, the invention relates to a circuit arrangement for reducing clock jitter in a delta-sigma modulator, the circuit arrangement comprising a compensation circuit which is set up to generate a compensation signal Verr which is based on an input signal Vin of the delta-sigma -Modulator is applied, wherein the compensation circuit has a measuring circuit for generating a correction voltage VJitter and a coupling circuit for conversion processing of the correction voltage VJitter into the compensation signal Verr and the measuring circuit comprises a first switch arrangement and a second switch arrangement, a second integrator, a first delay device and a sample and hold circuit.

It is preferred within the meaning of the invention that the advantages and technical effects that are described for the method also apply to the circuit arrangement, and vice versa. It is particularly preferred within the meaning of the invention that the circuit can be used in connection with a delta-sigma modulator. It can also be preferred that the delta-sigma modulator is part of the circuit arrangement.

It is provided within the meaning of the invention that the compensation signal Verr is generated by the compensation circuit, in particular the coupling circuit of the compensation circuit. This compensation signal Verr is applied to the input signal Vin of the delta-sigma modulator. It is further provided that the compensation circuit includes a measuring circuit for generating a correction voltage VJitter. Furthermore, the compensation circuit includes a coupling circuit for converting the correction voltage VJitter into the compensation signal Verr. This advantageously achieves a reduction in clock jitter in a delta-sigma modulator.

In a preferred embodiment of the invention, the circuit arrangement includes a first integrator which is set up to add a voltage value Vref to the input signal Vin as a function of a feedback signal Vfb from the delta-sigma modulator. Preferably, the value Vfb of the feedback signal varies due to jitter variations, which introduces errors in the delta-sigma modulator. These jitter fluctuations can preferably be measured using the main integrator, in which case a correction voltage VJitter can then be derived from the measured values. This correction voltage VJitter can preferably be applied to the main integrator, which is preferably part of the measuring circuit. Surprisingly, this means that the integrator does not have to be reset periodically.

It is preferred within the meaning of the invention that the first switch arrangement is set up to make a selection between a first reference signal +Vref,int and a second reference signal -Vref,int. It is particularly preferred within the meaning of the invention that a difference or a difference signal Δ is generated. This is preferably done after the integrator, with the delayed signal preferably being able to be used to control the switches. The second switch arrangement can preferably be used to bring the integrator output signal Vint together with a signal Vmess delayed by the first delay device and forward it to a sample and hold circuit, the sample and hold circuit preferably being set up to sample the difference signal Δ and to generate the correction voltage VJitter .

It is also preferred within the meaning of the invention that the coupling circuit includes a second delay device for delaying the feedback signal Vfb by half a period of the signal Vmess. This advantageously enables the feedback signal Vfb to be taken into account at the correct point in time, since the compensation signal Vjitter is only provided by the measuring circuit one integration phase late. The delayed signal Vfb is preferably used to multiply it with the compensation signal Vjitter, which advantageously achieves that the compensation signal Verr is added to the input signal Vin of the delta-sigma modulator at the right time. It is particularly preferred within the meaning of the invention that the circuit arrangement is set up to carry out the method for reducing clock jitter in a delta-sigma modulator.

• 1 Darstellung einer bevorzugten Ausführungsform eines Delta-Sigma-Modulators mit einem ersten Integrator und einer Kompensationsschaltung
• 2 Darstellung einer bevorzugten Ausführungsform der Messschaltung
• 3 beispielhafter Verlauf der Integrationsspannung Vint in Abhängigkeit von der Zeit t in T0
• 4 Darstellung einer bevorzugten Ausführungsform der Einkoppelschaltung
• 5 Darstellung eines Delta-Sigma-Modulators dritter Ordnung

The invention is described in more detail by means of the figure below; it shows:

• 1 Representation of a preferred embodiment of a delta-sigma modulator with a first integrator and a compensation circuit
• 2 Representation of a preferred embodiment of the measuring circuit
• 3 Example of integration voltage Vint as a function of time t in T0
• 4 Representation of a preferred embodiment of the coupling circuit
• 5 Representation of a third-order delta-sigma modulator

1 time the representation of a preferred embodiment of a delta-sigma modulator (1) with a first integrator (5) and a compensation circuit (2), wherein the entire switch arrangement comprising the delta-sigma modulator (1) and the compensation circuit (2) is preferably referred to as a circuit arrangement (13). It is preferred within the meaning of the invention that the 1 shown integrator from the first integrator 5 is equivalent to.

In the upper area of the 1 the first integrator (5) and the delta-sigma modulator (1) are shown in the lower part of 1 the compensation circuit (2) comprising the measuring circuit (4) and the coupling circuit (3). The input signal of the delta-sigma modulator (1) is preferably referred to as Vin for the purposes of the invention. A reference signal +Vref or −Vref, preferably a reference voltage, is preferably added to this input signal Vin, with this addition taking place as a function of a feedback signal Vfb, which can be coupled in by means of a switch. It is preferred that the switch is designed as a triple switch that can switch between the values +Vref, -Vref and/or ground (U=0 V). It is preferred within the meaning of the invention that the signal Vfb, which preferably also represents a voltage, is present with interference from a jitter fluctuation. This jitter fluctuation can preferably be measured with the first integrator (5), which is preferably part of the delta-sigma modulator (1) or the circuit arrangement (13).

According to the invention, it is preferred that the feedback signal Vfb is used together with a correction voltage VJitter as the input signal of the coupling circuit (3), which together with the measuring circuit (4) forms the compensation circuit (2). A signal Vmess is preferably used as the input signal of the measuring circuit (4).

According to the invention, it is preferable for the correction voltage VJitter to be converted into the compensation value Verr in the coupling circuit (3). The signal Verr is preferably formed from the signal VJitter and the delayed signal Vfb by multiplying the two values, with the signal Vfb preferably being delayed by half a period of the signal Vmess. According to the invention, it is preferred that the compensation voltage Verr is fed back into the delta-sigma modulator (1) as an output value, so that the voltage references can be corrected.

2 shows a representation of a preferred embodiment of the measuring circuit (4). In particular, a first switch arrangement (6) and a second switch arrangement (8), a second integrator (7), a first delay device (9) and a sample and hold circuit (10) are shown. The first switch arrangement (6) is set up to make a selection between a first reference signal +Vref,int and a second reference signal -Vref,int, as a result of which a difference signal Δ is generated. This differential signal Δ is forwarded to the second integrator (7), which is preferably set up to generate an integrator output signal Vint. The second integrator (7) is followed by a second switch arrangement (8), which can preferably be used to forward the integrator output signal Vint to a sample and hold circuit (10), the sample and hold circuit (10) being set up to calculate the correction voltage VJitter to create. It is also preferred that the integrator output signal Vint is compared to the reference signals +Vref,dif and -Vref,dif. In other words, the signal Vint is compared against the signals +Vref,dif and -Vref.dif, this comparison preferably taking into account the signs of the reference voltages.

d.h. bevorzugt mit anderen Worten, dass die Periodendauer Tmess bevorzugt dem Zweifachen der Impulsbreite des Feedback-Signals Vfb entspricht.It is within the meaning of the invention that the signal Vmeas is a square-wave signal that preferably has a period Tmeas. Preferably, the Vmess and Vfb signals have the same jitter. It is preferred within the meaning of the invention that the period duration Tmeas is equal to twice the pulse width of the feedback signal Vfb. In NRZ coding, the pulse width of Vfb preferably corresponds to one period of the system clock, the level preferably being held for the entire period. In this preferred embodiment of the invention, the signal Vmess can have twice the period of the system clock, which preferably corresponds to half the frequency clk/2. With RZ coding, it is preferred that the level is held for half the period of the system clock. As a result, the signal Vmess can preferably correspond to the system clock clk. It is preferred within the meaning of the invention that the following relationship applies: $$\text{Tmess}=2\cdot \text{pulse width of Vfb}\text{,}$$

ie, in other words, the period duration Tmess preferably corresponds to twice the pulse width of the feedback signal Vfb.

It can be preferred within the meaning of the invention that a multi-bit signal is used as the feedback signal Vfb, in which several bits can be used, for example values between -4 and +4. In this In this case, it is preferred that Vref,int corresponds to the smallest voltage reference in the delta-sigma modulator (1), which is formed, for example, by the voltage reference for a least significant bit (LSB), where the following should preferably apply: $$\text{Vref}\text{,int}=\text{Vref}\left(\text{LSB}\right)\text{.}$$

It is preferred within the meaning of the invention that Vref,dif can be derived from Vref,int, with Vref,dif preferably depending on the pulse width of the feedback signal Vfb, which preferably determines the integration time, the integration limits or integration ranges. It is also preferred that the integration range of the integrator is symmetrical about zero, so that preferably: $$\text{Vref}\text{,different}=0.5\cdot \text{Vref}\text{,int}\cdot \text{pulse width of}\text{Vfb}/\text{Period of the system clock}$$

3 shows an exemplary course of the integration voltage Vint as a function of the time t in T0. This example profile of the integrator output Vint applies in particular to NRZ coding. It is preferred within the meaning of the invention that with RZ coding the integration ranges, integration limits and the integration period are halved compared to the values for the NRZ coding, the measurement principle preferably remaining unchanged. The period duration T0 preferably corresponds to a nominal period of the system clock clk. The vertical dashed lines preferably indicate the end and beginning of a period of the system clock. The respective durations of the clock periods are in a lower part of the 3 shown, where nominal clock periods that are shortened or lengthened compared to the nominal clock period can occur. If all clock periods were nominal clock periods, the vertical dashed lines would always intersect the horizontal time axis t at the integers 1,2,3,4,5,6. This is in 3 illustrated example is not the case, in particular at the end of the second clock period, which is shortened, for example, compared to the nominal clock period. The dashed lines running vertically also run in particular through the minima and maxima of the integration voltage curve Vint, with these extremes of the curve preferably defining the lengths of the clock periods. At the ends of the shortened clock period 2 and the longer clock period 5, the value of the integration voltage Vint does not reach the limit value +Vref/2 or -Vref/2. Instead, the integration voltage Vint lags behind or overshoots these values. The difference between the limit value and the actual integration voltage value Vint is preferably VJitter.

If the limit values +Verf/2 or -Vref/2 are not reached at the end of an integration phase due to jitter, the reference voltages can be corrected by the value VJitter, preferably by the measuring circuit (4) of the delta-sigma modulator (1st ), which surprisingly allows the integrator to reach the integration limits again in the next clock period, i.e. in the next integration range, after a phase in which jitter occurs, especially under the condition that the corresponding clock runs nominally again.

4 shows a representation of a preferred embodiment of the coupling circuit (3). In particular, the second delay device (11) is shown, with which the feedback signal Vfb can be delayed by preferably half a period of the signal Vmess, so that the compensation signal Verr can be added together with the input signal Vin of the delta-sigma modulator (1) at the correct time can. A multiplier (12), which is preferably also a component of the coupling circuit (3), can be controlled with the time-delayed signal Vfb. Delaying the feedback signal Vfb by preferably half a period of the signal Vmess is necessary because the measuring circuit (4) outputs the compensation signal Vjitter also shifted by the duration of half a period of Vmess because it is required for measurement. It is preferred within the meaning of the invention that the duration of half a period of Vmeas corresponds to an integration phase. The correction voltage VJitter from the measuring circuit (4) and the feedback signal Vfb from the delta-sigma modulator (1) are preferably used as the input signal for the coupling circuit (3), the signal Verr preferably being composed of the signal VJitter and the delayed signal Vfb Multiplication of the two values is formed. It is preferred that the signal Vfb is preferably delayed by half a period of the signal Vmess.

The compensation voltage Verr, which can preferably be added to the input voltage Vin of the delta-sigma modulator (1), is preferably obtained as the output signal of the coupling circuit (3) and the compensation circuit (2).

The use of a multiplier (12) is particularly advantageous because it also allows multi-bit feedback signals to be processed with the coupling circuit (3). The compensation signal is therefore preferably obtained from the relationship: $$\text{lock}=\text{Vjitter}\cdot \text{Vfb}\left(\text{delay}\right)\text{.}$$

5 Figure 12 shows a representation of a third-order delta-sigma modulator. This preferably includes three downstream integrators and a preferably clocked comparator. Specifically clarified 5 that the proposed invention can be used in connection with delta-sigma modulators and how the feedback signal Vfb is preferably obtained. Vin is preferably used as the input signal for the third-order delta-sigma modulator, and the output signal is preferably referred to as Vdsm for the purposes of the invention. Shown in 5 is also the signal Vfb, which is preferably used for the feedback, in particular the feedback. According to the invention, it is preferred that the signal Vfb is equal to the output signal of the delta-sigma modulator. The transfer function of the delta-sigma modulator can preferably be adjusted with the coefficients a1, a2 and a3.

reference list

1

Delta Sigma Modulator

2

compensation circuit

3

coupling circuit

4

measuring circuit

5

first integrator

6

first switch arrangement

7

second integrator, main integrator

8th

second switch arrangement

9

first delay device

10

Sample&Hold circuit

11

second delay device

12

multiplier

13

circuit arrangement

BIBLIOGRAPHY

Tiew, Kei-Tee, and Yuan Chen. "DAC compensation for continuous-time delta-sigma modulators." 2005 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2005.

Claims (8)

Method for reducing the influence of a clock jitter in a delta-sigma modulator (1), a circuit arrangement (13) comprising a delta-sigma modulator (1) and a compensation circuit (2), the compensation circuit (2) having a measuring circuit ( 4) and a coupling circuit (3), wherein the measuring circuit (4) comprises a first switch arrangement (6) and a second switch arrangement (8), a second integrator (7), a first delay device (9) and a sample and hold circuit (10 ) comprising the following steps: - generation of a compensation signal Verr for application to an input signal Vin of the delta-sigma modulator (1) by the coupling circuit (3), - wherein a correction voltage VJitter from the measuring circuit (4) and a feedback signal Vfb from the delta-sigma modulator (1) can be used as an input signal for the coupling circuit (3) and - the correction voltage VJitter is proportional to the clock jitter and can be measured by the measuring circuit (4 ) is determined as a function of reference voltages, - selection between a first reference signal +Vref,int and a second reference signal -Vref.int by a first switch arrangement (6), the first switch arrangement (6) being driven with the signal Vmess bar, - forwarding the selected reference signal to the second integrator (7), - using the selected reference signal as an input signal for the second integrator (7), whereby an integrator output signal Vint is obtained as the output signal of the second integrator (7), - comparison of the integrator output signal Vint with the reference signals +Vref,dif and -Vref,dif, - applying a delay to the signal Vmess by the first delay device (9), - forwarding the difference of the reference signals through the second switch arrangement (8), the second switch arrangement (8) can be controlled with the delayed signal Vmess, - sampling of the differential signal by the sample and hold circuit (10), whereby the correction voltage VJitter is obtained as the output signal of the measuring circuit (4). procedure after claim 1 characterized by the further steps - addition of a voltage value Vref to the input signal Vin as a function of a feedback signal Vfb of the delta-sigma modulator (1) by a first integrator (5), - use of the feedback signal Vfb as an input signal for the coupling circuit (3), whereby a compensation signal Verr is obtained as the output signal of the coupling circuit (3), - use of a signal Vmess as input signal for the measuring circuit (4), - conversion of the clock jitter into a correction voltage VJitter, by the measuring circuit (4), with VJitter as an additional input signal for the coupling circuit (3) is used and VJitter is a function of the clock jitter, - the compensation signal Verr is added to the input signal Vin by the coupling circuit (3). Method according to one or more of the preceding claims, wherein the coupling circuit (3) comprises a second delay device (11), comprising the further steps: - Use of the correction voltage VJitter from the measuring circuit (4) and the feedback signal Vfb from the delta-sigma modulator (1) as an input signal for the coupling circuit (3), - applying a delay of half a period of the signal Vmess to the feedback signal Vfb by the second delay device (11), - Generation of the compensation signal Verr by the coupling circuit (3). Circuit arrangement (13) for reducing clock jitter in a delta-sigma modulator (1), characterized in that the circuit arrangement (13) comprises a compensation circuit (2) which is set up to generate a compensation signal Verr, which is based on an input signal Vin of the delta-sigma modulator (1), the compensation circuit (2) comprising a measuring circuit (4) for generating a correction voltage VJitter and a coupling circuit (3) for converting the correction voltage VJitter into the compensation signal Verr and the measuring circuit (4) a first switch arrangement (6) and a second switch arrangement (8), a second integrator (7), a first delay device (9) and a sample and hold circuit (10). Circuit arrangement (13) after claim 4 characterized in that the circuit arrangement (13) comprises a first integrator (5) which is set up to add a voltage value Vref to the input signal Vin as a function of a feedback signal Vfb from the delta-sigma modulator (1). Circuit arrangement (13) after claim 4 characterized in that the first switch arrangement (6) is set up to make a selection between a first reference signal +Vref,int and a second reference signal -Vref,int. Circuit arrangement (13) according to one or more of the preceding Claims 4 until 6 characterized in that the coupling circuit (3) comprises a second delay device (11) for delaying the feedback signal Vfb by half a period of the signal Vmess. Circuit arrangement (13) according to one or more of the preceding Claims 4 until 7 characterized in that the circuit arrangement (13) is set up to the method according to one or more of Claims 1 until 3 to perform.

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