EP2926374A1

EP2926374A1 - Display screen having organic light-emitting diodes

Info

Publication number: EP2926374A1
Application number: EP13820795.6A
Authority: EP
Inventors: Umberto Rossini; Henri Doyeux; Bernard Aventurier; Eva SERRES
Original assignee: Commissariat a lEnergie Atomique CEA; Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Current assignee: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date: 2012-11-30
Filing date: 2013-11-28
Publication date: 2015-10-07
Also published as: US20150270325A1; CA2892450A1; FR2999018B1; US9548345B2; FR2999018A1; WO2014083285A1

Abstract

The invention relates to a matrix display screen which includes, in sequence: a mounting (50); at least one first metal portion (156); a stack of layers (52, 72, 86, 104) including transistors (TFT1, TFT2); and organic light-emitting diodes (32).

Description

ORGANIC ELECTROLUMINESCENT DIODE DISPLAY SCREEN

Field

The present disclosure relates to a display screen organic light-emitting diodes, including a display screen for a head-up display.

Presentation of the prior art

The head-up displays, also called head-up displays, head-up displays or head-up display systems, also known as the HUD, of the English Head-Up Display, are augmented reality display systems that allow integrate visual information on a real scene seen by an observer. In practice, such systems can be placed in the visor of a helmet, in the cockpit of an aircraft or within the cabin of a vehicle. They are thus positioned at a small distance from the eyes of the user, for example a few centimeters or tens of centimeters.

The visual information is provided by a display screen. Conventionally, it is a cathode ray tube screen. The current trend is to replace CRTs with head-up displays by less bulky matrix display screens. It would be desirable to be able to use matrix diode screens organic luminescent devices which include display pixels arranged in rows and columns.

However, in a head-up display, the display screen must be able to provide a luminance of at least 70000 candelas per square meter. This may correspond to the provision of too high intensity currents incompatible with the proper functioning of display screens électrolumines diodes ^¬ conventional organic Centes.

summary

Thus, an embodiment provides a matrix display screen comprising successively:

a support ;

at least a first metal portion;

a stack of layers including transistors; and organic electroluminescent diodes.

According to one embodiment, the first metal portion is connected to at least one of the transistors.

According to one embodiment, the first metal portion extends vis-à-vis several display pixels.

According to one embodiment, the first metal portion extends vis-à-vis all the display pixels.

According to one embodiment, each display pixel comprises at least one of said transistors, the first metal portion being connected to said transistor for each display pixel.

According to one embodiment, the metal portion is full.

According to one embodiment, the metal portion comprises through openings.

According to one embodiment, the screen further comprises an electrode connected to the cathode of each light emitting diode, and at least a second metal portion, at the same level as the first metal portion, connected to the electrode. According to one embodiment, the second metal portion extends along an edge of the first metal portion.

According to one embodiment, the screen comprises a plurality of second metal portions, each second metal portion extending along an edge of the first metal portion and being connected to the electrode.

According to one embodiment, the stack comprises third metal portions, the thickness of the third metal portions being strictly less than the thickness of the first metal portion.

According to one embodiment, the transistors comprise thin-film transistors.

An embodiment also provides a head-up viewfinder comprising a display screen as defined above.

An embodiment also provides a method for producing a matrix display screen comprising the following successive steps:

- provide support;

forming on the support at least a first metal portion;

forming, on the first metal portion, a stack of layers including transistors; and

- Form organic light emitting diodes on the stack.

According to one embodiment, the method comprises, after the step of forming the stack and before the step of forming organic light-emitting diodes, the step of depositing a planarization layer on the stack.

According to one embodiment, the transistors are made of polycrystalline silicon deposited at low temperature or LTPS technology.

According to one embodiment, the first metal portion is made by a damascene method. According to one embodiment, the method comprises performing at least one contact recovery between one of the transistors and the first metal portion.

Brief description of the drawings

These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying drawings in which:

Figure 1 shows, in the form of a schematic block, an example of a head-up viewfinder;

FIG. 2 is a partial and diagrammatic representation of the equivalent circuit of an exemplary display pixel of an organic electroluminescent diode matrix screen;

FIG. 3 shows a partial and schematic cross section of the display pixel of FIG. 2 according to an example in which the display pixel is made with thin-film transistors;

FIG. 4 is a cross section, partial and schematic, of an embodiment of a matrix screen with light-emitting diodes;

Figure 5 is a section of Figure 4 along the line V-V;

Figure 6 is a section similar to Figure 3 of a display pixel of the screen of Figure 4;

Figure 7 is a section similar to Figure 5, partial and enlarged, of a variant of the display screen of Figure 4; and

FIGS. 8A to 8D are partial and schematic sections of structures obtained at steps of an embodiment of a method of manufacturing the matrix screen shown in FIG. 4.

For the sake of clarity, the same elements have been designated with the same references to the different figures and, from moreover, as is customary in the representation of circuits, the various figures are not drawn to scale. detailed description

In the rest of the description, unless otherwise indicated, the terms "substantially", "substantially", "about" and "of the order of" mean "to within 10%".

Figure 1 illustrates, schematically, the operation of a head-up viewfinder 5.

A semi-transparent plate 10 is placed between the eye of a user 12 and a scene to be observed 14. The objects of the scene to be observed 14 are generally located at infinity or at a significant distance from the observer 12. The semi-transparent plate 10 is inclined at an angle of 45 ° with respect to an axis connecting the scene 14 and the observer 12. The plate 10 makes it possible to transmit the information coming from the scene 14 to the observer 12, without alter this information.

A projection system 15 is provided to project an image seen by the observer 12 at the same distance as the real image of the scene 14 and superimpose it on it. This system comprises a display screen 16 located at the focal point object of an optical system 18. The display screen 16 is controlled by a display screen control module 20 which determines the images to be displayed by example from signals provided by unrepresented sensors.

The projection system 15 is placed perpendicular to the axis connecting the scene 14 and the observer 12 so that the beam from the optical system 18 reaches the semi-transparent plate 10 perpendicular to this axis. The beam from the optical system 18 thus reaches the semi-transparent plate 10 at an angle of 45 ° with respect to its surface and is reflected towards the observer 12. The image displayed on the screen 16 is collimated to infinity by the optical system 18. The observer 12 does not have to make accommodation effort, which limits the visual fatigue of the latter. The semi-circular blade transparent 10 combines the image of the scene 14 and the image from the projection system 15, whereby the observer 12 displays an image comprising the projected image superimposed on the image of the scene 14.

The display screen 16 is generally a CRT screen. It would be desirable to be able to use a matrix screen instead of a cathode ray tube screen, in particular to reduce the size of the screen. The smallest element of a digital image that can be displayed by the matrix screen 16 is called the image pixel. The smallest element of the screen 16 is called display pixel to display an image. For a color screen, the display of an image pixel may require several display pixels, for example red, green and blue display pixels. The display pixels of a matrix screen are regularly divided into rows and columns. For example, a monochrome display screen 16, used in a head-up display, can typically comprise 300 to 1500 rows and 300 to 1500 columns, for example 640 columns and 480 rows. For example, all the screens adapted to the VGA display standard (English acronym for Video Graphics Array) can be envisaged.

It would be desirable to be able to use an organic light-emitting diode (OLED) matrix display screen as a display screen 16 of a head-up display.

FIG. 2 is a partial and schematic representation of an exemplary display pixel 22 of an OLED matrix screen. Each display pixel 22 comprises an organic light-emitting diode 32, two P-type field-effect transistors TFT ₁ and TFT ₂ , and a capacitor C _S. The cathode of the diode 32 is connected to a cathode electrode V _C which may be common to all the display pixels 22 of the screen. For each row of the screen, a selection line V _SELECTION is connected to the gate of the transistor TFT ₁ of all the pixels display of the row. For each column of the screen, a transmission line of a data signal V _DATA is connected to one of the conduction terminals of the TFT transistor ₁ of each display pixel of the column. The other conduction terminal of the TFT transistor ₁ is connected to an armature of the capacitor C _S and to the gate of the transistor TFT ₂ . For each column of the screen, a supply line V _DD is connected, for each display pixel 22 of the column, to the other armature of the capacitor C _S and to a conduction terminal of the transistor TFT ₂ . other conduction terminal of the TFT transistor ₂ being connected to the anode of the diode 32.

The activation of the display pixel 22 comprises a selection phase and a transmission phase. During the selection phase, the TFT transistor ₁ is on. The capacitor C _S is charged by the potential applied to the line V _DATA which depends on the desired emission light intensity for the diode 32. During the transmission phase, the line V _DD is set to a reference potential. and the cathode electrode V _C is set to a low reference potential. A current flows in the diode 32 whose intensity is controlled by the TFT transistor ₂ and depends on the voltage across the capacitor C _S.

FIG. 3 represents the pixel 22, seen in cross section, in the case where the transistors TFT ₁ and TFT ₂ are thin-film transistors.

Each display pixel 22 comprises successively from bottom to top:

an area 40 serving in particular to support the entire screen;

a zone 42 comprising transistors TFT ₁ and TFT ₂ and conductive lines V _DATA , V _SELECTION and V _DD ;

a zone 44 comprising the diode 32 and the cathode electrode V _C ; and

an area 46 serving in particular as a protective coating. A substrate 50 is conventionally used to produce the zone 40. In the present example, the light radiation emitted by the diodes 32 is intended to be seen from the top in FIG. 3. The substrate 50 may be made of an insulating or conductive material. . Preferably, the substrate 50 is made of a good heat-conducting material, for example a semiconductor material to facilitate the evacuation of the heat produced by the transistors and the diodes, in particular silicon, or a metallic material.

For example, the transistors of the zone 42 are thin-film transistors. The source, drain and channel regions of the transistors are then produced in thin layers of a semiconductor material having a thickness of the order of or less than a hundred nanometers, for example amorphous silicon, microcrystalline silicon, polycrystalline silicon, monocrystalline silicon, cadmium selenide, or zinc oxide. Any type of thin film transistor manufacturing process can be implemented. By way of example, when the semiconductor material is polycrystalline silicon, the process for manufacturing the thin-film transistors may be a low-temperature polycrystalline silicon process or a low-temperature polysilicon (LTPS) process.

More specifically, the zone 42 comprises:

an insulating layer 52, for example made of silicon oxide, covering the substrate 50;

portions 54, 56 of a semiconductor material, especially polycrystalline or amorphous silicon, formed on the layer 52. The portion 54 comprises portions 58, 60 corresponding to the source or drain regions of the transistor

TFT ₁ , a portion 62 corresponding to the channel region of the TFT transistor ₁ , and a portion 64 constituting a lower electrode of the capacitor C _S. The portion 56 comprises portions 66, 68 corresponding to the source or drain regions of the TFT transistor ₂ and a portion 70 corresponding to the channel region of the TFT transistor ₂ ;

a dielectric layer 72, for example made of silicon oxide, covering the portions of the semiconductor material 54, 56 and the layer 52, and acting as gate insulator 74 for the dielectric layer TFT ₁ transistor, for the capacitor C _S and gate insulator 78 for the TFT transistor ₂ ;

metal portions, formed on the dielectric layer 72, in particular a metal portion 80 forming the metal gate of the TFT transistor ₁ , a metal track, not shown, forming the selection line V _SELECTION , a metal portion forming the upper electrode 82 of the capacitor C _S , and a metal portion 84 forming the metal gate of the TFT transistor ₂ ;

a dielectric layer 86, for example made of silicon oxide, covering the dielectric layer 72 and the metal portions 80, 82, 84;

metallic vias, only four vias 88, 90, 92 and 94 being visible in FIG. 3, passing through the dielectric layers 86 and 72 and coming into contact with the source and drain regions 58, 60 of the transistor TFT ₁ , of FIG. upper electrode 82 of the storage capacitor C5, the metal gate 84 of the transistor of the TFT transistor ₂ , the source and drain regions 66 and 68 of the transistor TFT ₂ ;

tracks or metal portions 96, 98, 100 and 110, formed on the dielectric layer 86 in contact with the vias 88, 90, 92, 94, the metal track 102 forming in particular the line V _DD and the metal track 96 forming the line V _DATA ;

an insulating layer 104, also called a smoothing layer or planarization layer, covering the insulating layer 86 and the metal tracks 96, 98, 100 and 102 and used to obtain a planar face 105 on which the light-emitting diode 32 is formed.

For example, the tracks, the vias and the metal portions of zone 42 are made of molybdenum, titanium, tungsten, an alloy of tungsten and molybdenum or aluminum.

By way of example, the zone 42 represented in FIG. 3 is manufactured by the formation of successive layers on the substrate 50. As a variant, the zone 42 is formed on an intermediate support and then is transferred to the substrate 50, the support intermediate being removed.

An opening 106 is formed in the layer 104 and exposes the metal portion 100.

Area 44 includes:

an anode electrode 108 of the light-emitting diode 32 covering the layer 104 and extending into the aperture 106 so that the electrode 108 is electrically connected to the drain region 66 of the TFT transistor ₂ ;

an insulating layer 110 formed on the layer 104 and a portion of the electrode 108;

a light-emitting diode 112 formed on the electrode 108, which may itself comprise a stack of several layers; and

a cathode electrode 114 of the light-emitting diode covering the diode 112 and the insulating layer 110 and extending over the entire display screen. The cathode 114 is made of a conductive material and at least partly transparent, for example a silver layer having a thickness of between 10 and 25 nm.

Area 46 may include:

a color filter 116 covering the cathode 114; and a protective layer 118 covering the color filter 116.

In addition, a metal track covering the insulating layer 86 is provided at the periphery of the matrix screen and is connected to the cathode electrode 114.

The thickness of the metal tracks provided on the insulating layer 86 is, for a conventional electroluminescent diode screen, generally of the order of a few tenths of a micrometer. In a conventional manner, the supply line V _DD has a width of 10 μm for a display pixel having a width of 40 μm and the metal track connected to the cathode electrode 104 has a width of 2 mm.

For an application in a head-up viewfinder, the power supply line V _DD must be able to transmit several milliamperes and the current collected by the cathode electrode can reach several amperes. For a conventional LED array screen, with the dimensions of the metal tracks used to make the power line V _DD , would result in significant voltage drops on the V _DD line, which could affect the smooth operation of the screen , especially because of crosstalk phenomena.

In addition, the metal track connected to the cathode electrode should have a thickness of several micrometers, or even more than 10 microns to have a sufficiently low resistance, which is not possible. Indeed, it is not possible to form an organic light-emitting diode on a too irregular surface induced by the thickness of the underlying metal tracks because the organic layers of the diode are very thin and generally deposited by evaporation. Too irregular a surface can cause discontinuities in deposited organic layers and thus induce short circuits between anode and cathode. It is therefore necessary, if the surface is too irregular, to deposit a smoothing layer, for example polyimide, deposited in particular by spinning, before forming the diodes. But the larger the surface irregularities to be filled, the more this smoothing layer must be thick. Under these conditions, the heat evacuation towards the substrate can be degraded. Furthermore, the contact via the electrode through this smoothing layer must be greater than the layer to be crossed is thick because it is difficult to make a steep brow of small size in a thick material organic. This causes a loss of useful area at the pixel.

It is therefore difficult to use conventional organic electroluminescent diode matrix screen structures for a head-up display application.

Thus, an object of an embodiment is to provide a matrix screen with organic light-emitting diodes at least partially overcoming some of the disadvantages of existing screens.

Another object is that the luminance of the LED array is increased relative to a conventional organic LED array screen.

Another object is that the thickness of the smoothing layer 104 is reduced compared to a conventional LED array screen.

Another object is that the thickness of the metal tracks on the insulating layer 86 is reduced compared to a conventional organic LED array screen.

The present invention consists in producing the supply lines V _DD of the display pixels and / or the metal tracks connected to the cathode electrode by conductive tracks, preferably metal tracks, different from those formed on the insulating layer. 86.

Figures 4 to 6 are sectional views of a display screen 150 according to one embodiment. In Figure 4, the area 46 is not shown.

With respect to the display screen shown in FIG. 3, the display screen 150 according to the present embodiment further comprises an additional zone 152 between the zone 42 in which the transistors TFT ₁ and TFT are formed. ₂ and the substrate 50. The zone 152 comprises an insulating layer 154 and metal portions 155 made on the surface of the insulating layer 154. According to one embodiment, a layer additional may be provided between these metal portions and the insulating layer 154.

By way of example, the metal portions 155 are advantageously made of copper, but they may be of other metals, for example aluminum.

For example, if the metal portions 155 are copper, the underlying additional layer is Ti / TiN or Ta / TaN, conventionally used as copper diffusion barrier.

By way of example, the thickness of the metal portions 155 is from 1 to 10 μm, for example 2 μm, and the thickness of the portion of the insulating layer 154 interposed between the metal portions 155 and the substrate 50 is approximately 100 to 1000 nm. The portion of the insulating layer 154 interposed between the metal portions 155 and the substrate 50 electrically isolates the metal portions 155 from the substrate 50 in the case where the substrate is an electrically conductive material. In the case where the substrate 50 is of a material which is an electrical insulator, the conductive portions 155 may be formed directly on the substrate 50.

The metal portions 155 comprise a metal portion 156 comprising a central zone 157, visible in FIG. 5, extending substantially under the whole of the zone 42 in which the transistors are formed and extending by connection pads 158. As a for example, the central zone 157 has, in the sectional plane of FIG. 5, a square section whose side measures, for example, from 10 mm to 200 mm, for example approximately 70 mm, extending at two opposite corners , by two connection pads 158. Each connection portion 158 is intended, in operation, to be connected to a source of a reference potential. In the present embodiment, the central zone 157 is a continuous metal zone.

The metal portions 155 further include two metal tracks 160, 162 which extend along two contiguous sides of the central zone 157 and meet at a connection pad 164. The metal portions 155 further comprise two metal tracks 166, 168 which extend along the other two contiguous sides of the central zone. 157 and meet at a connection pad 170. For example, each metal track 160, 162, 166, 168 has a length of the order of the dimension of the sides of the screen, or between 10 mm to 200 mm, for example about 70 mm, and a width of 1 mm to 10 mm, for example about 2 mm. As can be seen in FIG. 4, the cathode electrode 114 extends laterally to be connected at its periphery to the metal tracks 160, 162, 166, 168.

The metal portion 156 plays the role of the supply line V _DD described above. As can be seen in FIG. 6, the zone 42 is made analogously to what has been described previously with reference to FIG. 3 except that the feed line V _DD described previously is no longer produced by a track metal formed on the insulating layer 86 and that each display pixel comprises a conductive via 172 passing through the insulating layer 52 to connect the source region 56 of the TFT control transistor ₂ to the metal portion 156, as shown in FIG. 4, or through the insulating layers 52 and 86 to connect the upper electrode of the capacitor C _S to the metal portion 156.

According to one embodiment, in particular when the metal portions 155 are made of copper, the metal portions 155 are produced according to an etching process similar to the damascene etching method used in particular in the manufacture of integrated circuits. According to such a method, the insulating layer 154 is deposited on the substrate 50. Apertures are then made in the insulating layer 154 at the intended locations of the metal portions 155, these openings not extending over the entire thickness of the insulating layer 154. A Ti / TiN or Ta / TaN layer can stage may be deposited on the entire surface. Then a copper layer is deposited on the entire structure obtained and penetrates in particular in the recesses. A chemical mechanical planarization step or CMP (Chemical Mechanical Planarization) is performed to remove the copper layer surface portion until reaching the surface of the insulating layer 154 and delimit the metal portions 155 in the recesses.

According to another embodiment, in the case where the metal portions 155 are in a material that can be etched by a chemical etching, the formation of the portions 155 may comprise the deposition of a metal layer on an insulating layer and the etching of the metal layer to define the metal portions 155. The layer 52 can then be formed on and between the metal portions 155.

The metal tracks of the display screen in which the currents of the highest intensities circulate are made by the metal portions 155 in the present embodiment, and not by metal portions of the zone 42 in which the transistors of the display pixels. The dimensions of the portions 155 are adapted to allow the circulation of such currents. In particular, according to one embodiment, the thickness of the metal portions 96, 98, 100, 102 of the zone 42 is small, less than one micrometer, typically of the order of 0.1 or 0.2 μm, which does not induce a too irregular surface. It is then not necessary to deposit a smoothing layer 104 of too great a thickness which would harm the evacuation of calories through the substrate. This also limits the risk of short circuits at the light emitting diodes. Thus, the thickness of the metal portions 96, 98, 100, 102 of the zone 42 is at least twice, preferably at least 5 times, more preferably at least 10 times, still more preferably at least 20 times, smaller than the thickness of the metal portions 155. We have for example 2 microns thick for the zone 155 and 0.1 microns for the tracks of the zone 42).

Figure 7 shows another embodiment of the metal portion 156 in which the central zone 157 is traversed by openings 174 filled with an insulating material 176 and disjoined from each other. For example, the openings 174 are divided into rows and columns. Advantageously, the embodiment shown in FIG. 7 facilitates the formation of the metal portions 155. Indeed, in the case where a damascene-type etching process is used, it is generally preferable to have a substantially uniform density of metal and insulating portions over the entire surface to be treated in order to reduce the defects of unevenness, and in particular the formation of a dish profile (in English "dishing") during the chemical-mechanical polishing step, related to the difference in polishing rate between the metal and insulating portions.

FIGS. 8A to 8D are sections of structures obtained at steps of an embodiment of a method of manufacturing the display screen 150 shown in FIG. 4 in which the source and drain regions of the TFT transistors ₁ and TFT ₂ are made in a silicon layer, in particular of monocrystalline silicon, which is transferred to a multilayer structure comprising the metal portions 155.

FIG. 8A shows a multilayer structure successively comprising the substrate 50, the insulating layer 154, the metal portions 155 and an insulating layer 180.

In FIG. 8B, there is shown a multilayer structure 182 of the SOI (Silicon On Insulator) type successively comprising a substrate 184, an insulating layer 186, a semiconductor layer 188, for example monocrystalline silicon, and an insulating layer 190 .

FIG. 8C represents the structure obtained after bonding between the insulating layers 180 and 190. Figure 8D shows the structure obtained after removing the substrate 184 and the insulating layer 186, for example by etching.

The following steps of the method include forming the areas 42, 44 and 46 described above. In particular, the source and drain regions of the transistors TFT ₁ and TFT ₂ can be produced in the semiconductor layer 188.

Alternatively, the insulating layer 186 of the multilayer structure 182 may be replaced by a weakened zone of the semiconductor material composing the substrate 184 and the semiconductor layer 188. As a result, after the step of bonding the multilayer structure 182, the multilayer structure 182 is divided into two parts at the weakened zone.

Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, each display pixel may have a structure different from that shown in FIG. 3 and comprise a larger number of transistors.

Claims

1. Matrix display screen (16) comprising successively:

a support (50);

at least a first metal portion (156) and a second metal portion (160, 162, 166, 168), at the same level as the first metal portion (156);

a stack of layers (52, 72, 86, 104) including transistors (TFT ₁ , TFT ₂ );

organic electroluminescent diodes (32); and an electrode (114) connected to the cathode of each light emitting diode (32), the second metal portion (160, 162, 166, 168) being connected to the electrode.

2. Screen according to claim 1, wherein the first metal portion (156) is connected to at least one of the transistors (TFT ₁ , TFT ₂ ).

The screen of claim 1, wherein the first metal portion (156) extends in respect of a plurality of display pixels (22).

The screen of claim 3, wherein the first metal portion (156) extends vis-à-vis all the display pixels (22).

A screen according to claim 4, wherein each display pixel (22) comprises at least one of said transistors (TFT ₁ , TFT ₂ ), the first metal portion (156) being connected to said transistor for each pixel of said display.

6. Screen according to any one of claims 1 to 5, wherein the metal portion (156) is full.

7. Screen according to any one of claims 1 to 5, wherein the metal portion (156) comprises through openings (174).

The screen of claim 1, wherein the second metal portion (160, 162, 166, 168) extends along an edge of the first metal portion (156).

A screen according to claim 1 or 8, including a plurality of second metal portions (160, 162, 166, 168), each second metal portion extending along an edge of the first metal portion (156) and being connected to the electrode (114).

10. Screen according to any one of claims 1 to 9, wherein the stack comprises third metal portions (96, 98, 100, 102), the thickness of the third metal portions being strictly less than the thickness of the first metal portion (156).

11. Screen according to any one of claims 1 to 9, wherein the transistors (TFT ₁ , TFT ₂ ) comprise thin film transistors.

Head-up display (5) comprising a display screen (16) according to any one of claims 1 to

11.

13. A method of producing a matrix display screen (16) comprising the following successive steps:

providing a support (50);

- forming on the support at least a first metal portion (156) and a second metal portion (160, 162, 166, 168) at the same level as the first metal portion (156);

forming, on the first metal portion, a stack of layers (52, 72, 86, 104) including transistors (TFT ₁ , TFT ₂ );

forming organic electroluminescent diodes (32) on the stack; and

an electrode (114) connected to the cathode of each light emitting diode (32), the second metal portion (160, 162, 166, 168) being connected to the electrode.

The method of claim 13 comprising, after the step of forming the stack and before the step of forming the organic light emitting diodes (32), the step of depositing a planarization layer (104) on the stack.

15. The method of claim 13 or 14, wherein the transistors (TFT ₁ , TFT ₂ ) are made of low temperature polycrystalline silicon or LTPS technology.

The method of any one of claims 13 to 15, wherein the first metal portion (156) is made by a damascene method.

17. Method according to any one of claims 13 to 16, comprising performing at least one contact recovery between one of the transistors (TFT ₁ , TFT ₂ ) and the first metal portion (156).

The method of any one of claims 13 to 17, comprising the steps of:

providing a multilayer structure comprising the support (50), the first metal portion (156) and the second metal portion (160, 162, 166, 168);

providing an additional support (182) comprising a layer (188) of a semiconductor material;

stick the additional support on the multilayer structure;

removing a portion of the additional support to expose the layer of the semiconductor material; and

forming the transistors (TFT ₁ , TFT ₂ ) at least partially in the layer of the semiconductor material.