EP2907108A1 - Datenverarbeitungsvorrichtung zur konfiguration einer anzeigeschnittstelle auf basis von kompressionscharakteristiken komprimierter anzeigedaten und entsprechendes datenverarbeitungsverfahren - Google Patents

Datenverarbeitungsvorrichtung zur konfiguration einer anzeigeschnittstelle auf basis von kompressionscharakteristiken komprimierter anzeigedaten und entsprechendes datenverarbeitungsverfahren

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Publication number
EP2907108A1
EP2907108A1 EP13845478.0A EP13845478A EP2907108A1 EP 2907108 A1 EP2907108 A1 EP 2907108A1 EP 13845478 A EP13845478 A EP 13845478A EP 2907108 A1 EP2907108 A1 EP 2907108A1
Authority
EP
European Patent Office
Prior art keywords
data
display
interface
data processing
processing apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP13845478.0A
Other languages
English (en)
French (fr)
Other versions
EP2907108A4 (de
Inventor
Chi-Cheng Ju
Tsu-Ming Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/937,224 external-priority patent/US20140098893A1/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of EP2907108A1 publication Critical patent/EP2907108A1/de
Publication of EP2907108A4 publication Critical patent/EP2907108A4/de
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/005—Adapting incoming signals to the display format of the display terminal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T9/00—Image coding
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/12—Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/136—Incoming video signal characteristics or properties
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/156—Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/164—Feedback from the receiver or from the transmission channel
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/172—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/02—Handling of images in compressed format, e.g. JPEG, MPEG
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2350/00—Solving problems of bandwidth in display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/10—Use of a protocol of communication by packets in interfaces along the display data pipeline

Definitions

  • the disclosed embodiments of the present invention relate to transmitting and receiving display data over a display interface, and more particularly, to a data processing apparatus for configuring a display interface based on a compression characteristic of a compressed display data and related data processing method.
  • a display interface is disposed between a first chip and a second chip to transmit display data from the first chip to the second chip for further processing.
  • the first chip may be a host application processor
  • the second chip may be a driver integrated circuit (IC).
  • the display data may include image data, video data, graphic data, and/or OSD (on-screen display) data.
  • the display data may be single view data for two-dimensional (2D) display or multiple view data for three-dimensional (3D) display.
  • 2D/3D display with higher resolution can be realized.
  • the display data transmitted over the display interface would have a larger data size/data rate, which increases the power consumption of the display interface inevitably.
  • the host application processor and the driver IC are both located at a portable device (e.g., a smartphone) powered by a battery device, the battery life is shortened due to the increased power consumption of the display interface.
  • a portable device e.g., a smartphone
  • the battery life is shortened due to the increased power consumption of the display interface.
  • a data processing apparatus for configuring a display interface based on a compression characteristic of a compressed display data and related data processing method are proposed.
  • an exemplary data processing apparatus includes an output interface and a display controller.
  • the output interface is arranged for packing a compressed display data into an output bitstream and outputting the output bitstream via a display interface.
  • the display controller is arranged for referring to at least a compression characteristic of the compressed display data to configure a transmission setting of the output interface over the display interface.
  • an exemplary data processing apparatus includes an input interface and a controller.
  • the input interface is arranged for receiving an input bitstream via a display interface, and un-packing the input bitstream into a compressed display data that is transmitted over the display interface.
  • the controller is arranged for configuring a reception setting of the input interface over the display interface in response to at least a compression characteristic of the compressed display data.
  • an exemplary data processing method includes following steps: referring to at least a compression characteristic of a compressed display data to configure a transmission setting of an output interface over the display interface; and utilizing an output interface for packing the compressed display data into an output bitstream and outputting the output bitstream via the display interface.
  • an exemplary data processing method includes the following steps: configuring a reception setting of an input interface over a display interface in response to at least a compression characteristic of a compressed display data; and utilizing an input interface for receiving an input bitstream via the display interface, and un-packing the input bitstream into the compressed display data that is transmitted over the display interface.
  • FIG. 1 is a block diagram illustrating a data processing system according to an embodiment of the present invention.
  • FIG. 2 is a flowchart illustrating a first control and data flow of the data processing system shown in FIG. 1.
  • FIG. 3 is a flowchart illustrating a second control and data flow of the data processing system shown in FIG. 1.
  • FIG. 4 is a diagram illustrating the change of the blanking period after the interface compression is applied.
  • FIG. 5 is a flowchart illustrating a third control and data flow of the data processing system shown in FIG. 1.
  • FIG. 6 is a flowchart illustrating a method of setting the application processor by referring to a result of checking a de-compression capability of the driver IC according to an embodiment of the present invention.
  • the present invention proposes applying data compression to a display data and then transmitting a compressed display data over a display interface.
  • the data size/data rate of the compressed display data is smaller than that of the original un-compressed display data, the power consumption of the display interface is reduced correspondingly.
  • the present invention further proposes configuring the display interface based on the compression characteristic of the compressed display data. Further details will be described as below.
  • FIG. 1 is a block diagram illustrating a data processing system according to an embodiment of the present invention.
  • the data processing system 100 includes a plurality of data processing apparatuses such as an application processor 102 and a driver integrated circuit (IC) 104.
  • the application processor 102 and the driver IC 104 may be different chips, and the application processor 102 communicates with the driver IC 104 via a display interface 103 having a plurality of data lines (e.g., DL0, DL1, DL2, and DL3) (for example, differential pair, a pin or group of pins) and one clock line CLK.
  • the display interface 103 may be a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).
  • DSI display serial interface
  • MIPI Mobile Industry Processor Interface
  • eDP embedded display port
  • VESA Video Electronics Standards Association
  • the application processor 102 supports un-compressed data transmission and compressed data transmission.
  • the application processor 102 When the application processor 102 is used to transmit un- compressed data to the driver IC 104, the application processor 102 generates the un-compressed display data Dl according to an input display data Dl provided by an external data source 105, and transmits the un-compressed display data Dl over the display interface 103.
  • the application processor 102 When the application processor 102 is used to transmit compressed data to the driver IC 104, the application processor 102 generates a compressed display data Dl ' according to the input display data Dl provided by the external data source 105, and transmits the compressed display data Dl ' over the display interface 103.
  • the data source 105 may be a camera sensor, a memory card or a wireless receiver
  • the input display data Dl may include image data, video data, graphic data, and/or OSD data.
  • the input display data Dl may be single view data for 2D display or multiple view data for 3D display.
  • the application processor 102 includes a display controller 112, an output interface 114 and other circuitry 116.
  • the other circuitry 116 includes circuit elements required for processing the input display data Dl to generate the un-compressed data Dl or the compressed data Dl '.
  • the other circuitry 116 may have a display processor, a compressor, a multiplexer, etc.
  • the display processor performs image processing operations, including scaling, rotating, etc.
  • the compressor performs data compression.
  • the multiplexer receives the un-compressed display data Dl and the compressed display data Dl ', and selectively outputs the un-compressed display data Dl or the compressed display data Dl ' according to the operation mode of the application processor 102.
  • the multiplexer when the application processor 102 is operated under a compression mode, the multiplexer outputs the compressed display data Dl '; and when the application processor 102 is operated under a non-compression mode, the multiplexer outputs the un-compressed display data Dl.
  • the present invention focuses on the control of the output interface 114, further description of the other circuitry 116 is omitted here for brevity.
  • the output interface 114 includes a packing unit 117 and a plurality of switches (e.g.,
  • each of the switches 118 1-118 4 controls whether a data line is used for data transmission.
  • the switches 118 1-118 4 are controlled by a plurality of enable signals EN0- EN3 generated from the display controller 112, respectively.
  • an enable signal has a first logic value (e.g., T)
  • a corresponding switch is enabled (i.e., switched on) to enable the data transmission over the corresponding data line; and when the enable signal has a second logic value (e.g., ⁇ '), the corresponding switch is disabled (i.e., switched off) to disable the data transmission over the corresponding data line.
  • T When an enable signal has a first logic value (e.g., T), a corresponding switch is enabled (i.e., switched on) to enable the data transmission over the corresponding data line; and when the enable signal has a second logic value (e.g., ⁇ '), the corresponding switch is disabled (i.e., switched off) to disable the data transmission over the corresponding data line.
  • the driver IC 104 it communicates with the application processor 102 via the display interface 103.
  • the driver IC 104 supports un-compressed data reception and compressed data reception.
  • the application processor 102 transmits the uncompressed data Dl to the driver IC 104
  • the driver IC 104 is operated under a non-decompression mode to receive an un-compressed data D2 from the display interface 103 and drive a display panel 106 according to the un-compressed display data D2.
  • the display panel 106 may be implemented using any 2D/3D display device (e.g. a retina display), and the pixel arrangement may be a rectangle layout, a triangle layout or a pentile layout.
  • the driver IC 104 When the application processor 102 transmits the compressed data Dl ' to the driver IC 104, the driver IC 104 is operated under a de-compression mode to receive a compressed display data D2' from the display interface 103 and drive the display panel 106 according to a de-compressed display data derived from decompressing the compressed display data D2'. If there is no error introduced during the data transmission, the un-compressed data Dl transmitted under the non-compression mode should be identical to the un-compressed data D2 received under the non-decompression mode, and the compressed data Dl ' transmitted under the compression mode should be identical to the compressed data D2' received under the de-compression mode.
  • the driver IC 104 includes a driver IC controller 122, an input interface 124 and other circuitry 126.
  • the other circuitry 126 may include circuit elements required for driving the display panel 106 according to a video mode or an image/command mode.
  • the other circuitry 126 may have a de-compressor, a display buffer, multiplexers, etc.
  • the de-compressor is used for performing data de-compression to obtain a de-compressed display data.
  • the display buffer is arranged for storing a display data which is an un-compressed display data, a compressed display data or a de-compressed display data, depending upon actual design consideration/requirement.
  • the multiplexers control interconnections of the de-compressor, the display buffer and the display panel 106. As the present invention focuses on the control of the input interface 124, further description of the other circuitry 126 is omitted here for brevity.
  • the input interface 124 includes an un-packing unit 127 and a plurality of switches (e.g., 128 1, 128_2, 128_3 and 128 4). It should be noted that the number of the switches included in the input interface 124 is equal to the number of data lines included in the display interface 103. Hence, each of the switches 128 1-128 4 controls whether a data line is used for data reception. In this embodiment, the switches 128 1-128 4 are controlled by a plurality of enable signals EN0'- EN3' generated from the driver IC controller 122, respectively.
  • EN0'- EN3' generated from the driver IC controller 122
  • an enable signal has a first logic value (e.g., T)
  • a corresponding switch is enabled (i.e., switched on) to enable the data reception over the corresponding data line; and when the enable signal has a second logic value (e.g., ⁇ '), the corresponding switch is disabled (i.e., switched off) to disable the data reception over the corresponding data line.
  • T When an enable signal has a first logic value (e.g., T), a corresponding switch is enabled (i.e., switched on) to enable the data reception over the corresponding data line; and when the enable signal has a second logic value (e.g., ⁇ '), the corresponding switch is disabled (i.e., switched off) to disable the data reception over the corresponding data line.
  • the display controller 112 controls the other circuitry 116 to generate the un-compressed display data Dl to the output interface 114, and controls the output interface 114 to use all of the data lines DL0- DL3, each having a predetermined operating frequency, for data transmission.
  • the predetermined operating frequency i.e., a bit clock rate per line
  • the pixel rate equals 161 MHz.
  • the bit clock rate per line reaches 970 Mbps.
  • the driver IC controller 122 controls the input interface 124 to use all of the data lines DL0-DL3, each having the predetermined operating frequency, for data reception, and controls the other circuitry 126 to drive the display panel 106 based on the un-compressed display data D2.
  • the packing unit 117 is arranged for packing/packetizing the un-compressed display data Dl based on the transmission protocol of the display interface 103 and accordingly generating an output bitstream to the display interface 103, wherein all of the switches 118 1-118 4 are enabled (i.e., switched on), and each data line is operated under the predetermined operating frequency (e.g., 970 Mbps) determined according to above equations.
  • the output interface 114 has a transmission setting for packing/packetizing the un-compressed display data Dl into an output bitstream and outputting the output bitstream via the display interface 103.
  • the un-packing unit 117 is arranged for un- packing/un-packetizing an input bitstream based on the transmission protocol of the display interface 103 and accordingly generating the un-compressed display data D2 to the other circuitry 126, wherein all of the switches 128 1-128 4 are enabled (i.e., switched on), and each data line is operated under the predetermined operating frequency (e.g., 970 Mbps) determined according to above equations.
  • the input interface 124 has a reception setting for receiving an input bitstream via the display interface 103 and un-packing/un-packetizing the input bitstream into the un-compressed display data Dl that is transmitted over the display interface 103.
  • the aforementioned un-compressed data transmission is exploited and standardized by MIPFs DSI and VESA's eDP.
  • MIPFs DSI and VESA's eDP may not afford the high data rate, and may have potential problems in high power dissipation and low design yield.
  • the other circuitry 116 in the application processor 102 is configured to have a compressor implemented therein, and the other circuitry 126 in the driver IC 104 is configured to have a de-compressor implemented therein.
  • the compressed data transmission over the display interface 103 is realized through the compressor and the de-compressor.
  • the display controller 112 controls the other circuitry 116 to generate the compressed display data Dl ' to the output interface 114, wherein the compressor implemented in the other circuitry 116 may employ a lossy or lossless compression algorithm, depending upon actual design consideration/requirement.
  • the packing unit 117 packs/packetizes the compressed display data Dl ' based on the transmission protocol of the display interface 103 and accordingly generates an output bitstream to the display interface 103.
  • the output interface 114 is arranged for packing/packetizing the compressed display data Dl ' into an output bitstream and outputting the output bitstream via the display interface 103.
  • the driver IC controller 122 controls the other circuitry 126 to drive the display panel 106 based on the compressed display data D2', wherein the de-compressor implemented in the other circuitry 126 may employ a lossy or lossless de-compression algorithm, depending upon actual design consideration/requirement.
  • the un-packing unit 127 un-packs/un- packetizes the input bitstream into the compressed display data D2' based on the transmission protocol of the display interface 103.
  • the input interface 124 is arranged for receiving an input bitstream via the display interface 103, and un-packing/un-packetizing the input bitstream into the compressed display data D2' that is transmitted over the display interface 103.
  • the output interface 114 is controlled by the display controller 112 to have a different transmission setting
  • the input interface 124 of the driver IC 104 is controlled by the driver IC controller 122 to have a different reception setting.
  • the display interface 103 provides a data line management layer and is scalable to the number of data lines according to the bandwidth and the compression requirement.
  • the display controller 112 is therefore arranged for referring to at least a compression characteristic of the compressed display data Dl ' to configure a transmission setting of the output interface 114 over the display interface 103, and the driver IC controller 122 is arranged for configuring a reception setting of the input interface 124 over the display interface 103 in response to at least the compression characteristic of the compressed display data Dl '.
  • the aforementioned compression characteristic may be a compression ratio M corresponding to the compressed display data Dl ', where M ⁇ 1.0.
  • the compression ratio M may be expressed using the following equation.
  • the amount of un-compressed data reaches 192 bits (i.e., 4x2x24 bits).
  • the compression ratio M is equal 0.5
  • the compressed data would have 96 bits.
  • the number of data lines, the operating frequency of each data line, and/or the behavior in the blanking period may be adjusted to improve the overall system performance.
  • each of the display controller 112 and the driver IC controller 122 refers to the compression ratio M to configure the number of data lines enabled over the display interface 103 for data transmission and reception when the application processor 102 is used to transmit the compressed display data Dl ' to the driver IC 104, wherein an operating frequency of each data line (i.e., a bit clock rate of each data line) remains unchanged regardless of the configured number of data lines.
  • the application processor 102 may inform the driver IC 104 of the compression ratio M corresponding to the compressed display data Dl '.
  • the display controller 112 sets each of the enable signals EN0-EN3 by the first logic value (e.g., T) such that all of the switches 118 1-118 4 are enabled (i.e., switched on), and the driver IC controller 122 sets each of the enable signals EN0'-EN3' by the first logic value (e.g., ' 1 ') such that all of the switches 128 1-128 4 are enabled (i.e., switched on).
  • the first logic value e.g., T
  • the driver IC controller 122 sets each of the enable signals EN0'-EN3' by the first logic value (e.g., ' 1 ') such that all of the switches 128 1-128 4 are enabled (i.e., switched on).
  • the display controller 112 may set two of four enable signals (e.g., EN0 and EN1) by the first logic value (e.g., ' 1 ') and set the remaining enable signals (e.g., EN2 and EN3) by the second logic value (e.g., ⁇ '), and the driver IC controller 122 may set two of four enable signals (e.g., EN0' and EN1 ') by the first logic value (e.g., T) and set the remaining enable signals (e.g., EN2' and EN3') by the second logic value (e.g., ⁇ ').
  • EN0 and EN1 the first logic value
  • EN2 and EN3' the remaining enable signals
  • FIG. 2 is a flowchart illustrating a first control and data flow of the data processing system 100 shown in FIG. 1.
  • the compression ratio M is referenced to configure the number of data lines enabled over the display interface 103, and the operating frequency of each data line remains unchanged. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown in FIG. 2.
  • the exemplary first control and data flow may be briefly summarized by following steps.
  • Step 200 Start.
  • Step 202 Check if a compression mode is enabled. If yes, go to step 210; otherwise, go to step 204.
  • Step 204 The other circuitry 116 generates the un-compressed display data Dl according to the input display data DI.
  • Step 206 The display controller 112 controls the output interface 114 to switch on all of the switches 118 1-118 4. In this way, all of the data lines DL0-DL3 of the display interface 103 would be used by the application processor 102 for data transmission.
  • Step 208 The packing unit 117 directly packs/packetizes the un-compressed display data Dl into an output bitstream. Go to step 216.
  • Step 210 The other circuitry 116 generates the compressed display data Dl ' according to the input display data DI.
  • Step 212 The display controller 112 refers to the compression ratio M corresponding to the compressed display data Dl ' to switch on a portion of the switches 118 1-118 4. In this way, only part of the data lines DL0-DL3 of the display interface 103 would be used by the application processor 102 for data transmission.
  • Step 214 The packing unit 117 packs/packetizes the compressed display data Dl ' into an output bitstream.
  • Step 216 Transmit the output bitstream over the display interface 103.
  • Step 218 Check if a de-compression mode is enabled. If yes, go to step 226; otherwise, go to step 220.
  • Step 220 The driver IC controller 122 controls the input interface 124 to switch on all of the switches 128 1-128 4. In this way, all of the data lines DL0-DL3 of the display interface 103 would be used by the driver IC 104 for data reception.
  • Step 222 The un-packing unit 127 un-packs/un-packetizes an input bitstream into the un-compressed display data D2.
  • Step 224 The other circuitry 126 drives the display panel 106 according to the uncompressed display data D2. Go to step 232.
  • Strep 226 The driver IC controller 122 refers to the compression ratio M corresponding to the compressed display data Dl ' to switch on a portion of the switches 128 1- 128 4. In this way, only part of the data lines DL0-DL3 of the display interface 103 would be used by the driver IC 104 for data reception.
  • Step 228 The un-packing unit 127 un-packs/un-packetizes the input bitstream into the compressed display data D2'.
  • Step 229 The other circuitry 126 derives a de-compressed display data from de- compressing the compressed display data D2 ' .
  • Step 230 The other circuitry 126 drives the display panel 106 according to the decompressed display data.
  • Step 232 End.
  • steps 202-216 are performed by the application processor 102, and steps 218-230 are performed by the driver IC 104.
  • steps 202-216 are performed by the application processor 102
  • steps 218-230 are performed by the driver IC 104.
  • each of the display controller 112 and the driver IC controller 122 refers to the compression ratio M to configure an operating frequency of each data line (i.e., a bit clock rate of each data line) when the application processor 102 is used to transmit the compressed display data Dl ' to the driver IC 104, wherein the number of data lines enabled over the display interface 103 remains unchanged regardless of the configured operating frequency.
  • the application processor 102 may inform the driver IC 104 of the compression ratio M corresponding to the compressed display data Dl '.
  • all of the data lines DL0-DL3, each having the predetermined operating frequency, will be used for transmitting the un-compressed display data Dl.
  • each of the data lines DL0-DL3 is controlled to operate under the predetermined operating frequency, wherein all of the switches 118 1-118 4 are enabled (i.e., switched on) by the display controller 112, and all of the switches 128 1-128 4 are enabled (i.e., switched on) by the driver IC controller 122.
  • the operating frequency of each data line is set by a value equal to a product of the predetermined operating frequency (i.e., a non-compression/non-decompression mode bit clock rate) and the compression ratio M.
  • the required clock frequency selection may be implemented using different clock generators which supply clocks with different clock rates.
  • the bandwidth can be reduced by the interface compression, and the reduced operating frequency is related to the compression ratio M. Besides, due to the reduced operating frequency of each data line enabled over the display interface 103, the transmission power dissipation and EMI can be alleviated.
  • FIG. 3 is a flowchart illustrating a second control and data flow of the data processing system 100 shown in FIG. 1.
  • the compression ratio M is referenced to configure the operating frequency of each data line, and the number of data lines enabled over the display interface 103 remains unchanged. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown in FIG. 3.
  • the exemplary second control and data flow may be briefly summarized by following steps.
  • Step 300 Start.
  • Step 302 Check if a compression mode is enabled. If yes, go to step 310; otherwise, go to step 304.
  • Step 304 The other circuitry 116 generates the un-compressed display data Dl according to the input display data DL
  • Step 306 The display controller 112 controls the output interface 114 to set a predetermined operating frequency of data transmission on each data line.
  • Step 308 The packing unit 117 directly packs/packetizes the un-compressed display data Dl into an output bitstream. Go to step 316.
  • Step 310 The other circuitry 116 generates the compressed display data Dl ' according to the input display data DL
  • Step 312 The display controller 112 refers to the compression ratio M corresponding to the compressed display data Dl ' to set a reduced operating frequency of data transmission on each data line.
  • Step 314 The packing unit 117 packs/packetizes the compressed display data Dl ' into an output bitstream.
  • Step 316 Transmit the output bitstream over the display interface 103.
  • Step 318 Check if a de-compression mode is enabled. If yes, go to step 326; otherwise, go to step 320.
  • Step 320 The driver IC controller 122 controls the input interface 124 to set a predetermined operating frequency of data reception on each data line.
  • Step 322 The un-packing unit 127 un-packs/un-packetizes an input bitstream into the un-compressed display data D2.
  • Step 324 The other circuitry 126 drives the display panel 106 according to the uncompressed display data D2. Go to step 332.
  • Strep 326 The driver IC controller 122 refers to the compression ratio M corresponding to the compressed display data Dl ' to set a reduced operating frequency for data reception on each data line.
  • Step 328 The un-packing unit 127 un-packs/un-packetizes the input bitstream into the compressed display data D2'.
  • Step 329 The other circuitry 126 derives a de-compressed display data from decompressing the compressed display data D2'.
  • Step 330 The other circuitry 126 drives the display panel 106 according to the decompressed display data.
  • Step 332 End.
  • steps 302-316 are performed by the application processor 102, and steps 318-330 are performed by the driver IC 104.
  • steps 302-316 are performed by the application processor 102
  • steps 318-330 are performed by the driver IC 104.
  • the display controller 112 refers to the compression ratio M to configure a behavior of the output interface 114 during a blanking period between adjacent data transmissions
  • the driver IC controller 122 refers to the compression ratio M to configure a behavior of the input interface 124 during a blanking period between adjacent data transmissions, wherein the number of data lines enabled over the display interface 103 and the operating frequency of each data line remain unchanged regardless of the configured behavior of the output interface 114 and the configured behavior of the input interface 124.
  • FIG. 4 is a diagram illustrating the change of the blanking period after the interface compression is applied.
  • the banking period is generally shorter than the data transmission period.
  • the banking period is extended due to a shorter data transmission period.
  • the interface compression is capable of creating an extra blanking period.
  • the extra blanking period may allow negotiation between the application processor 102 and the driver IC 104 so as to alleviate electrostatic discharge (ESD), EMI and/or power consumption.
  • ESD electrostatic discharge
  • the data transmission may be turned off and/or additional commands may be sent from the application processor 102 to the driver IC 104.
  • the bandwidth can be reduced by the interface compression, and the extended blanking period is related to the compression ratio M.
  • FIG. 5 is a flowchart illustrating a third control and data flow of the data processing system 100 shown in FIG. 1.
  • the compression ratio M is referenced to configure the behavior of the output interface 114 and the input interface 124 during the blanking period, and the number of data lines enabled over the display interface 103 and the operating frequency of each data line remain unchanged. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown in FIG. 5.
  • the exemplary third control and data flow may be briefly summarized by following steps.
  • Step 500 Start.
  • Step 502 Check if a compression mode is enabled. If yes, go to step 508; otherwise, go to step 504.
  • Step 504 The other circuitry 116 generates the un-compressed display data Dl according to the input display data DL
  • Step 506 The packing unit 117 directly packs/packetizes the un-compressed display data Dl into an output bitstream. Go to step 514.
  • Step 508 The other circuitry 116 generates the compressed display data Dl ' according to the input display data DL
  • Step 510 The display controller 112 refers to the compression ratio M corresponding to the compressed display data Dl ' to configure the behavior of the output interface 114 during the blanking period between adjacent data transmissions.
  • Step 512 The packing unit 117 packs/packetizes the compressed display data Dl ' into an output bitstream.
  • Step 514 Transmit the output bitstream over the display interface 103.
  • Step 516 Check if a de-compression mode is enabled. If yes, go to step 522; otherwise, go to step 518.
  • Step 518 The un-packing unit 127 un-packs/un-packetizes an input bitstream into the un-compressed display data D2.
  • Step 520 The other circuitry 126 drives the display panel 106 according to the un- compressed display data D2. Go to step 528.
  • Strep 522 The driver IC controller 122 refers to the compression ratio M corresponding to the compressed display data Dl ' to configure the behavior of the input interface 214 during the blanking period between adjacent data transmissions.
  • Step 524 The un-packing unit 127 un-packs/un-packetizes the input bitstream into the compressed display data D2 ' .
  • Step 525 The other circuitry 126 derives a de-compressed display data from decompressing the compressed display data D2'.
  • Step 526 The other circuitry 126 drives the display panel 106 according to the decompressed display data.
  • Step 528 End.
  • steps 502-514 are performed by the application processor 102, and steps 516-526 are performed by the driver IC 104.
  • steps 502-514 are performed by the application processor 102
  • steps 516-526 are performed by the driver IC 104.
  • the display interface 103 may have at least one data line which is a bidirectional line.
  • the data line DLO as shown in FIG. 1 is bidirectional.
  • the display controller 112 may further check a de-compression capability of the driver IC 104 by sending a request to the driver IC 104, and the driver IC controller 122 may further inform the application processor 102 of the de-compression capability of the driver IC 104 by sending a response to the application processor 102.
  • the application processor 102 can detect whether the driver IC 104 has the ability of performing data de-compression, and further detect what kinds of de-compression algorithms the driver IC 104 supports if the driver IC 104 is equipped with de-compression capability. In a case where the driver IC 104 supports the interface compression, the driver IC 104 may enable the de-compression mode after transmitting the de-compression capability information in response to the request issued by the application processor 102. Next, the application processor 102 enables the compression mode according to a checking result of the de-compression capability of the driver IC 104, and configures the compressor in the other circuitry 116 to employ one of compression algorithms corresponding to de-compression algorithms supported by the driver IC 104.
  • the driver IC 104 when the driver IC 104 does not support the interface compression, the driver IC 104 simply operates under the non-decompression mode, and the application processor 102 would enable the non-compression mode according to the checking result of the de-compression capability of the driver IC 104.
  • FIG. 6 is a flowchart illustrating a method of setting the application processor 102 by referring to a result of checking a de-compression capability of the driver IC 104 according to an embodiment of the present invention. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown in FIG. 6.
  • the exemplary method may be briefly summarized by following steps.
  • Step 600 Start.
  • Step 602 Check a de-compression capability of the driver IC 104 to see if the driver IC 104 supports the proposed interface compression, and accordingly obtain a checking result.
  • Step 604 Refer to the checking result to determine if the de-compression mode in the driver IC 104 is set? If yes, go to step 606; otherwise, go to step 608.
  • Step 606 Enable the compression mode in the application processor 102. Go to step
  • Step 608 Enable the non-compression mode in the application processor 102.
  • Step 610 End.

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EP13845478.0A 2012-10-09 2013-09-18 Datenverarbeitungsvorrichtung zur konfiguration einer anzeigeschnittstelle auf basis von kompressionscharakteristiken komprimierter anzeigedaten und entsprechendes datenverarbeitungsverfahren Withdrawn EP2907108A4 (de)

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US201261711319P 2012-10-09 2012-10-09
US201261712949P 2012-10-12 2012-10-12
US13/937,224 US20140098893A1 (en) 2012-10-09 2013-07-09 Data processing apparatus for configuring display interface based on compression characteristic of compressed display data and related data processing method
PCT/CN2013/083739 WO2014056391A1 (en) 2012-10-09 2013-09-18 Data processing apparatus for configuring display interface based on compression characteristic of compressed display data and related data processing method

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EP13846200.7A Withdrawn EP2907304A4 (de) 2012-10-09 2013-09-09 Datenverarbeitungssystem zur übertragung komprimierter daten über eine anzeigeschnittstelle
EP13845478.0A Withdrawn EP2907108A4 (de) 2012-10-09 2013-09-18 Datenverarbeitungsvorrichtung zur konfiguration einer anzeigeschnittstelle auf basis von kompressionscharakteristiken komprimierter anzeigedaten und entsprechendes datenverarbeitungsverfahren

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US9466258B2 (en) 2016-10-11
CN104737223B (zh) 2017-10-20
US20140098119A1 (en) 2014-04-10
CN104704550A (zh) 2015-06-10
WO2014056389A1 (en) 2014-04-17
CN107181946A (zh) 2017-09-19
CN104704533A (zh) 2015-06-10
EP2907038A4 (de) 2016-05-25
CN107230461A (zh) 2017-10-03
CN104704551A (zh) 2015-06-10
US9514705B2 (en) 2016-12-06
US20140098114A1 (en) 2014-04-10
CN104737224A (zh) 2015-06-24
EP2907108A4 (de) 2016-05-25
CN104737224B (zh) 2016-10-05
EP2907038A1 (de) 2015-08-19
WO2014056391A1 (en) 2014-04-17
US9711109B2 (en) 2017-07-18
WO2014056407A1 (en) 2014-04-17
US20140098115A1 (en) 2014-04-10
US20140098110A1 (en) 2014-04-10
US20160253980A1 (en) 2016-09-01
US9633624B2 (en) 2017-04-25
WO2014056406A1 (en) 2014-04-17
CN107181946B (zh) 2019-05-21
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US9355613B2 (en) 2016-05-31
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US9773469B2 (en) 2017-09-26
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US20160253979A1 (en) 2016-09-01
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CN106097406A (zh) 2016-11-09

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