EP2856360B1 - Multi-fpga-prototypentwicklung einer asic-schaltung - Google Patents

Multi-fpga-prototypentwicklung einer asic-schaltung Download PDF

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Publication number
EP2856360B1
EP2856360B1 EP13724840.7A EP13724840A EP2856360B1 EP 2856360 B1 EP2856360 B1 EP 2856360B1 EP 13724840 A EP13724840 A EP 13724840A EP 2856360 B1 EP2856360 B1 EP 2856360B1
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Prior art keywords
programmable chips
hierarchy
routing
partitioning
modules
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English (en)
French (fr)
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EP2856360A1 (de
Inventor
Zied Marrakchi
Christophe ALEXANDRE
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Siemens Industry Software Inc
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Siemens Industry Software Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Definitions

  • the invention relates to the prototyping of an ASIC circuit by means of a system of the multi-FPGA type.
  • each functional block is an FPGA
  • the connections between functional blocks will be the connections between the FPGAs on the board.
  • Verilog netlist board which defines each FPGAs and the connections between the different FPGAs.
  • the aim of the invention is to provide a solution to remedy these drawbacks.
  • Logical Design it is a set of logical instances (modules). Each module communicates with different other modules by signals. Each module has a logical resource value that corresponds to the amount of logical resources it contains. Module resources are determined by the logic synthesis process. Logical Design and Design NetList are used interchangeably in this document.
  • Configurable system It is a hardware platform containing multiple programmable heterogeneous elements interconnected by physical tracks (printed circuit tracks). Each programmable element has a logical capacity which corresponds to the quantity of each logical resource it contains.
  • a logical resource is a basic logical block (Lut, Ram %) contained in the element.
  • interconnections which are physical tracks connecting pins of elements
  • flexible interconnections which are flexible physical connectors allowing to connect free pins of the elements, by cables.
  • This system can be thought of as a logical design in which the instances are programmable elements and the signals are the physical tracks.
  • Configurable System and Board Interconnect List are used interchangeably in the following, and analogously, programmable element and FPGA are used interchangeably in the following.
  • Identification It is about matching a logical design on a configurable system.
  • the constraints are on the one hand the limit of the logical resources available per programmable element (logical resource constraint), and on the other hand the limit of the pins available per element and the limit of the connection tracks between pairs of elements (constraint of logical connections).
  • the goal is to achieve maximum system frequency.
  • Proposed solution For large complex designs, the sum of the instance logical resources (sum of the dimensions of the design modules) is greater than the sum of the logical resources available per element (element capacity).
  • partitioning By partitioning, the constraint of connections is relaxed and transformed into a goal of reducing inter-module communications when placed in different elements. After partitioning, if the number of signals exchanged between the parts is greater than the number of physical tracks available, it is mandatory to group the signals to share the same track.
  • the compiler according to the invention makes it possible to meet the constraint of logical resources and to obtain the maximum clock frequency of the system in a completely automated manner.
  • the design implementation flow consists of the following steps:
  • This flow is iterative. One iteration is to perform all four steps. After the time analysis, if the required frequency is reached, we generate the netlist of each FPGA sub-design, and the intra-FPGA time constraints (time budget). If the frequency is not reached, critical modules and connections are identified and labeled. The design is analyzed (step 1) with respect to these characteristics to improve the quality of the result.
  • Hierarchical module (instance) it is a module which instantiates (contains) other modules (children)
  • Leaf module is a module without a child module
  • Hierarchical Design is a design that contains hierarchical modules
  • Internal Signal is a signal connecting only children of the same module
  • External signal is a signal that connects two children belonging to two different modules
  • Module flattening the module disappears but we keep its children (example of module A)
  • Module preservation when we preserve a module we keep its perimeter and all its children are not considered in the partition phase (they cannot be separated).
  • Example: module B is preserved.
  • the object of the design analysis is to create a new design hierarchy suitable for the partition process.
  • This new hierarchy is created from the initial design hierarchy by deploying the hierarchical modules.
  • the modules to be deployed or to be preserved are chosen firstly with regard to the constraints and secondly to the optimization phase.
  • the implicit constraints relate to the intrinsic characteristics of the problem: quantity of design resources against quantity of target resources, initial partition constraints.
  • the User constraints are deduced from user commands such as assignment commands, indivisible commands or group commands.
  • the quality criterion can be the Number of Rent's of the module or its combinatorial / sequential characteristic.
  • modules in the new hierarchy can be tagged with their lost common parent.
  • N is equal to the number of hierarchical levels.
  • the frequency of the system depends mainly on: the Multiplexing Ratio which defines how many signals are sent successively in the same clock period; and the number of signals multiplexed in a combinational path, which corresponds to the number of combinational HOPs multiplexed per critical path.
  • Some configurable systems have flexible interconnections and can be customized to better match the characteristics of the design implemented. So when the board is manufactured, some element pins are left free (not connected by physical tracks to pins of other elements but connected to specific connectors).
  • the invention allows specifying how to connect the connection pins and add cables between them. Then, in the routing phase, these cables are considered to be physical tracks.
  • the cable assignment problem can be solved as a routing problem if one can model the free connection pins in the routing graph.
  • a connector group of pins
  • the fact that connectors are flexible is modeled by adding edges (possibility to connect) between all nodes (representing connectors).
  • the tracks that remain frozen are grouped into super-tracks.
  • Each supertrack presents a group of tracks with the same source and destination element.
  • the size of a super track is equal to the size of the connector.
  • each connector is represented by a node. Consequently, we obtain a compressed graph.
  • We create super-branches which are groups of meta-branches.
  • the size of a super branch is equal to the connector size. In this way, negotiation-based routing can be performed to route the compressed design to the compressed graph.
  • the result of the routing defines how the branches are grouped (multiplexed), their path and connector connections (cables).

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Claims (11)

  1. Computerimplementiertes Verfahren zur Entwicklung eines Prototypen, der mehrere programmierbare Chips aufweist, wie beispielsweise FPGA-Chips, die durch physische Bahnen einer Karte miteinander verbunden sind, um eine ASIC-Schaltung zu modellieren, wobei diese ASIC-Schaltung dazu bestimmt ist, eine Logikentwicklung umzusetzen, die eine Hierarchie von Logikmodulen aufweist, die miteinander kommunizieren, wobei dieses Verfahren die folgenden Schritte aufweist:
    - Partitionieren der Hierarchie von Logikmodulen in Bereiche, die jeweils einen oder mehrere programmierbare Chips aufweisen, durch Minimierung:
    - einerseits der Kommunikationen zwischen Bereichen auf eine Weise, die mit den physischen Verbindungen korreliert, die zwischen jedem Paar von programmierbaren Chips verfügbar ist;
    - und andererseits der Anzahl von Durchquerungen von programmierbaren Chips von einem kritischen kombinatorischen Pfad; und
    - Herstellen eines Routings der Signale zwischen programmierbaren Chips unter Nutzung der verfügbaren physischen Ressourcen, wobei das Herstellen des Routings das Routing der physischen Bahnen der Karte und der Kabel, die mit programmierbaren Chips verbunden sind, aufweist,
    wobei iterativ und automatisiert Modifikationen auf die Partitionierung angewandt werden, bevor ein neues Routing hergestellt wird und die Betriebsfrequenz des Prototyps, der von den programmierbaren Chips der Bereiche durch eine Zeitanalyse geschätzt wird, bis eine Zielfrequenz erreicht wird,
    das Verfahren ferner aufweisend, vor dem Schritt des Partitionierens, einen Schritt des Erzeugens einer neuen Hierarchie von Logikmodulen ausgehend von der Hierarchie der Logikmodule der Logikentwicklung durch Einebnung der Module, die nicht bewahrt werden können, gemäß Entwicklungszwängen, wobei die Logikentwicklung umgesetzt wird, und wobei der Schritt des Partitionierens auf diese neue Hierarchie angewandt wird.
  2. Verfahren nach Anspruch 1, wobei das Partitionieren rekursiv ist, um sich an die Hierarchie der programmierbaren Plattform anzupassen, durch:
    - Partitionierung der Hierarchie in Bereiche, die jeweils Ressourcen aufweisen, die auf die Summe der Ressourcen der programmierbaren Chips begrenzt ist, die sie enthält;
    - Partitionierung der Entwicklungsinstanzen, die zu jedem Bereich gehören, zwischen lokalen programmierbaren Chips, ohne es den Instanzen eines programmierbaren Chips zu erlauben, sich zu einem programmierbaren Chip eines unterschiedlichen Bereichs zu bewegen.
  3. Verfahren nach Anspruch 1 oder 2, wobei der Schritt des Herstellens eines Routings der Signale zwischen den programmierbaren Chips unter Nutzung der verfügbaren physischen Ressourcen durch Darstellung der Ressourcen der Karte durch einen Graphen sichergestellt wird, in welchem die Knoten Kontaktstifte programmierbarer Chips und die Ränder physische Bahnen sind.
  4. Verfahren nach Anspruch 1, umfassend einen Schritt des Ausgestaltens des Prototypen mit einer Liste der Logikmodule und des Routings der Signale.
  5. Verfahren nach Anspruch 1, umfassend einen Schritt des Analysierens der Kritizität der Signale und einen Schritt des Multiplexens der Signale, wobei die kritischsten Signale mit den niedrigsten Multiplexverhältnissen gemultiplext werden.
  6. Prototyping-System zur Umsetzung einer Entwicklung, die eine Hierarchie von Modulen umfasst, umfassend:
    eine Karte, die physische Bahnen umfasst; und
    eine Mehrzahl von programmierbaren Chips, die durch die Leiterbahnen miteinander verbunden sind, wobei die programmierbaren Chips durch ein Verfahren ausgestaltet sind, das Folgendes umfasst:
    das Partitionieren der Hierarchie von Modulen in Bereiche, die jeweils mindestens einen programmierbaren Chip umfassen, durch Minimierung der Kommunikationen zwischen Bereichen auf eine Weise, die mit den physischen Verbindungen korreliert, die zwischen jedem Paar von programmierbaren Chips verfügbar sind, und der Anzahl von Durchquerungen von programmierbaren Chips von einem kritischen kombinatorischen Pfad; und
    das Herstellen eines Routings der Signale zwischen programmierbaren Chips unter Nutzung der verfügbaren physischen Ressourcen, wobei das Herstellen des Routings das Routing der physischen Bahnen der Karte und der Kabel zwischen programmierbaren Chips umfasst,
    wobei iterativ und automatisiert Modifikationen auf die Partitionierung angewandt werden, bevor ein neues Routing hergestellt wird und die Betriebsfrequenz des Prototyps, der von den programmierbaren Chips der Bereiche durch eine Zeitanalyse geschätzt wird, bis eine Zielfrequenz erreicht wird,
    das System ferner aufweisend, vor dem Partitionieren, ein Erzeugen einer neuen Hierarchie von Logikmodulen ausgehend von der Hierarchie der Logikmodule der Logikentwicklung durch Einebnung der Module, die nicht bewahrt werden können, gemäß Entwicklungszwängen, wobei die Logikentwicklung umgesetzt wird, und wobei das Partitionieren auf diese neue Hierarchie angewandt wird.
  7. System nach Anspruch 6, wobei das Herstellen des Routings der Signale ein Multiplexen der Signale auf den physischen Bahnen der Karte umfasst.
  8. System nach Anspruch 7, wobei ein Multiplexverhältnis verringert wird, indem andere programmierbare Chips durchlaufen werden, um ein Endziel zu erreichen.
  9. Computerprogramm vom Typ Compiler, der eine Entwicklung umsetzt, die eine Hierarchie von Modulen auf einem Prototyping-System umsetzt, das eine Karte, die physische Bahnen umfasst, und eine Mehrzahl von programmierbaren Chips, die durch die Leiterbahnen miteinander verbunden sind, umfasst, wobei das System angeordnet ist:
    die Hierarchie von Modulen in Bereiche zu partitionieren, die jeweils mindestens einen programmierbaren Chip umfassen, durch Minimierung der Kommunikationen zwischen Bereichen auf eine Weise, die mit den physischen Verbindungen korreliert, die zwischen jedem Paar von programmierbaren Chips verfügbar sind, und der Anzahl von Durchquerungen von programmierbaren Chips von einem kritischen kombinatorischen Pfad; und
    ein Routing der Signale zwischen programmierbaren Chips unter Nutzung der verfügbaren physischen Ressourcen herzustellen, wobei das Herstellen des Routings das Routing der physischen Bahnen der Karte und der Kabel zwischen programmierbaren Chips aufweist,
    wobei iterativ und automatisiert Modifikationen auf die Partitionierung angewandt werden, bevor ein neues Routing hergestellt wird und die Betriebsfrequenz des Prototyps, der von den programmierbaren Chips der Bereiche durch eine Zeitanalyse geschätzt wird, bis eine Zielfrequenz erreicht wird,
    wobei das Programm ferner angeordnet ist, vor dem Partitionieren eine neue Hierarchie von Logikmodulen zu erzeugen, ausgehend von der Hierarchie der Logikmodule der Logikentwicklung durch Einebnung der Module, die nicht bewahrt werden können, gemäß Entwicklungszwängen, wobei die Logikentwicklung umgesetzt wird, und wobei das Partitionieren auf diese neue Hierarchie angewandt wird.
  10. Computerprogramm nach Anspruch 9, wobei das Herstellen des Routings der Signale ein Multiplexen der Signale auf den physischen Bahnen der Karte umfasst.
  11. Computerprogramm nach Anspruch 9, wobei ein Multiplexverhältnis verringert wird, indem andere programmierbare Chips durchlaufen werden, um ein Endziel zu erreichen.
EP13724840.7A 2012-06-01 2013-05-24 Multi-fpga-prototypentwicklung einer asic-schaltung Active EP2856360B1 (de)

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FR1201577A FR2991476B1 (fr) 2012-06-01 2012-06-01 Prototypage multi-fpga d'un circuit asic
PCT/EP2013/060718 WO2013178543A1 (fr) 2012-06-01 2013-05-24 Prototypage multi-fpga d'un circuit asic

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CN112364590B (zh) * 2020-10-28 2022-08-09 福州大学 一种实用的逻辑验证架构级fpga布线器的构建方法
CN112329367A (zh) * 2020-12-02 2021-02-05 国微集团(深圳)有限公司 一种基于图卷积神经网络的逻辑设计切割方法及系统
CN114330184B (zh) * 2022-03-15 2022-07-15 上海国微思尔芯技术股份有限公司 一种多层次分组方法及装置
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EP2856360A1 (de) 2015-04-08
US20170053052A1 (en) 2017-02-23
FR2991476A1 (fr) 2013-12-06
WO2013178543A1 (fr) 2013-12-05
FR2991476B1 (fr) 2022-04-22
US9400860B2 (en) 2016-07-26
US9817934B2 (en) 2017-11-14
US20150286761A1 (en) 2015-10-08

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