Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
  • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
  • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/50—Physical imperfections
  • H10D62/57—Physical imperfections the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
  • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
  • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials

Definitions

• This disclosure presents a high electron mobility transistor (HEMT) having a controlled lateral two-dimensional electron gas in type III nitride devices using ion
• This disclosure relates to type III - nitride HEMT devices and in particular to two dimensional electron gas (2DEG) in the drift region.
• 2DEG two dimensional electron gas
• a high electron mobility transistor is a field effect transistor incorporating a junction between two materials with different band gaps (i.e., a heteroj unction) .
• Gallium nitride (GaN) HEMTs have attracted attention due to their high-power performance.
• type Ill-nitride HEMT devices used in power applications there is a design tradeoff between the on-state resistance and breakdown voltage
• field plate and multistep field plates are some of the techniques that are used to improve the electric field distribution. However, field plates typically result in multiple peaks and suffer from less than ideal flat field distribution, and may exhibit a saw tooth profile. Field plates also add to the gate to drain capacitance. In
• a high electron mobility field effect transistor comprises a two dimensional electron gas (2DEG) in the drift region between the gate and the drain that has a non-uniform lateral 2DEG distribution that increases in a direction in the drift region from the gate to the drain.
• 2DEG two dimensional electron gas
• a high electron mobility field effect transistor comprises lattice damage in a drift region of a carrier supply layer between a gate and a drain, wherein the lattice damage decreases in a direction in the drift region from the gate to the drain.
• a method of fabricating a high electron mobility field effect transistor comprises forming a channel carrier traveling layer on a substrate, forming a carrier supply layer on the channel carrier traveling layer, forming a mask layer on the carrier supply layer, the mask layer configured to be aligned with a drift region from a gate to a drain, and configured to have a lateral variation in a direction from the gate to the drain, and implanting ions through the mask layer into the carrier supply layer.
• HEMT high electron mobility field effect transistor
• FIG. 1 shows the use of a gray scale mask to control ion implantation to be tapered in a drift region in accordance with the present disclosure
• FIG. 2 shows a tapered two dimensional electron gas (2DEG) charge density in a type III Nitride device in accordance with the present disclosure
• FIGs. 3A-3C are flow diagrams for methods of fabricating a HEMT device in accordance with the present disclosure.
• a field effect transistor (FET) device structure 10 is shown.
• the FET device structure 10 is composed of a stack of III-V layers, such as GaN layer 14 and AlGaN layer 16, grown on a substrate 12 that can be any of the suitable substrates that are commonly used to grow type Ill-nitride materials.
• Suitable substrates include but are not limited to silicon (Si), Sapphire, silicon carbide (SiC) , and bulk single crystal gallium nitride (GaN) .
• the stack of III-V layers may include a buffer layer of GaN or aluminum gallium nitride (AlGaN) grown on the substrate 12. Then a channel layer also known as a channel carrier travelling layer, such as GaN layer 14, is grown on the buffer layer. Then a barrier layer also known as a carrier supplying layer, such as AlGaN layer 16, is grown on top of the GaN layer 14. An A1N spacer layer may be between the GaN layer 14 and the AlGaN layer 16 to improve device electrical performance.
• AlGaN aluminum gallium nitride
• a suitable masking layer 50 which may be Si 3 N 4 , is grown.
• the masking layer 50 is used as a masking layer to stop the majority of the ions implanted via ion implantation 52 from reaching the AlGaN layer 16. Only a small fraction of the implanted ions, the tail of the Gaussian distribution, are intended to reach the AlGaN layer 16 to cause damage to the lattice. The small fraction of ions that succeed in reaching the AlGaN layer 16 ideally do not penetrate deep into the AlGaN layer 16.
• the masking layer 50 is configured to vary the density of ions implanted along the drift region between a gate and a drain of a field effect transistor (FET) .
• a mask layer 50 may be used, as shown in FIG. 1, to form a tapered mask layer 60 in the drift region between points 62 and 64.
• the tapered mask layer 60 has a lateral profile and has a height that increases towards the drain.
• a mask may be used that has with various size openings to vary the density of ions implanted along the drift region. Either type of mask modulates the ion
• the mask layer 50 may be configured to provide a lattice damage that linearly increases from point 64, along the drift region from near the drain 20, to point 62 near the gate 22.
• the source contact 18 and drain contact 20 shown in FIG. 2 may be formed by metal evaporation or metal
• a passivation layer 24 may be deposited between the source 18 and the drain 20.
• a gate region is then formed by etching through the passivation layer 24 in a gate area between the source 18 and drain 20 and into the AlGaN layer 16. In another embodiment the etch may extend through the AlGaN layer 16 and partially into the GaN layer 14 to an appropriate depth.
• a gate dielectric 26 is then deposited over the area between the source 18 and gate 22 and the gate 22 and the drain 20, and also deposited to line the etched trench that extends into the AlGaN layer 16. If the etched trench extends into the GaN layer 14, then the gate dielectric 26 also lines the etched trench that extends into the GaN layer 14.
• gate metal 22 is formed by evaporation or sputtering and fills the etched trench.
• alternating passivation and metallization layers may be formed as a part of back-end processing to improve the parasitic resistance of the device and provide connection to device pads and/or a package.
• the distribution of lattice damage in the drift region of the AlGaN layer 14 provides a significant improvement of the figure of merit (FOM) in type III Nitride HEMT devices by achieving flat electric field distribution in the drift region between the gate 22 and the drain 20.
• FOM figure of merit
• the 2DEG 42 is varied in the drift region to form a non-uniform lateral 2DEG distribution 44. As shown in the embodiment of FIG. 2, the 2DEG increases in the drift region in the direction from the gate 22 towards the drain 20.
• the stress in the AlGaN layer 16 may be varied by opening windows in the photo resist with varying size where the size of the opening is a function of the lateral distance from the gate to the drain.
• the size of the openings may be larger or smaller in the drift region near the gate and decrease or increase, respectively, in the drift region in the direction of the drain.
• the 2DEG 44 density increases as a function of distance from the gate region along the drift region, as shown in FIG. 2.
• FIGs. 3A-3C are flow diagrams for methods of fabricating a HEMT a type III Nitride device in accordance with the present disclosure.
• a channel carrier traveling layer 14 is formed on a substrate 12. Then in step 102 a carrier supply layer 16 is formed on the channel carrier traveling layer 14.
• the layers 14 and 16 are formed by an epi manufacturer .
• a mask layer 50 is formed on the carrier supply layer 16.
• the mask layer is configured to be aligned with a drift region from a gate to a drain, and configured to be have a lateral variation in a direction from the gate to the drain.
• ions 52 are implanted through the mask layer 50 into the carrier supply layer 16.
• the mask layer is formed in step 108 by forming a tapered section on the mask layer that has a thickness that increases in the direction from the gate to the drain by using gray scale photolithography and then in step 110 etching the mask layer to form the tapered section.
• the mask layer is formed by coating the carrier supply layer with photoresist in step 112 and then in step 114 opening windows in the photoresist of varying size such that the size of the openings decrease in the direction from the gate to the drain.
• a high electron mobility field effect transistor comprising:
• a two dimensional electron gas (2DEG) in the drift region between the gate and the drain that has a non-uniform lateral 2DEG distribution that increases in a direction in the drift region from the gate to the drain.
• concept 2 The HEMT of concept 1 further comprising:
• the lattice damage decreases in a direction in the drift region from the gate to the drain.
• the HEMT of concept 1 further comprising:
• a channel carrier traveling layer on the substrate a channel carrier traveling layer on the substrate; and a carrier supply layer on the channel carrier traveling layer .
• the substrate comprises silicon (Si) , sapphire, silicon carbide (SiC) , OR bulk single crystal gallium nitride (GaN) ;
• the channel carrier traveling layer comprises a GaN layer;
• the carrier supply layer comprises a AlGaN layer.
• the HEMT of concept 4 further comprising:
• a gate dielectric layer surrounding the gate metal extending through the passivation layer and into the AlGaN layer .
• the HEMT of concept 4 further comprising:
• the gate comprises:
• a gate dielectric layer surrounding the gate metal extending through the passivation layer and the AlGaN layer and into the GaN layer.
• a high electron mobility field effect transistor comprising:
• the lattice damage decreases in a direction in the drift region from the gate to the drain.
• a two dimensional electron gas (2DEG) in the drift region between the gate and the drain that has a non-uniform lateral 2DEG distribution that increases in a direction in the drift region from the gate to the drain.
• a channel carrier traveling layer on the substrate a channel carrier traveling layer on the substrate; and a carrier supply layer on the channel carrier traveling layer .
• the substrate comprises silicon (Si) , sapphire, silicon carbide (SiC) , or bulk single crystal gallium nitride (GaN) ;
• the channel carrier traveling layer comprises a GaN layer;
• the carrier supply layer comprises a AlGaN layer.
• the HEMT of concept 10 further comprising:
• the gate comprises:
• a gate dielectric layer surrounding the gate metal extending through the passivation layer and into the AlGaN layer .
• the HEMT of concept 10 further comprising:
• the gate comprises:
• a gate dielectric layer surrounding the gate metal extending through the passivation layer and the AlGaN layer and into the GaN layer.
• a method of fabricating a high electron mobility field effect transistor (HEMT) comprising:
• the mask layer configured to be aligned with a drift region from a gate to a drain, and configured to have a lateral variation in a direction from the gate to the drain;
• the method concept 13 further comprising:
• the substrate comprises silicon (Si) , sapphire, silicon carbide (SiC) , or bulk single crystal gallium nitride (GaN) ;
• the channel carrier traveling layer comprises a GaN layer;
• the carrier supply layer comprises a AlGaN layer.
• forming a passivation layer over the AlGaN layer; and forming a gate comprising the steps of:
• 2DEG two dimensional electron gas

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• 2013
  • 2013-05-09 WO PCT/US2013/040441 patent/WO2013176905A1/en not_active Ceased
  • 2013-05-09 CN CN201380024745.5A patent/CN105103296B/zh not_active Expired - Fee Related
  • 2013-05-09 EP EP13793952.6A patent/EP2852979A4/de not_active Ceased

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