EP2835760B1

EP2835760B1 - Switched capacitor differentiator

Info

Publication number: EP2835760B1
Application number: EP13179643.5A
Authority: EP
Inventors: Jiri Nerad
Original assignee: Asicentrum sro
Current assignee: Asicentrum sro
Priority date: 2013-08-07
Filing date: 2013-08-07
Publication date: 2019-01-16
Anticipated expiration: 2033-08-07
Also published as: EP2835760A1

Description

Field of the Invention

The present invention relates to the field of switched capacitor differentiators and to electronic devices comprising such a differentiator as well as to a method of operating a switched capacitor differentiator.

Background and Prior Art

Switched capacitor differentiators are widely known and are typically operable to generate an output signal reflecting a difference between two input signal samples which are either received at the same time or at subsequent points of time. In general, switched capacitor differentiators comprise at least one capacitor which is necessary to store one or two input voltage samples. Moreover, such differentiators also comprise an operational amplifier to store the two input signal samples and to generate an output signal being indicative of the difference between the two input signals.
The patent US 5,168,461 for instance discloses a backward mapping switched capacitor differentiator based on the inverting operational amplifier configuration featuring an input circuit comprising a first capacitor and a first switch. Moreover, a feedback circuit is implemented including a second capacitor in parallel with a second switch, wherein the feedback circuit has an input coupled to the output of an operational amplifier and an output coupled to the inverting input of said amplifier.
Li and Moon (IEEE J. Solid-State Circuits, vol. 39(9), pp. 1468-1476, 2004; DOI: :10.1109/JSSC.2004.829378) disclosed a 10-bit 100-MS/s pipelined ADC with time-shifted correlated double sampling (CDS). They reviewed multiplying DAC, used in such a pipelined ADC, with conventional CDS. In publication JP 2011-124843 A , a switched-capacitor differential amplifier is disclosed.
In general the capacitors used in switched capacitor differentiators feature non-negligible parasitic capacitances. Additionally, when using at least two or even more capacitors for storage of input signals the capacitors should mutually match. However, in practical scenarios such differentiator circuits exhibit a certain degree of capacitor mismatch. Additionally, also the operational amplifier inherently comprises a certain offset.
All of these mentioned phenomena may induce major or minor drawbacks on the general operation of such switched capacitor differentiators. Moreover, demands for low parasitic capacitances and low capacitor mismatch require elaborate selection of electronic components and render the production and manufacturing process rather complicated and cost intensive.

Summary of the Invention

It is therefore an object of the present invention to provide an improved switched capacitor differentiator, wherein parasitic capacitances of the capacitors or capacitor mismatch have only a minor effect or wherein such inevitable deficiencies of such components have reduced impact on the overall performance of the switched capacitor differentiator.
The present invention provides a method for operating a switched capacitor differentiator, according to independent claim 1 or independent claim 2, and a corresponding switched capacitor differentiator for implementing said method, according to independent claim 6. Further aspects of the invention are outlined in the dependent claims. Embodiments which do not fall within the scope of the claims do not describe part of the present invention.
According to a first example, the switched capacitor differentiator comprises an operational amplifier having an output, an inverting input and a non-inverting input. The capacitor differentiator further comprises an input port, typically to receive an input voltage signal and further comprises a reference voltage, that is a reference voltage supply. Additionally, the switched capacitor differentiator comprises a first capacitor and a second capacitor. Moreover, the switched capacitor differentiator also comprises a switching structure comprising various switches to alternately couple at least one of the first and the second capacitors with the operational amplifier, with the input port and/or with the reference voltage in at least three different switch configurations.
In a first switch configuration, the first capacitor is coupled between the input port and the reference voltage. Hence, when in the first switch configuration, the first capacitor is effectively charged with the difference between a first input voltage signal V1 and the reference voltage Vref.
In a second switch configuration, which is different from the first switch configuration, the second capacitor is coupled between the input port and a node connected to the operational amplifier output and the operational amplifier inverting input. In the second switch configuration a second input voltage signal is present at the input port. Moreover, since the second capacitor in the second switch configuration is placed between the input port and a node of the operational amplifier feedback loop, the second capacitor is charged with the difference between the second input voltage signal V2 and a voltage signal reflecting a combination of the reference voltage Vref and an offset voltage Voff of the operational amplifier.
In a third switch configuration the first and second capacitors are connected in series between the operational amplifier inverting input and output. In this third switch configuration both capacitors form part of the operational amplifier feedback loop. Therefore, any offset voltage of the operational amplifier that influences the circuit operation in the second switch configuration is effectively compensated or subtracted by the successive switch configurations. In effect, the settled output voltage of the operational amplifier in the third switch configuration is effectively independent of the offset voltage of the operational amplifier. Hence, in the third switch configuration an output signal can be provided, which is free of any influence of the operational amplifier offset voltage Voff.
Also, the effect of bottom plate parasitic capacitances of the first and/or the second capacitors can be reduced or even eliminated.
During the settling transient in the third, that is final, configuration, the bottom plate parasitic capacitance of the first capacitor is driven by the operational amplifier output and cannot introduce any signal charge error.
When the circuit reaches a settled state in the third, that is final, configuration, the voltage across the bottom plate parasitic capacitance of the second capacitor does not differ from its value at time of charging the second capacitor with the corresponding input voltage sample in the second switch configuration. Therefore, the presence of the bottom plate capacitance at the second capacitor cannot cause any signal error as all error charge is ultimately returned.
Moreover, it is due to the particular switching structure, that the settled output voltage of the operational amplifier in the third switch configuration does not depend on the ratio of capacitances of the two capacitors as there is effectively no charge redistribution between the first and the second capacitors during transition from one configuration to any other configuration. So the output of the operational amplifier and hence the output of the switched capacitor differentiator is effectively not degraded by any capacitor mismatch.
By the particular switching structure, even capacitors with substantial bottom plate parasitic capacitances or capacitors featuring a comparatively large degree of capacitor mismatch can be used without degrading the function of the switched capacitor differentiator. In effect, a rather cost efficient and improved switched capacitor differentiator can be provided.
According to an example the switching structure comprises three pairs of switches to alternately transfer the switching structure into the first, second or third switch configurations. The switching structure altogether comprises six switches. Typically, the two switches of a pair of switches can be activated or deactivated at the same time or with a small delay between each other, hence closed or opened simultaneously or not.
Moreover, in order to switch between any two of the first, second or third switch configurations always two pairs of switches have to be operated in such a way that both switches of one pair are opened and then the two switches of the other pair are closed, that is, there exists a period of time where no switch is closed. Typically, to transfer the differentiator from the first configuration into the second configuration, the first pair of switches is opened and then, after short pause time, the second pair of switches is closed. In the same way, the differentiator can be transferred from the second configuration to the third configuration by opening the second pair of switches and then closing the third pair. Also, the differentiator can be transferred from the third configuration to the first configuration by opening the third pair of switches and then closing the first pair.
Moreover, the switched capacitor differentiator is typically driven in such a way that it is transferred from the first switch configuration into the second switch configuration and thereafter into the third switch configuration. Thereafter, the switched capacitor differentiator returns into the first switch configuration. Switching of the switches or pairs of switches of the switched capacitor differentiator is typically driven by a clock signal. Moreover, the input signal present at the input port is synchronized with the clock signal so that a first input signal V1 is present at the input port while the differentiator is in the first switch configuration and in that a second input signal V2 is present at the input port while the switched capacitor differentiator is in the second switch configuration.
Accordingly and following another example one pair of switches is closed at a time to transfer the switching structure into one of first, second or third switch configurations, while residual pairs of switches are open. Consequently, activation of one pair of switches is sufficient to transfer the switched capacitor differentiator in one of the first, second or third switch configurations.
In still another example each pair of switches comprises two switches across the switching structure that are switchable simultaneously or with a small delay between each other and which are actually both switched on or off, that is, both switches have the same state in any configuration and change state either simultaneously or with a small delay between each other.
According to a further example at least one of the first and second capacitors is connectable with the operational amplifier by its bottom plate.
Typically and according to another example the bottom plate of the first capacitor is connectable to the operational amplifier output by a single switch belonging to the third switching pair. In this way, the bottom plate of the first capacitor is connected to the operational amplifier output when the switching structure is in the third switching configuration where the opposite plate, that is the top plate of the first capacitor, is preferably connected with a corresponding top plate of the second capacitor through another switch of the third switching pair.
Moreover and according to another example the bottom plate of the second capacitor is connected with the inverting input of the operational amplifier. Typically, the bottom plate of the second capacitor is permanently connected with the inverting input of the operational amplifier. The top plate of the second capacitor may be in turn connected to a respective top plate of the first capacitor, typically by a switch of the third pair of switches.
Consequently and according to another example the first and the second capacitors are connectable in series with their top plates while their bottom plates are connected with the output and with the inverting input of the operational amplifier.
With the above described layouts regarding the bottom plate and top plate connection of the first and second capacitors, the effect and influence of the bottom plate capacitance can be effectively compensated. Generally, when referring to plate capacitors, the top plate parasitic capacitance is much smaller compared to the bottom plate parasitic capacitance. In the present context, its effect on the operation of the switched capacitor differentiator may be substantially neglected.
According to another example at least one of the first and second capacitors comprises a sandwich structure. In the sandwich layout the bottom or outer plate effectively surrounds or encloses the top or inner plate of the capacitor. Compared to a conventional plate capacitor layout a sandwich capacitor layout features an increased bottom plate capacitance while virtually having no top plate capacitance. In this way, and since the bottom plate parasitic capacitance is compensated by the switching structure and the described switching scheme, the switched capacitor differentiator can be driven almost free of any errors otherwise due to bottom or top plate parasitic capacitances.
According to another example at least one of the first and second capacitors can also comprise a shielded fringe or comb structure where a fringe or comb capacitor is surrounded or enclosed by metal plates typically placed above and/or below said capacitor and preferably connected together outside the layout of said capacitor. The shielding plates are connected to one of the terminals of the fringe or comb capacitor, effectively forming an increased bottom plate capacitance while the other terminal of the fringe or comb capacitor has virtually no parasitic capacitance. Again, since the bottom plate parasitic capacitance is compensated by the switching structure and the described switching scheme, the switched capacitor differentiator can be driven almost free of any errors due to parasitic capacitances.
According to another example the switching structure comprises a first switch located between the input port and the first capacitor. The switching structure further comprises a second switch which is located between an opposite plate of the first capacitor and the reference voltage. Typically, the first and second switches form the first pair of switches which is to be activated to turn the switching structure into the first switch configuration. In this example the first capacitor is in line or in series with both, first and second switches. Closing of the first switch connects a top plate of the first capacitor with the input port while closing of the second switch connects the bottom plate of the first capacitor with the reference voltage.
According to a further example the switching structure comprises a third switch located between the input port and the second capacitor. The switching structure furthermore comprises a fourth switch located between the output of the operational amplifier and a node, wherein said node is in connection with the opposite plate of the second capacitor and is in connection with the inverting input of the operational amplifier. In other words, by means of the third switch the top plate of the second capacitor can be directly connected to the input port. By closing the fourth switch, a feedback loop of the operational amplifier connecting the output of the operational amplifier with its inverting input can be closed in order to place said operational amplifier in voltage follower mode. Here, the bottom plate of the second capacitor is connected with a node belonging to said feedback loop.
In still another example the switching structure comprises a fifth switch located between the top plates of the first and the second capacitors. Additionally, the switching structure comprises a sixth switch which is located between the bottom plate of the first capacitor and the output of the operational amplifier.
By means of the fifth switch, first and second capacitors can be connected in line or in series while the sixth switch may close a modified feedback loop of the operational amplifier. Closing of third and fourth switches corresponds to closing of the second pair of switches to transfer the switching structure into the second switch configuration. In a corresponding way, closing of fifth and sixth switches forming the third pair of switches transfers the switching structure into the third switch configuration.
Another example also relates to an electronic device comprising a switched capacitor differentiator as described above. In an example the electronic device further comprises a clock generator and an optical sensor, wherein the clock generator is connected to both the optical sensor and switched capacitor differentiator. The optical sensor is further directly connected to the input port of the switched capacitor differentiator in order to provide a sequence of input voltage signal samples.
By means of the clock generator, the switched capacitor differentiator can be repeatedly and alternately switched between the first, the second and the third switch configurations, wherein this switching is synchronized with varying input voltage signals at the input port of the switched capacitor differentiator. The output of the switched capacitor differentiator may then typically be used as an input for an analog-to-digital converter for further signal processing.
The switched capacitor differentiator may be used for a large variety of electronic devices, such as in optical signal processing systems that may be used in cameras, mobile phones, optical computer periphery devices or other.
Moreover another example also relates to a method of operating a switched capacitor differentiator as described above. Said method comprises the steps of transferring the switching structure of the switched capacitor differentiator into a first switch configuration in which the first capacitor is coupled between the input port and the reference voltage. Thereafter, in a subsequent step the switching structure is transferred into a second switch configuration in which the second capacitor is coupled between the input port and a node, wherein said node is connected to the operational amplifier output and the operational amplifier inverting input. Thereafter and in a third step, the switching structure is transferred into a third switch configuration in which the first and second capacitors are connected in series between the operational amplifier inverting input and output. The method of operating the switched capacitor differentiator can be modified in such a way that the switch connected between the inverted input and the output of the operational amplifier remains in a closed state during the first and second phases of the cycle, that is for the first and second switch configurations.
Moreover another example also relates to the alternative method of operating a switched capacitor differentiator as described above. Said method comprises the steps of transferring the switching structure of the switched capacitor differentiator into a first switch configuration in which the second capacitor is coupled between the input port and a node, wherein said node is connected to the operational amplifier output and the operational amplifier inverting input. Thereafter, in a subsequent step the switching structure is transferred into a second switch configuration in which the first capacitor is coupled between the input port and the reference voltage. Thereafter and in a third step, the switching structure is transferred into a third switch configuration in which the first and second capacitors are connected in series between the operational amplifier inverting input and output. The alternative method of operating the switched capacitor differentiator can be modified in such a way that the switch connected between the inverted input and the output of the operational amplifier remains in a closed state during the first and second phases of the cycle, that is for the first and second switch configurations.
It will be contemplated to those having ordinary skills in the art, that various modifications of the switched capacitor differentiator, the electronic device and the respective method of operating the capacitive differentiator may be made without departing from the scope of the present invention as it is defined in the appended claims. Moreover it has to be noted that any features and benefits described in connection with the switched capacitor differentiator equally relate to the method of operating the same and vice versa.

Brief Description of the Drawings

In the following, various embodiments of the invention will be described by making reference to the drawings, in which:

Figure 1 schematically illustrates a simplified circuit diagram of the switched capacitor differentiator,
Figure 2 shows an excerpt of the active components of the switched capacitor differentiator according to Figure 1 in the first switch configuration,
Figure 3 shows an excerpt of the active components of the switched capacitor differentiator according to Figure 1 in the second switch configuration,
Figure 4 shows the active components of the switched capacitor differentiator according to Figure 1 in the third switch configuration,
Figure 5 schematically illustrates a plate capacitor,
Figure 6 schematically shows a sandwich design of a capacitor,
Figure 7 schematically shows a simplified circuit diagram of an electronic device comprising the switched capacitor differentiator, and
Figure 8 is indicative of the three consecutive method steps for driving or operating the switched capacitor differentiator.

Detailed Description

In the circuit diagram according to Figure 1 the complete switched capacitor differentiator 10 is schematically illustrated. The switched capacitor differentiator 10 comprises an operational amplifier 12 having an output 18, an inverting input 14 and a non-inverting input 16. Additionally, the switched capacitor differentiator 10 comprises an input port 34, which is typically to be connected with an output of an optical sensor 60 as for instance illustrated in Figure 7.
Additionally, the switched capacitor differentiator 10 comprises a reference voltage 20, that is a reference voltage supply Vref. Moreover, a first capacitor 30 as well as a second capacitor 32 are provided. The reference voltage Vref 20 is connected to ground via a resistor divider 22 comprising a first resistor 24 and a second resistor 26. Between the first and second resistor 24, 26 connected in series there is provided a node 25 that is connected with the non-inverting input 16 of the operational amplifier 12.
Additionally, the switched capacitor differentiator 10 comprises a switching structure 40 comprising various switches 41, 42, 43, 44, 45, 46. The switches can be coupled pair-wise. Typically, switches 41 and 42 can form a first pair of switches, switches 43 and 44 can form a second pair of switches and switches 45 and 46 can form a third pair of switches. Closing a pair of switches, that is closing the two switches of a respective pair of switches, turns the switching structure 40 into the first, second or third switch configurations.
Typically, the first switch configuration shown in Figure 2 is achieved when the first and second switches 41, 42 forming the first pair of switches are closed. In the same way, the second switch configuration shown in Figure 3 is obtained by closing the third and fourth switch 43, 44 forming the second pair of switches, and the third switch configuration shown in Figure 4 is obtained by closing the third pair of switches, that is by closing switches 45 and 46.
As further illustrated in Figure 1, the first switch 41 is operable to connect the first capacitor 30 with the input port 34 while the second switch 42 is operable to connected said first capacitor 30 with the reference voltage 20. In detail, the first switch 41 is located between a node 51 and a node 56. The node 51 connects the first capacitor 30 with the fifth switch 45, which is further connected with another node 55, which in turn is connectable with the node 56 via the third switch 43.
Moreover, the second switch 42 actually connects a node 52 with the reference voltage 20. The node 52 is further connected with the first capacitor 30 and sixth switch 46. The other end or other terminal of the sixth switch 46 is in fact connected with another node 53. Said node 53 is further connected with the fourth switch 44, and the output 18 of the operational amplifier 12, which is identical to the output port 36 of the switched capacitor differentiator 10. The fourth switch 44 is located between the nodes 53, 54. By closing said fourth switch 44, the operational amplifier 12 is placed in the voltage follower mode. The node 54 is namely connected with the fourth switch 44 and with the inverting input 14 of the operational amplifier 12.
Also, the node 54 is permanently connected with the second capacitor 32, which is permanently connected with an opposite terminal to the node 55. Nodes 55 and 51 are connectable by means of the fifth switch 45 whereas the nodes 55 and 56 are connectable by means of the third switch 43.
When closing the first and the second switches 41, 42, hence when transferring the switched capacitor differentiator 10 in the first switch configuration the active components of the switched capacitor differentiator 10 are illustrated in Figure 2. As a consequence, the first capacitor 30 is effectively coupled between the first input voltage V1 and the reference voltage Vref. Here, a bottom plate 30a of the first capacitor 30 is connected to Vref while the bottom plate 30b is connected to the input port 34. As a consequence, a settled voltage across the first capacitor 30 substantially equals the difference V1 - Vref.
When switching the switching structure 40 from the first switch configuration into the second switch configuration, the first and second switches 41, 42 are opened and then the third and fourth switches 43, 44 are closed. As a consequence, the inverting input 14 of the operational amplifier 12 is connected with its output 18, thereby forming a feedback loop 13 and placing the operational amplifier 12 in a voltage follower mode.
Additionally, the second capacitor 32 is connected to the feedback loop 13 while being further connected with the input port 34. In other words, the input port 34 is coupled to the feedback loop 13 via the second capacitor 32. Also here, a top plate 32b of the second capacitor 32 is connected with the input port 34 while a bottom plate 32a of the second capacitor 32 is connected with the node 54 connected to the inverting input 14 of the operational amplifier. As a consequence, the settled voltage across the second capacitor equals V2 - (R·Vref - Voff), wherein Voff represents the offset voltage of the operational amplifier 12, wherein R represents the division ratio of the resistor divider formed by the resistors 24, 26 and wherein V2 represents the input voltage present at the input port 34 during the second switch configuration. The voltage at the non-inverting input 16 of the operational amplifier 12 equals R·Vref - Voff.
When switching now into the third switch configuration as it is illustrated in Figure 4, the third and fourth switches 43, 44 are opened and then the fifth and sixth switches 45, 46 are closed. As a consequence, the two capacitors 30, 32 are connected in series. Additionally, the first and second capacitors 30, 32 are directly connected with each other by their top plates 30b, 32b. Now, the first capacitor 30, in particular its bottom plate 30a, is connected to the output 18 of the operational amplifier 12 while the second capacitor, in particular its bottom plate 32a, is connected to the inverting input 14 of the operational amplifier 12. In this way, the first and second capacitors 30, 32 form a kind of a modified feedback loop of the operational amplifier 12.
Here, the settled voltage at the non-inverting input of the operational amplifier equals R·Vref - Voff while the settled voltage from the output 18 of the operational amplifier 12 to the non-inverting input 14 of the operational amplifier 12 equals V2 - (R·Vref - Voff) - (V1 - Vref). As a consequence, at the output port 32 a settled output voltage equals Vref - (V1 - V2). Hence, the inherent offset of the operational amplifier 12 has absolutely no effect on the output voltage of the switched capacitor differentiator 10.
Moreover, since by a comparison of the second and third switch configuration a settled voltage across the parasitic capacitance cp2 of the second capacitor 32 has not changed, the parasitic capacitance cp2 of the second capacitor 32 has not introduced any signal charge error. In other words, any error charge in the second capacitor 32 that may be due to switching activity at the top plate 32b of the second capacitor 32 is effectively compensated as any error charge is first transferred to the parasitic capacitance cp2 and then fully returned to the second capacitor 32 after the feedback loop reaches a steady state at the end of the third switch configuration.
Moreover, after the third switch configuration is established, the parasitic capacitance cp1 of the first capacitor 30 is in parallel with the operational amplifier output 18 and cannot introduce any signal charge error either.
Regarding switch timing, several rules must be observed. For the three pairs of switches 41, 42, 43, 44, 45 and 46, the two switches of the same pair can be switched on and off either simultaneously or with a delay between each other, that is, one switch can change its state earlier and the other switch can change its state later. Furthermore for the three switch configurations or three phases of operation, it is important to have non-overlap switch control, that is two pairs of switches cannot change state simultaneously. The switches 41, 42 of the first pair must be both open before closing the switches 43, 44 of the second pair. The switches 43, 44 of the second pair must be both open before closing the switches 45, 46 of the third pair. The switches 45, 46 of the third pair must be both open before closing the switches 41, 42 of the first pair, and so on for each successive cycle. The non-overlap switch control means that when transferring from one configuration to any other, short period of time must exist where no switch is closed.
The switch 44 used to place the operational amplifier in the voltage follower mode is normally closed throughout the second phase when the input voltage V2 has to be stored on the second capacitor 32, but it can be closed earlier than the start of the second phase and remain in closed state until the end of the second phase. In precise terms, the switch 44 can be closed as early as the start of the first phase but not later than the start of the second phase. The non-overlap rule does not apply here for the switch 44 of the second pair of switches, given that the switch 44 can remain closed during the transition from the first to the second switch configuration. Longer time of closed switch 44 brings an advantage of more precise amplifier settling.
It should be also noted that the pause time between the second phase and the third phase needs to be short as, during that time, the operational amplifier output can drift. If the pause time is long, the output voltage can reach the positive or negative supply terminal. Then, after switches 45, 46 are closed at the start of the third phase or third switch configuration, the operational amplifier output is still near one end of the supply voltage range, while the first capacitor 30 is charged. Consequently the node 51, and possibly the node 55, can get beyond the supply voltage range for a short time. Depending on switch implementation, such event can bring signal charge errors. To avoid this, the pause time needs to be set in such a way that the expected drift at the operational amplifier output during the pause is very small compared to the supply voltage.
In Figures 5 and 6 two conventional but variable and interchangeable capacitor designs are illustrated. Said capacitor designs can be used for the first capacitor 30 and/or the second capacitor 32. Figure 5 represents a plate capacitor 30 having a top plate 30b and a bottom plate 30a. Typically, the bottom plate capacitance is larger since the bottom plate 30a of the capacitor 30 is closer to the grounded substrate of the integrated circuit and typically designed to have larger area compared to the top plate 30b. In a sandwich architecture as illustrated in Figure 6, the top plate 30b turns into an inner plate which is effectively shielded and surrounded by the bottom plate. In particular, with the sandwich architecture as shown in Figure 6 the top plate parasitic capacitance can be minimized or even completely eliminated.
In Figure 7, a schematic diagram of an electronic device 64 implementing the switched capacitor differentiator 10 is schematically shown. The switched capacitor differentiator 10 as well as an optical sensor 60 are both driven by a clock generator 62. Upon receiving a clock signal, the switched capacitor differentiator 10 alternately or sequentially switches between the first, the second and the third switch configurations in a predetermined manner. Typically, in a first phase of the clock signal, the switched capacitor differentiator 10 is in the first switch configuration, in a second phase of the clock signal the differentiator is in a second switch configuration and in a subsequent third phase of the clock signal the switched capacitor differentiator 10 is in the third switch configuration before returning to the first phase again.
Synchronous with this switching, the optical sensor 60 provides varying input voltages V1, V2 at the input port 34 of the switched capacitor differentiator. The output port 36 of the switched capacitor differentiator 10 is connected to an analog-to-digital converter 66 which provides subsequent digital signal processing.
In Figure 8 only a very rough diagram of the method of operating the switched capacitor differentiator 10 is illustrated. In a first step 100, the switching structure 40 of the switched capacitor differentiator 10 is transferred into the first switch configuration. Thereafter, in step 102 the switching structure 40 is transferred into the second switch configuration. Thereafter, in step 104 the switching structure 40 is transferred into the third switch configuration. When arriving at the third switch configuration, a comparison between the consecutive input signals V1, V2 presented during the first and during the second phases at the input port 34 can be effectively conducted and a respective output signal can be transmitted to the analog-to-digital converter 66. After terminating the third step 104, the method typically returns to the first step 100 and may then transfer the switching structure from the third switch configuration back to the first switch configuration.
Two ways exist for assigning the three switch configurations to the three steps or phases of circuit operation. In one method, the first configuration is as shown in Figure 2, the second configuration as shown in Figure 3 and the third configuration as shown in Figure 4. In the alternative method, the first configuration is as shown in Figure 3, the second configuration as shown in Figure 2 and the third configuration as shown in Figure 4. Both methods can be modified in such a way that the operational amplifier is placed in the follower mode of operation throughout the first two phases of operation, that is, the switch connecting the operation amplifier output with its inverting input is closed from the start of the first phase until the end of the second phase. Several cycles with said three phases or three switch configurations can be successively repeated.
The present design is of particular advantage in that main sources of signal transfer errors in switched capacitor circuits, such as top and bottom plate parasitic capacitances, and operational amplifier offset can be substantially reduced or even entirely eliminated.

Claims

A method of operating a switched capacitor differentiator, which includes an operational amplifier (12) having an output (18), an inverting input (14) and a non-inverting input (16), an input port (34) and a reference voltage (20), a first capacitor (30) and a second capacitor (32), and a switching structure (40), which comprises three pairs of switches (41, 42, 43, 44, 45, 46) to alternately couple at least one of the first and the second capacitors (30, 32) with the operational amplifier (12), the input port (34) and with the reference voltage (20) in at least three different switch configurations,
wherein the method comprises determining a difference between two input signals, by:
- transferring the switching structure (40) in a first phase into a first switch configuration in which the first capacitor (30) is coupled between the input port (34) to receive the first input signal and the reference voltage (20), by closing a first switch (41) of a first pair connected to a top plate (30b) of the first capacitor (30) and the input port (34), and by closing a second switch (42) of the first pair connected to a bottom plate (30a) of the first capacitor (30) and the reference voltage (20),

- transferring the switching structure (40) in a second phase into a second switch configuration in which the second capacitor (32) is coupled between the input port (34) to receive the second signal and a node (54) connected to the operational amplifier output (18) and inverting input (14), by closing a third switch (43) of a second pair connected to a top plate (32b) of the second capacitor (32) and the input port (34), and by closing a fourth switch (44) of the second pair connected to the operational amplifier output (18) and the node (54) linked to the inverted input (14) and a bottom plate (32a) of the second capacitor (32), and

- transferring the switching structure (40) in a third phase into a third switch configuration in which the first and second capacitors (30, 32) are connected in series between the inverting input (14) and the operational amplifier output (18), by closing a fifth switch (45) of a third pair connected to the top plate (30b) of the first capacitor (30) and the top plate (32b) of the second capacitor (32), and by closing a sixth switch (46) of the third pair connected to the bottom plate (30a) of the first capacitor (30) and the operational amplifier output (18) wherein the first and second switches of the first pair are closed during the first switch configuration, while the other switches are designed to be open, wherein the third and fourth switches of the second pair are closed during the second switch configuration, while the other switches are designed to be open, and wherein the fifth and sixth switches of the third pair are closed during the third switch configuration, while the other switches are designed to be open.
A method of operating a switched capacitor differentiator, which includes an operational amplifier (12) having an output (18), an inverting input (14) and a non-inverting input (16), an input port (34) and a reference voltage (20), a first capacitor (30) and a second capacitor (32), and a switching structure (40), which comprises three pairs of switches (41, 42, 43, 44, 45, 46) to alternately couple at least one of the first and the second capacitors (30, 32) with the operational amplifier (12), the input port (34) and with the reference voltage (20) in at least three different switch configurations,
wherein the method comprises determining a difference between two input signals (V1, V2), by:
- transferring the switching structure (40) in a first phase into a first switch configuration in which the second capacitor (32) is coupled between the input port (34) to receive the second signal and a node (54) connected to the operational amplifier output (18) and inverting input (14), by closing a third switch (43) of a second pair connected to a top plate (32b) of the second capacitor (32) and the input port (34), and by closing a fourth switch (44) of the second pair connected to the operational amplifier output (18) and the node (54) linked to the inverted input (14) and a bottom plate (32a) of the second capacitor (32),

- transferring the switching structure (40) in a second phase into a second switch configuration in which the first capacitor (30) is coupled between the input port (34) to receive the first signal and the reference voltage (20), by closing a first switch (41) of a first pair connected to a top plate (30b) of the first capacitor (30) and the input port (34), and by closing a second switch (42) of the first pair connected to a bottom plate (30a) of the first capacitor (30) and the reference voltage (20), and

- transferring the switching structure (40) in a third phase into a third switch configuration in which the first and second capacitors (30, 32) are connected in series between the inverting input (14) and the operational amplifier output (18), by closing a fifth switch (45) of a third pair connected to the top plate (30b) of the first capacitor (30) and the top plate (32b) of the second capacitor (32), and by closing a sixth switch (46) of the third pair connected to the bottom plate (30a) of the first capacitor (30) and the operational amplifier output (18) wherein the third and fourth switches of the second pair are closed during the first switch configuration, while the other switches are designed to be open, wherein the first and second switches of the first pair are closed during the second switch configuration, while the other switches are designed to be open, and wherein the fifth and sixth switches of the third pair are closed during the third switch configuration, while the other switches are designed to be open.
The method according to claim 1, wherein for the passage from the first switch configuration to the second switch configuration, the first and second switches (41, 42) of the first pair are open before closing the third and fourth switches (43, 44) of the second pair, wherein for the passage from the second switch configuration to the third switch configuration, the third and fourth switches (43, 44) of the second pair are open before closing the fifth and sixth switches (45, 46) of the third pair, and wherein for the passage from the third switch configuration to the first switch configuration, the fifth and sixth switches (45, 46) of the third pair are open before closing the first and second switches (41, 42) of the first pair.
The method according to claim 2, wherein for the passage from the first switch configuration to the second switch configuration, the third and fourth switches (43, 44) of the second pair are open before closing the first and second switches (41, 42) of the first pair, wherein for the passage from the second switch configuration to the third switch configuration, the first and second switches (41, 42) of the first pair are open before closing the fifth and sixth switches (45, 46) of the third pair, and wherein for the passage from the third switch configuration to the first switch configuration, the fifth and sixth switches (45, 46) of the third pair are open before closing the third and fourth switches (43, 44) of the second pair.
The method according to any one of claims 1 or 2, wherein the fourth switch (44) of the second pair of switches, which is placed between the inverting input (14) of the operational amplifier (12) and its output (18), is and stays closed from the start of the first phase until the end of the second phase to keep the operational amplifier in voltage follower mode.
A switched capacitor differentiator configured to implement the method according to any one of preceding claims, said switched capacitor differentiator comprising :
- an operational amplifier (12) having an output (18), an inverting input (14) and a non-inverting input (16),

- an input port (34) and a reference voltage (20),

- a first capacitor (30) and a second capacitor (32), and

- a switching structure (40) comprising three pairs of switches (41, 42, 43, 44, 45, 46) to alternately couple at least one of the first and the second capacitors (30, 32) with the operational amplifier (12), the input port (34) and with the reference voltage (20) in order to transfer the switching structure (40) into the first, second or third switching configurations for determining the difference between two input signals (V1, V2), wherein the first pair of switches includes first and second switches (41, 42), with the first switch (41) connected to a top plate (30b) of the first capacitor (30) and the input port (34), with the second switch (42) connected to a bottom plate (30a) of the first capacitor (30) and the reference voltage (20), wherein the second pair of switches includes third and fourth switches (43, 44), with the third switch (43) connected to a top plate (32b) of the second capacitor (32) and the input port (34), and the fourth switch (44) connected to the operational amplifier output (18) and the node (54) linked to the inverted input (14) and a bottom plate (32a) of the second capacitor (32), and wherein the third pair of switches includes fifth and sixth switches (45, 46), with the fifth switch (45) connected to the top plate (30b) of the first capacitor (30) and the top plate (32b) of the second capacitor (32), and the sixth switch (46) connected to the bottom plate (30a) of the first capacitor (30) and the operational amplifier output (18).
The switched capacitor differentiator according to claim 6, wherein one pair of switches (41, 42 or 43, 44 or 45, 46) is designed to be closed at a time to transfer the switching structure (40) into one of first, second or third switch configurations, while residual pairs of switches (41, 42 or 43, 44 or 45, 46) are designed to be open.
The switched capacitor differentiator according to claim 6, wherein each pair of switches comprises two switches (41, 42, 43, 44, 45, 46) that are arranged to be switchable simultaneously or with a delay between each other.
The switched capacitor differentiator according to claim 6, wherein at least one of the first and second capacitors (30, 32), which includes a bottom plate (30a, 32a) and a top plate (30b, 32b), is connectable with the operational amplifier (12) by its bottom plate (30a, 32a).
The switched capacitor differentiator according to claim 6, wherein the bottom plate (30a) of the first capacitor (30) is connectable through one switch (46) of the switching structure (40) to the operational amplifier output (18).
The switched capacitor differentiator according to claim 6, wherein bottom plate (32a) of the second capacitor (30) is connected with the inverting input (14) of the operational amplifier (12).
The switched capacitor differentiator according to claim 6, wherein the first and the second capacitors (30, 32) are connectable in series with their top plates (30b, 32b).
The switched capacitor differentiator according to claim 6, wherein at least one of the first or second capacitors (30, 32) comprises a sandwich structure where a bottom or outer plate effectively surrounds or encloses a top or inner plate or where the top or inner plate or combination of plates is effectively shielded on both sides by the bottom or outer plate or combination of plates.
The switched capacitor differentiator according to claim 6, wherein at least one of the first or second capacitors (30, 32) comprises a shielded fringe or comb structure where a fringe or comb capacitor is enclosed or shielded by metal plates placed above and/or below said capacitor and electrically connected to one of the terminals of said fringe or comb capacitor.
An electronic device comprising a switched capacitor differentiator (10) according to claim 6.
The electronic device according to claim 15, further comprising a clock generator (62) and an optical sensor (60) both connected to the switched capacitor differentiator (10) to provide a sequence of input voltage signals at the input port (34) at consecutive clock pulses.