Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/90—Buffering arrangements
  • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools

Definitions

• the invention relates to a method and device within a data network for providing a dynamic scheduling of memory accesses and, in particular, to dynamic bandwidth allocation for a memory connected to a network device.
• Fig. 1 shows a diagram for illustrating the problem underlying the present invention.
• the diagram illustrates the bandwidth efficiency of data packets of variable size which are sent through a conventional digital data interface.
• the data bus is working at a frequency of 100MHz and comprises a data bus width of 256 bits.
• the inherent property of this exemplary digital interface is its minimum burst size of 256 bits. If the data packet size is an integer multiple of the minimum burst size then the bandwidth efficiency is 100% as shown in Fig. 1 . For example, if the data packet size is 32 bytes corresponding to 256 bits, the bandwidth efficiency is 100%.
• the bandwidth efficiency is also 100%.
• the data packet size DPS of a data packet DP is only one byte more than the minimum burst size, for example 33 bytes or 65 bytes, the bandwidth efficiency degrades considerably as illustrated in Fig. 1 .
• the bandwidth efficiency drops almost to 50% as shown in Fig. 1 and increases gradually until a bandwidth efficiency of 100% is reached at a data packet size of 64 bytes. Accordingly, there is a need for an apparatus and a method for providing a dynamic scheduling and bandwidth allocation which increases the bandwidth efficiency for data packets with variable data packet size.
• said apparatus is adapted to read egress data packets to be transmitted to a data link of said data network from the data memory slices of the data memory in read operations such that a misbalance between read operations from different data memory slices of said data memory can be minimized.
• the bursts comprise read bursts where data is read from a predetermined number of consecutive memory addresses.
• the bursts comprise also write bursts where data is written to a predetermined number of con- secutive memory addresses.
• the number of memory devices multiplied with the memory device width is equal to the memory width of the data memory.
• the memory width is equal to the bus width of a data bus of a digital interface.
• each memory buffer is adapted to store several bursts and comprises a memory buffer size which corresponds to a number of bursts stored in the respective memory buffer.
• a queue is provided having a memory buffer pointer managed by a queue manager of the apparatus.
• the memory size of the data memory is equal to the memory buffer size multiplied by the number of memory buffers.
• the invention further provides a method for dynamic scheduling of memory accesses to a data memory as a second aspect of the present invention.
• said method comprises the steps of:
• the store and forward network device is formed by a network router.
• the store and forward network device is formed by a network switch.
• Fig. 1 shows a diagram for illustrating the problem underlying the method and apparatus according to the present invention
• the data network device 1 as shown in Fig. 2 is adapted to write ingress data packets DPs received at its ingress data ports, from a data source of the data network into data memory slices DMS of the data memory 4 in write operations. Writing of ingress data packets DPs into data memory slices DMS of the data memory 4 is performed such that the received data packets DPs are evenly distributed in write operations between the different data memory slices DMS of the data memory 4.
• the number of bits in a data burst is the burst size BS of the data burst B and corresponds to a burst length (BL) multiplied with the slice size SS of a data memory slice DMS of the data memory 4:
• M is number of memory buffers MB
• MBS is the memory buffer size of a memory buffer.
• diagram 3A shows a data transport of the data packets DPs with slicing as performed by the apparatus and method according to the first and second aspect of the present invention.
• Fig. 3A three data packets DP1 , DP2, DP3 are transported via the digital interface, wherein the first data packet comprises 100 bytes corresponding to 800 bits so that 4 x 256 bits are transported consecutively via the data bus width of 256 bits.
• the second data packet DP2 comprises 50 bytes corresponding to 400 bits so that 2 x 256 bits have to be transported via the data bus width of 256 bits.
• the buffer size is 4 times the minimum data packet size DPSmin then in the worst case scenario of the data network 3 ⁇ 4 of the memory is wasted because no more than one data packet DP can be stored in a data buffer. Accordingly, the data memory is implemented with 4 times the actual traffic stored during RTT time.
• a slicing is performed, wherein a wide bus is divided to narrow busses that are independent from each other. This property is taken as an advantage in the case of slicing by choosing the slice where to store the received data packet DP.
• a dequeuing is performed wherein a data packet DP is read from the data memory 4 and forwarded to a data link within the data network. As opposed to the enqueuing operation the dequeuing operation specifies precisely which data packet DP is to be sent.
• the method and device according to the present invention with the partitioning of the data bus and memory into slices reduces waste of bandwidth. Balancing of the slices can be performed by mechanisms comprising a static slicing by design or a dynamic slicing during operation. With a static slicing the slice size SS is selected such that even the minimum data packet is spread over more than one slice. Data packets DP can be written such that the slices always toggle. With dynamic slicing it is possible to perform a write balance for read (W4R). When the mechanism detects that one slice is utilized more than the other, it inserts the write operation in unbalanced manner but in the opposite direction. Further, it is possible to perform a read balance for read (R4R). When the method detects that one slice is utilized more than the other it reads the next slice in an unbalanced manner but in the opposite direction. It does this by changing the order that is necessary as explained above.
• W4R write balance for read
• R4R read balance for read

Landscapes

• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Data Exchanges In Wide-Area Networks (AREA)

Applications Claiming Priority (1)

Publications (1)

Family

ID=46146846

Family Applications (1)

Country Status (3)

Family Cites Families (4)

• 2012
  • 2012-05-15 CN CN201280072778.2A patent/CN104272682A/zh active Pending
  • 2012-05-15 EP EP12722332.9A patent/EP2834950A1/de not_active Withdrawn
  • 2012-05-15 WO PCT/EP2012/059035 patent/WO2013170886A1/en active Application Filing

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events