EP2671251A2 - Method and device for electrically contact-connecting connection areas of two substrates - Google Patents

Method and device for electrically contact-connecting connection areas of two substrates

Info

Publication number
EP2671251A2
EP2671251A2 EP12714202.4A EP12714202A EP2671251A2 EP 2671251 A2 EP2671251 A2 EP 2671251A2 EP 12714202 A EP12714202 A EP 12714202A EP 2671251 A2 EP2671251 A2 EP 2671251A2
Authority
EP
European Patent Office
Prior art keywords
substrate
housing
pads
phase
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP12714202.4A
Other languages
German (de)
French (fr)
Inventor
Ghassem Azdasht
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pac Tech Packaging Technologies GmbH
Original Assignee
Pac Tech Packaging Technologies GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pac Tech Packaging Technologies GmbH filed Critical Pac Tech Packaging Technologies GmbH
Publication of EP2671251A2 publication Critical patent/EP2671251A2/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00Soldering, e.g. brazing, or unsoldering
    • B23K1/005Soldering by means of radiant energy
    • B23K1/0056Soldering by means of radiant energy soldering by means of beams, e.g. lasers, E.B.
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00Working by laser beam, e.g. welding, cutting or boring
    • B23K26/02Positioning or observing the workpiece, e.g. with respect to the point of impact; Aligning, aiming or focusing the laser beam
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/36Selection of non-metallic compositions, e.g. coatings, fluxes; Selection of soldering or welding materials, conjoint with selection of non-metallic compositions, both selections being of interest
    • B23K35/362Selection of compositions of fluxes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/64Manufacture or treatment of solid state devices other than semiconductor devices, or of parts thereof, not peculiar to a single device provided for in groups H01L31/00 - H10K99/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7501Means for cleaning, e.g. brushes, for hydro blasting, for ultrasonic cleaning, for dry ice blasting, using gas-flow, by etching, by applying flux or plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/751Means for controlling the bonding environment, e.g. valves, vacuum pumps
    • H01L2224/75101Chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/75261Laser
    • H01L2224/75263Laser in the upper part of the bonding apparatus, e.g. in the bonding head
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053Bonding environment
    • H01L2224/81054Composition of the atmosphere
    • H01L2224/81065Composition of the atmosphere being reducing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/8122Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/81224Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81905Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
    • H01L2224/81907Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909Post-treatment of the bump connector or bonding area
    • H01L2224/8191Cleaning, e.g. oxide removal step, desmearing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER

Definitions

  • the present invention relates to a method for electrically contacting pads of two substrates, wherein the first substrate with its second substrate facing pads is directly and electrically connected mechanically to the pads of the second substrate and the pads of the first substrate are provided with a Lotstoffön Ltd.
  • the first substrate may be a chip and the second substrate a carrier substrate, wherein the chip is contacted face-down with its chip pads against the substrate pads.
  • the invention relates to an apparatus for carrying out a second phase of the method according to the invention.
  • CONFIRMATION COPY facing pads and previously applied to the pads of the chip solder is mounted directly on the carrier substrate or a printed circuit board.
  • the solder agent application is reflowed during reflow soldering in a soldering oven and connects to the connection surfaces of the carrier substrate.
  • phase I the chip is positioned with its pads against the pads of the substrate and the chip pads and / or the substrate pads are provided with a LotstoffKU.
  • phase I the chip is applied with laser energy to the rear, in such a way that the solder is melted or fused at least to the extent to allow a fixation of the chip on the substrate, wherein at the same time a leveling or a uniform flattening of the chips on the chip pads . Plotted on the substrate pads Lotstoffträge takes place, so that a contact is made between all chip pads and substrate pads.
  • an arrangement of the component arrangement formed by the chip and the substrate takes place in a housing which is designed such that, during a reflow of the solder material application, the component arrangement is acted upon by a flux medium, in particular in gaseous form, which preferably consists of a nitrogen - / formic acid mixture consists.
  • a flux medium in particular in gaseous form, which preferably consists of a nitrogen - / formic acid mixture consists.
  • FIG. 1 shows a device for carrying out the method during phase II, after the above-described fixation of the chip on the substrate has previously been carried out in the phase I not shown here.
  • the component assembly is transferred to the position shown in FIG. 1, in which it is located below the housing 3 and then the housing 3 is lowered over the component assembly, as shown in Fig. 1.
  • the component arrangement formed from the chip 6 and the substrate 7 is located in an interior of a housing 3 sealed to the outside by a seal 2 relative to a support table 1.
  • the housing 3 has a wall which is otherwise substantially gas-tight in relation to the surroundings Inflow opening 8 and an outlet Flow opening 9, which allow a flow or flushing or flooding of the housing interior with a gaseous medium.
  • the substantially parallel to a rear side of the chip 6 arranged housing wall is formed by a glass plate or a transparent plate, which allows a backward loading of the chip with laser energy 5, wherein the laser radiation is focused according to the dimensions of the back of the chip 6 to a to avoid direct heat input or energy input into the substrate 7.
  • a reflow of the solder deposit 10 arranged between the chip connection surfaces and the substrate connection surfaces occurs during a flow through the housing interior with a flux gas, which in the present case is formed from a mixture of nitrogen and formic acid.
  • a nitrogen flow outside the housing 3 can be passed over a surface of a formic acid bath, so that the entrained fumes of formic acid mix with the nitrogen prior to the inflow into the housing 3.
  • a flow or purging of the interior of the housing 3 with a preferably pure protective gas flow, in which case preferably a nitrogen flow is used, for flux deposits, ie here in particular Precipitates of formic acid to avoid on the device assembly 6/7.
  • a nitrogen flow is used, for flux deposits, ie here in particular Precipitates of formic acid to avoid on the device assembly 6/7.
  • any gaseous flux which produces comparable effects can be used instead of the formic acid exemplified here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Laser Beam Processing (AREA)

Abstract

The present invention relates to a method for electrically contacting terminal faces of two substrates (6, 7), in particular of a chip (6) and of a carrier substrate (7). Furthermore, the invention relates to a device for performing a second phase of the method according to the invention. The method according to the invention takes place in two successive phases, wherein, in a first phase, the chip (6) is positioned with its terminal faces against terminal faces of the substrate (7) and laser energy (5) is applied to the chip (6) at the rear and, in a subsequent second phase, in a housing (3), a flux medium is applied and at the same time a reflow is performed by means of laser energy (5) being applied to the chip (6) at the rear, and a process of rinsing the housing interior is subsequently performed. The device according to the invention for performing a second phase of the method comprises a carrier table (1) and a housing (3), which together with a top side of the carrier table (1) forms a housing interior, in which the component arrangement is positioned, and also a laser light source (5), which is oriented in such a way that the laser radiation impinges on the first substrate (6) on the rear side.

Description

Verfahren und Vorrichtung zur elektrischen Kontaktierung von Anschlussflächen zweier Substrate  Method and device for electrical contacting of connection surfaces of two substrates
Die vorliegende Erfindung betrifft ein Verfahren zur elektrischen Kontaktierung von Anschlussflächen zweier Substrate, wobei das erste Substrat mit seinen dem zweiten Substrat zugewandten Anschlussflächen direkt mit den Anschlussflächen des zweiten Substrats elektrisch und mechanisch verbunden wird und die Anschlussflächen des ersten Substrats mit einem Lotmittelauftrag versehen sind. Insbesondere können zur Ausbildung eines Chipmoduls das erste Substrat ein Chip und das zweite Substrat ein Trägersubstrat sein, wobei der Chip Face-Down mit seinen Chipanschlussflächen gegen die Substratanschlussflächen kontaktiert wird. The present invention relates to a method for electrically contacting pads of two substrates, wherein the first substrate with its second substrate facing pads is directly and electrically connected mechanically to the pads of the second substrate and the pads of the first substrate are provided with a Lotmittelauftrag. In particular, to form a chip module, the first substrate may be a chip and the second substrate a carrier substrate, wherein the chip is contacted face-down with its chip pads against the substrate pads.
Weiterhin betrifft die Erfindung eine Vorrichtung zur Ausführung einer zweiten Phase des erfindungsgemäßen Verfahrens. Furthermore, the invention relates to an apparatus for carrying out a second phase of the method according to the invention.
Aus dem allgemeinen Stand der Technik sind Verfahren zur Direktmon- tage von Halbleiter-Chips auf Trägersubstraten bekannt. So existieren Verfahren, bei denen der ungehäuste Chip mit seinen dem Trägersubstrat Methods for the direct mounting of semiconductor chips on carrier substrates are known from the general state of the art. Thus, there are methods in which the unhoused chip with its the carrier substrate
BESTÄTIGUNGSKOPIE zugewandten Anschlussflächen und vorher auf die Anschlussflächen des Chips aufgetragenen Lotmitteln (Lotperlen) direkt auf dem Trägersubstrat oder einer Leiterplatte befestigt wird. Dabei wird der Lotmittelauftrag beim Reflow-Löten in einem LÖtofen wiederaufgeschmolzen und verbindet sich mit den Anschlussflächen des Trägersubstrats. Derartige Verfahren gestalten sich sowohl hinsichtlich ihres Ablaufs als auch in Bezug auf die dafür erforderlichen Vorrichtungen als sehr komplex. CONFIRMATION COPY facing pads and previously applied to the pads of the chip solder (solder balls) is mounted directly on the carrier substrate or a printed circuit board. In this case, the solder agent application is reflowed during reflow soldering in a soldering oven and connects to the connection surfaces of the carrier substrate. Such methods are very complex both in terms of their operation and in terms of the devices required for them.
Der vorliegenden Erfindung liegt daher die Aufgabe zu Grunde, einen Verfahrensablauf und eine Vorrichtung zu dessen Durchführung vorzu- schlagen, die den Prozess der elektrischen Kontaktierung von Anschlussflächen zweier Substrate, insbesondere von Halbleiterbauelementen mit Trägersubstraten, technisch vereinfacht und somit wirtschaftlicher gestaltet. It is therefore an object of the present invention to propose a method sequence and a device for carrying it out, which simplifies the process of electrically contacting terminal surfaces of two substrates, in particular semiconductor devices with carrier substrates, and thus makes them more economical.
Das erfindungsgemäße Verfahren erfolgt in zwei aufeinanderfolgenden Phasen, wobei in Phase I der Chip mit seinen Anschlussflächen gegen die Anschlussflächen des Substrats positioniert wird und die Chipanschlussflächen und/oder die Substratanschlussflächen mit einem Lotmittelauftrag versehen sind. In Phase I erfolgt eine rückwärtige Beaufschlagung des Chips mit Laserenergie, derart, dass das Lotmittel zumindest soweit aufgeschmolzen bzw. angeschmolzen wird, um eine Fixierung des Chips auf dem Substrat zu ermöglichen, wobei gleichzeitig eine Nivellierung bzw. eine gleichmäßige Abflachung der auf den Chipanschlussflächen bzw. den Substratanschlussflächen angeordneten Lotmittelaufträge erfolgt, so dass zwischen sämtlichen Chipanschlussflächen und Substrat- anschlussflächen ein Kontakt hergestellt ist. The inventive method is carried out in two successive phases, wherein in phase I, the chip is positioned with its pads against the pads of the substrate and the chip pads and / or the substrate pads are provided with a Lotmittelauftrag. In phase I, the chip is applied with laser energy to the rear, in such a way that the solder is melted or fused at least to the extent to allow a fixation of the chip on the substrate, wherein at the same time a leveling or a uniform flattening of the chips on the chip pads . Plotted on the substrate pads Lotmittelaufträge takes place, so that a contact is made between all chip pads and substrate pads.
Nachfolgend der Phase I erfolgt eine Anordnung der aus dem Chip und dem Substrat gebildeten Bauelementanordnung in einem Gehäuse, das so ausgebildet ist, dass während eines Reflows des Lotmaterialauftrags eine Beaufschlagung der Bauelementanordnung mit einem, insbesondere gasförmig ausgebildeten, Flussmittelmedium erfolgt, das vorzugsweise aus einem Stickstoff- / Ameisensäure-Gemisch besteht. Besonders vorteilhaft ist es dabei, wenn das Gehäuse so ausgebildet ist, dass eine Durchströmung des Gehäuseinnenraums mit dem Medium erfolgt, wobei gleichzeitig zur Beaufschlagung ein Reflow durch eine rückwärtige Beaufschlagung des Chips mit Laserenergie ähnlich wie in der zuvor geschilderten Phase I erfolgt. Subsequent to phase I, an arrangement of the component arrangement formed by the chip and the substrate takes place in a housing which is designed such that, during a reflow of the solder material application, the component arrangement is acted upon by a flux medium, in particular in gaseous form, which preferably consists of a nitrogen - / formic acid mixture consists. Especially It is advantageous if the housing is formed so that a flow through the housing interior is carried out with the medium, at the same time for applying a reflow by a backward loading of the chip with laser energy similar to that in the previously described phase I.
Nachfolgend der Beaufschlagung mit dem Flussmittelmedium, das insbesondere ein Aufbrechen einer möglicherweise in Phase I ausgebildeten Oxidschicht auf dem Lotmittelauftrag ermöglicht, erfolgt ein Spülvorgang des Gehäuseinnenraums, bei dem vorzugsweise ausschließ- lieh ein Schutzgas verwendet wird. Subsequent to the application of the flux medium, which in particular makes it possible to break up an oxide layer possibly formed in phase I on the solder agent application, a flushing process of the interior of the housing takes place, in which exclusively a protective gas is preferably used.
Weitere vorteilhafte Ausgestaltungsmerkmale ergeben sich aus der nachfolgenden Beschreibung und der Zeichnung, die eine bevorzugte Ausführungsform der Erfindung an Hand eines Beispiels erläutert. Further advantageous design features will become apparent from the following description and the drawing, which illustrates a preferred embodiment of the invention with reference to an example.
Es zeigt: Fig. 1 : eine schematische Darstellung der erfindungsgemäßen 1 shows a schematic representation of the invention
Vorrichtung.  Contraption.
In Fig. 1 ist eine Vorrichtung zur Ausführung des Verfahrens während Phase II dargestellt, nachdem zuvor in der hier nicht näher dargestellten Phase I die vorstehend beschriebene Fixierung des Chips auf dem Sub- strat erfolgt ist. Nach Durchführung der Phase I wird die Bauelementanordnung in die in der Fig. 1 dargestellte Position überführt, in der sie sich unterhalb des Gehäuses 3 befindet und anschließend wird das Gehäuse 3 über die Bauelementanordnung abgesenkt, wie in Fig. 1 dargestellt. In Phase II befindet sich die aus dem Chip 6 und dem Substrat 7 gebildete Bauelementanordnung in einem Innenraum eines nach außen hin durch eine Dichtung 2 gegenüber einem Trägertisch 1 abgedichteten Gehäuses 3. Das Gehäuse 3 weist in einer ansonsten zur Umgebung hin im Wesentlichen gasdichten Umwandung eine Zuströmöffnung 8 sowie eine Aus- Strömöffnung 9 auf, die eine Durchströmung bzw. Spülung oder Flutung des Gehäuseinnenraums mit einem gasförmigen Medium ermöglichen. Die im Wesentlichen parallel zu einer Rückseite des Chips 6 angeordnete Gehäusewandung ist durch eine Glasplatte bzw. eine transparente Platte gebildet, die eine rückwärtige Beaufschlagung des Chips mit Laserenergie 5 ermöglicht, wobei die Laserstrahlung entsprechend den Abmessungen der Rückseite des Chips 6 fokussiert ist, um einen unmittelbaren Wärmeeintrag bzw. Energieeintrag in das Substrat 7 zu vermeiden. In Folge der rückwärtigen Beaufschlagung des Chips 6 mit Laserstrahlung 5 erfolgt ein Reflow des zwischen den Chipanschlussflächen und den Substratanschlussflächen angeordneten Lotmittelauftrags 10 während einer Durchströmung des Gehäuseinnenraums mit einem Flussmittelgas, das im vorliegenden Fall aus einem Gemisch aus Stickstoff und Ameisensäure gebildet ist. Zur Ausbildung dieses Gasgemisches kann bei- spielsweise eine Stickstoffströmung außerhalb des Gehäuses 3 über eine Oberfläche eines Ameisensäurebades geleitet werden, so dass die mitgerissenen Dämpfe der Ameisensäure sich mit dem Stickstoff vor der Einströmung in das Gehäuse 3 vermischen. Nach erfolgtem Reflow, also insbesondere nach Beaufschlagung der Rückseite des Chips mit Laser- energie, erfolgt eine Durchströmung bzw. -Spülung des Innenraums des Gehäuses 3 mit einer vorzugsweise reinen Schutzgasströmung, wobei hier vorzugsweise eine Stickstoffströmung zum Einsatz kommt, um Flussmittelablagerungen, also hier insbesondere Ablagerungen von Ameisensäure, auf der Bauelementanordnung 6/7 zu vermeiden. Anstelle der hier beispielhaft erwähnten Ameisensäure kann grundsätzlich auch j edes gasförmige Flussmittel verwendet werden, das vergleichbare Wirkungen erzeugt. FIG. 1 shows a device for carrying out the method during phase II, after the above-described fixation of the chip on the substrate has previously been carried out in the phase I not shown here. After performing the phase I, the component assembly is transferred to the position shown in FIG. 1, in which it is located below the housing 3 and then the housing 3 is lowered over the component assembly, as shown in Fig. 1. In phase II, the component arrangement formed from the chip 6 and the substrate 7 is located in an interior of a housing 3 sealed to the outside by a seal 2 relative to a support table 1. The housing 3 has a wall which is otherwise substantially gas-tight in relation to the surroundings Inflow opening 8 and an outlet Flow opening 9, which allow a flow or flushing or flooding of the housing interior with a gaseous medium. The substantially parallel to a rear side of the chip 6 arranged housing wall is formed by a glass plate or a transparent plate, which allows a backward loading of the chip with laser energy 5, wherein the laser radiation is focused according to the dimensions of the back of the chip 6 to a to avoid direct heat input or energy input into the substrate 7. As a result of the backward loading of the chip 6 with laser radiation 5, a reflow of the solder deposit 10 arranged between the chip connection surfaces and the substrate connection surfaces occurs during a flow through the housing interior with a flux gas, which in the present case is formed from a mixture of nitrogen and formic acid. To form this gas mixture, for example, a nitrogen flow outside the housing 3 can be passed over a surface of a formic acid bath, so that the entrained fumes of formic acid mix with the nitrogen prior to the inflow into the housing 3. After the reflow, ie in particular after loading the rear side of the chip with laser energy, there is a flow or purging of the interior of the housing 3 with a preferably pure protective gas flow, in which case preferably a nitrogen flow is used, for flux deposits, ie here in particular Precipitates of formic acid to avoid on the device assembly 6/7. In principle, any gaseous flux which produces comparable effects can be used instead of the formic acid exemplified here.
Abweichend von der in der Fig. 1 beispielhaft erfolgten Darstellung der Bauelementanordnung als eine Kombination aus einem Chip 6 mit einem Substrat 7 ist es auch möglich, das erfindungsgemäße Verfahren aufNotwithstanding the example in FIG. 1 representation of the component arrangement as a combination of a chip 6 with a substrate 7, it is also possible to the inventive method
Wafer-Ebene durchzuführen, also zwei Wafer miteinander zu verbinden. Darüber hinaus ist es auch möglich, abweichend von der gewählten Darstellung nicht nur einen Chip mit einem Substrat zu verbinden bzw. in einem Reflow-Verfahren zwischen den Substratanschlussflächen und den Chipanschlussflächen angeordnete Lotmaterial aufträge bzw. -depots aufzuschmelzen, sondern auch Stapelanordnungen von Chips mit einer Mehrzahl von übereinander angeordneten Chips mit einem Substrat zu verbinden. Perform wafer level, so to connect two wafers together. In addition, it is also possible, notwithstanding the chosen representation, not only to connect a chip to a substrate or to reflow solder deposits or depots arranged in a reflow process between the substrate pads and the chip pads, but also stack arrangements of chips with one To connect a plurality of stacked chips to a substrate.

Claims

Patentansprüche claims
Verfahren zur elektrischen ontaktierung von Anschlussflächen zweier Substrate (6, 7), wobei das erste Substrat (6) mit seinen dem zweiten Substrat (7) zugewandten Anschlussflächen direkt mit den Anschlussflächen des zweiten Substrats (7) elektrisch und mechanisch verbunden wird und die Anschlussflächen des ersten Substrats (6) mit einem Lotmittelauftrag ( 10) versehen sind, und wobei der Verfahrensablauf in zwei aufeinanderfolgenden Phasen erfolgt, mit einer ersten Phase, in der Method for the electrical ontaktierung of pads of two substrates (6, 7), wherein the first substrate (6) with its the second substrate (7) facing pads electrically and mechanically connected directly to the pads of the second substrate (7) and the pads of the first substrate (6) are provided with a Lotmittelauftrag (10), and wherein the process sequence takes place in two successive phases, with a first phase, in the
- das erste Substrat (6) mit seinen Anschlussflächen gegen die Anschlussflächen des zweiten Substrats (7) positioniert wird und - The first substrate (6) is positioned with its pads against the pads of the second substrate (7) and
- eine rückwärtige Beaufschlagung des ersten Substrats (6) mit Laserenergie (5) derart erfolgt, dass das Lotmittel ( 10) zumindest soweit aufgeschmolzen wird, dass eine mechanische Fixierung des ersten Substrats (6) auf dem zweiten Substrat (7) ermöglicht wird und eine elektrische Kontaktierung der einander zugewandten Anschlussflächen erfolgt - A backward loading of the first substrate (6) with laser energy (5) takes place such that the solder (10) is at least melted so far that a mechanical fixation of the first substrate (6) on the second substrate (7) is made possible and a electrical contacting of the mutually facing connection surfaces takes place
und mit einer zweiten Phase, in der and with a second phase, in the
- in einem Gehäuseinnenraum eine Beaufschlagung der aus den Substraten (6, 7) gebildeten Bauelementeanordnung mit einem Flussmittelmedium erfolgt,  in an interior of the housing, the component arrangement formed by the substrates (6, 7) is exposed to a flux medium,
- gleichzeitig durch eine rückwärtige Beaufschlagung des ersten Substrats (6) mit Laserenergie (5) ein Wiederaufschmelzen des Lotmaterials ( 10) erfolgt und  - At the same time by a backward loading of the first substrate (6) with laser energy (5), a re-melting of the solder material (10) takes place and
- nachfolgend ein Spülvorgang des Gehäuseinnenraums durchgeführt wird.  - Subsequently, a purging of the housing interior is performed.
Verfahren nach Anspruch 1 , Method according to claim 1,
d adurch gek ennz ei chn et ,  characterized ,
dass das Flussmittelmedium einen gasförmigen Zustand aufweist. Verfahren nach Anspruch 2, the flux medium has a gaseous state. Method according to claim 2,
dadurch gekennzeichnet,  characterized,
dass das gasförmige Flussmittelmedium aus einem Stickstoff- Ameisensäure-Gemisch besteht.  the gaseous flux medium consists of a mixture of nitrogen and formic acid.
Verfahren nach Anspruch 3, Method according to claim 3,
dadurch gekennzeichnet,  characterized,
dass zur Ausbildung des gasförmigen Flussmittelmediums außerhalb des Gehäuseinnenraums eine Stickstoffströmung über eine Oberfläche eines Ameisensäurebades geleitet wird, so dass sich die mitgerissenen Dämpfe der Ameisensäure vor der Beaufschlagung der Bauelementeanordnung mit dem Stickstoff vermischen.  in that, to form the gaseous flux medium outside the interior of the housing, a nitrogen flow is conducted over a surface of a formic acid bath, so that the entrained fumes of the formic acid mix with the nitrogen before the component arrangement is acted upon.
Verfahren nach einem der Ansprüche 1 bis 4, Method according to one of claims 1 to 4,
dadurch gekennzeichnet,  characterized,
dass der Spülvorgang mit einer reinen Schutzgasströmung durchgeführt wird.  that the rinsing process is carried out with a pure protective gas flow.
Verfahren nach Anspruch 5, Method according to claim 5,
dadurch gekennzeichnet,  characterized,
dass die reine Schutzgasströmung eine Stickstoffströmung ist.  that the pure protective gas flow is a nitrogen flow.
Vorrichtung zur Ausführung einer zweiten Phase des Verfahrens nach Anspruch 1, mit einem Trägertisch (1) zur Auflage der aus den Substraten (6, 7) gebildeten Bauelementeanordnung, mit einem Gehäuse (3), das die Bauelementeanordnung umschließt und zusammen mit einer Oberseite des Trägertisches (1) einen Gehäuseinnenraum ausbildet, in dem die Bauelementeanordnung positioniert ist, und mit einer Laserlichtquelle (5), die derart ausgerichtet ist, dass die Laserstrahlung rückseitig auf das erste Substrat (6) trifft. Apparatus for carrying out a second phase of the method according to claim 1, comprising a support table (1) for supporting the component arrangement formed from the substrates (6, 7), with a housing (3) enclosing the component arrangement and together with an upper side of the support table (1) forming a housing interior in which the device assembly is positioned, and a laser light source (5) aligned such that the laser radiation hits the first substrate (6) at the back.
8. Vorrichtung nach Anspruch 7, 8. Apparatus according to claim 7,
dadurch gekennzeichnet, dass das Gehäuse (3) mit einer umlaufenden Dichtung (2) gegenüber der Oberseite des Trägertisches (1) versehen ist. characterized, the housing (3) is provided with a circumferential seal (2) opposite the top side of the support table (1).
. Vorrichtung nach Anspruch 7 oder 8, , Device according to claim 7 or 8,
dadurch gekennzeichnet,  characterized,
dass das Gehäuse (3) eine Zuströmöffnung (8) und eine Ausströmöffnung (9) aufweist, die eine Durchströmung des Gehäuseinnenraums mit einem Flussmittelmedium oder einem Spülmedium ermöglichen.  the housing (3) has an inflow opening (8) and an outflow opening (9), which allow a flow through the interior of the housing with a flux medium or a flushing medium.
0. Vorrichtung nach einem der Ansprüche 7 bis 9, 0. Device according to one of claims 7 to 9,
dadurch gekennzeichnet,  characterized,
dass eine im Wesentlichen parallel zu einer Rückseite des ersten Substrats (6) angeordnete Gehäusewandung (4) des Gehäuses (3) als transparente Platte (4) ausgebildet ist, um eine rückwärtige Beaufschlagung des ersten Substrats (6) mit Laserenergie (5) zu ermöglichen.  in that a housing wall (4) of the housing (3) arranged substantially parallel to a rear side of the first substrate (6) is designed as a transparent plate (4) in order to allow rearward application of laser energy (5) to the first substrate (6) ,
EP12714202.4A 2011-02-02 2012-01-30 Method and device for electrically contact-connecting connection areas of two substrates Withdrawn EP2671251A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102011010161 2011-02-02
PCT/DE2012/000068 WO2012103868A2 (en) 2011-02-02 2012-01-30 Method and device for electrically contact-connecting connection areas of two substrates

Publications (1)

Publication Number Publication Date
EP2671251A2 true EP2671251A2 (en) 2013-12-11

Family

ID=45954256

Family Applications (1)

Application Number Title Priority Date Filing Date
EP12714202.4A Withdrawn EP2671251A2 (en) 2011-02-02 2012-01-30 Method and device for electrically contact-connecting connection areas of two substrates

Country Status (6)

Country Link
US (1) US9649711B2 (en)
EP (1) EP2671251A2 (en)
JP (1) JP2014506012A (en)
KR (1) KR20140014156A (en)
CN (1) CN103477424B (en)
WO (1) WO2012103868A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104842069A (en) * 2014-02-13 2015-08-19 泰科电子(上海)有限公司 Laser welding system
EP3335334B1 (en) * 2015-08-13 2019-11-20 BAE Systems PLC Apparatus and method for communications management
US20180270833A1 (en) * 2015-09-25 2018-09-20 Gary David Boudreau Interference management for multiuser in-coverage device to device communication
FR3061801A1 (en) * 2017-01-12 2018-07-13 Commissariat Energie Atomique METHOD FOR ELECTRICAL CONNECTION BETWEEN AT LEAST TWO ELEMENTS
KR102052904B1 (en) 2018-03-27 2019-12-06 순천향대학교 산학협력단 Dice game apparatus for cognitive function test
DE102018114013A1 (en) * 2018-06-12 2019-12-12 Osram Opto Semiconductors Gmbh METHOD FOR FIXING A SEMICONDUCTOR CHIP ON A SURFACE, METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT AND SEMICONDUCTOR COMPONENT
KR102208069B1 (en) * 2019-01-29 2021-01-27 주식회사 프로텍 Laser Bonding Apparatus for Semi-conductor Chip in Nitrogen Atmosphere
US11651973B2 (en) 2020-05-08 2023-05-16 International Business Machines Corporation Method and apparatus of processor wafer bonding for wafer-scale integrated supercomputer

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH459316A (en) * 1965-06-18 1968-07-15 Ibm Method for the correct contact insertion of microminiaturized circuit elements in an integrated circuit
US3486223A (en) * 1967-04-27 1969-12-30 Philco Ford Corp Solder bonding
JPH06262743A (en) * 1993-03-11 1994-09-20 Seiko Epson Corp Bonding device
JPH0774209A (en) * 1993-09-01 1995-03-17 Nippondenso Co Ltd Manufacture of semiconductor device
DE69401108T2 (en) * 1993-09-28 1997-04-03 At & T Corp Surface mount soldering arrangement of integrated circuit packs without wire connections
WO2005005088A2 (en) * 2003-07-01 2005-01-20 Chippac, Inc. Method and apparatus for flip chip attachment by post-collapse re-melt and re-solidification of bumps
JP2005294823A (en) * 2004-03-11 2005-10-20 Hitachi Metals Ltd System and method for forming connection bumps of electronic component or the like, and device and method for bonding conductive balls
DE60219779T2 (en) * 2001-03-28 2007-12-27 Intel Corp., Santa Clara FLUX-FREE FLIP CHIP CONNECTION
US20080268571A1 (en) * 2007-04-24 2008-10-30 Samsung Techwin Co., Ltd. Apparatus for heating chip, flip chip bonder having the apparatus, and method for bonding flip chip using the same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4278867A (en) * 1978-12-29 1981-07-14 International Business Machines Corporation System for chip joining by short wavelength radiation
DE3737563A1 (en) * 1987-11-05 1989-05-18 Ernst Hohnerlein SOLDERING MACHINE
JPH0763861B2 (en) * 1989-10-23 1995-07-12 日産自動車株式会社 Panel parts welding equipment
JPH04186696A (en) * 1990-11-16 1992-07-03 Mitsubishi Electric Corp Bonding device
US5227604A (en) * 1991-06-28 1993-07-13 Digital Equipment Corporation Atmospheric pressure gaseous-flux-assisted laser reflow soldering
JPH0677638A (en) * 1992-08-21 1994-03-18 Matsushita Electric Ind Co Ltd Laser soldering equipment
DE4443822C2 (en) * 1994-12-09 1997-07-10 Telefunken Microelectron Laser soldering process
JP3285294B2 (en) * 1995-08-08 2002-05-27 太陽誘電株式会社 Circuit module manufacturing method
DE19751487A1 (en) * 1997-11-20 1999-06-02 Pac Tech Gmbh Method and device for the thermal connection of pads of two substrates
JP2000174059A (en) * 1998-12-09 2000-06-23 Matsushita Electric Ind Co Ltd Method of mounting electronic component
JP2001156436A (en) * 1999-11-30 2001-06-08 Ueda Japan Radio Co Ltd Method of soldering electronic part
TW570856B (en) * 2001-01-18 2004-01-11 Fujitsu Ltd Solder jointing system, solder jointing method, semiconductor device manufacturing method, and semiconductor device manufacturing system
JP3350529B1 (en) * 2001-06-07 2002-11-25 富士通株式会社 Solder joining apparatus and solder joining method
JP3404021B2 (en) 2001-01-18 2003-05-06 富士通株式会社 Soldering equipment
DE10213577B3 (en) * 2002-03-26 2004-02-19 Siemens Ag Process for simultaneous laser beam soldering
JP4522752B2 (en) * 2004-06-10 2010-08-11 三菱電機株式会社 Terminal joining method by soldering
US20090045444A1 (en) * 2007-08-13 2009-02-19 Holger Huebner Integrated device and circuit system
US7642135B2 (en) 2007-12-17 2010-01-05 Skyworks Solutions, Inc. Thermal mechanical flip chip die bonding
JP5378078B2 (en) * 2009-06-19 2013-12-25 株式会社東芝 Manufacturing method of semiconductor device
JP4901933B2 (en) * 2009-09-29 2012-03-21 株式会社東芝 Manufacturing method of semiconductor device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH459316A (en) * 1965-06-18 1968-07-15 Ibm Method for the correct contact insertion of microminiaturized circuit elements in an integrated circuit
US3486223A (en) * 1967-04-27 1969-12-30 Philco Ford Corp Solder bonding
JPH06262743A (en) * 1993-03-11 1994-09-20 Seiko Epson Corp Bonding device
JPH0774209A (en) * 1993-09-01 1995-03-17 Nippondenso Co Ltd Manufacture of semiconductor device
DE69401108T2 (en) * 1993-09-28 1997-04-03 At & T Corp Surface mount soldering arrangement of integrated circuit packs without wire connections
DE60219779T2 (en) * 2001-03-28 2007-12-27 Intel Corp., Santa Clara FLUX-FREE FLIP CHIP CONNECTION
WO2005005088A2 (en) * 2003-07-01 2005-01-20 Chippac, Inc. Method and apparatus for flip chip attachment by post-collapse re-melt and re-solidification of bumps
JP2005294823A (en) * 2004-03-11 2005-10-20 Hitachi Metals Ltd System and method for forming connection bumps of electronic component or the like, and device and method for bonding conductive balls
US20080268571A1 (en) * 2007-04-24 2008-10-30 Samsung Techwin Co., Ltd. Apparatus for heating chip, flip chip bonder having the apparatus, and method for bonding flip chip using the same

Also Published As

Publication number Publication date
KR20140014156A (en) 2014-02-05
CN103477424A (en) 2013-12-25
CN103477424B (en) 2016-12-14
WO2012103868A2 (en) 2012-08-09
WO2012103868A8 (en) 2012-11-15
US20140027418A1 (en) 2014-01-30
WO2012103868A3 (en) 2012-09-27
US9649711B2 (en) 2017-05-16
JP2014506012A (en) 2014-03-06

Similar Documents

Publication Publication Date Title
EP2671251A2 (en) Method and device for electrically contact-connecting connection areas of two substrates
DE69005104T2 (en) METHOD FOR SOLDERING WITHOUT FLUID.
DE69209793T2 (en) Soldering by heat conduction from a plasma
EP0427020B1 (en) Method and device for processing soldering joint partners
DE102015107724B4 (en) Method for producing a substrate arrangement, substrate arrangement, method for connecting an electronic component to a substrate arrangement and electronic component
EP1594165A2 (en) Method of electrically insulating a substrate for a power-device
WO2002056652A2 (en) Method for the production of an electronic component
CN109923951A (en) Soft soldering method
DE19911887C1 (en) Process for reflow soldering in a vapor phase vacuum soldering system
DE69204557T2 (en) Plasma based soldering.
WO2019030254A1 (en) Method for producing a power module
DE19541039A1 (en) Chip module e.g. for chip card
DE10004647C1 (en) Method for producing a semiconductor component with a multichip module and a silicon carrier substrate
EP3086361A2 (en) Method for producing a substrate arrangement with a prefixing means, corresponding substrate arrangement, method for connecting an electronic component with a substrate arrangement using a prefixing means formed on the electronic component and/or the substrate arrangement and an electronic component bonded with a substrate arrangement
DE3936955C1 (en) Plasma treating conductor plates for electronic elements - with process gas e.g. oxygen, hydrogen, fluoro-(chloro)-hydrocarbon, etc. before soldering
DE10303588B3 (en) Vertical assembly process for semiconductor devices
US7159758B1 (en) Circuit board processing techniques using solder fusing
DE2728330A1 (en) Fluxless soldering of contacts and/or semiconductor slices - using solder preforms which are aligned in a jig and heated
DE102004005361A1 (en) Process for the production of metallic interconnects and contact surfaces on electronic components
DE102007010882B4 (en) Method for producing a solder joint between a semiconductor chip and a substrate
DE102007004253A1 (en) Method and device for correcting faulty solder bump arrays
Thomas et al. Electronics Production Defects and Analysis
WO2023117397A1 (en) Method for producing a soldered connection between a carrier element and at least one electronic structural element, composite component and machine for producing a composite component
DE102009017692B4 (en) Process for the production of a low temperature contact for microelectronic structures
DE4225138A1 (en) Multichip module and method for its production

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20130814

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20160812

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20170127