EP2591552A1

EP2591552A1 - Data interface comprising intrinsically safe, integrated fault detection

Info

Publication number: EP2591552A1
Application number: EP11724410.3A
Authority: EP
Inventors: Natalja Kehl; Siegbert Steinlechner
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2010-07-07
Filing date: 2011-06-01
Publication date: 2013-05-15
Also published as: WO2012004065A1; KR20130093583A; CN102986141B; JP2013534108A; JP5638131B2; US9083331B2; US20130176050A1; CN102986141A; DE102010031030B3

Abstract

The invention relates to an intrinsically safe digital circuit (18) having at least one output signal (y₀, y₁) and at least four input signals (a₀, a₁, b₀, b₁) for determining a potential fault in the circuit (80) and/or in one of the input signals (a₀, a₁, b₀, b₁) thereof, at least four input signals (a₀, a₁, b₀, b₁) forming two dual-rail-inverted input signal pairs (a, b) and at least two output signals (y₀, y₁) forming a dual-rail-inverted output signal pair (y), characterized in that the output signal pair (y) transmits a piece of information which is the same as that from one of the input signal pairs (a) if the fault is not present.

Description

Description title

Data interface with intrinsically safe, integrated error detection state of the art

The invention is based on a circuit or a method according to the preamble of the independent claims. The invention relates to the detection of errors or disturbances in digital

Circuits.

Safety-critical applications require circuits that allow detection of a present permanent or transient fault. It is known from Parag K. Lala, "Self-Checking and Fault Tolerant Digital Design", Academic Press 2001, that an inverted doubled circuit is used for this purpose, and the outputs of this circuit are equal in the event of a fault

subsequent circuit an error is signaled. Furthermore, so-called intrinsically safe two-rail checkers are known, which use two outputs for signaling an error, so that a defect in one of the two own

Outputs is also detected. A conventional two-rail checker has in its basic form two pairs of input signals, each consisting of a signal and its inverted signal, and an output pair for

Error detection. A pair of signals is commonly referred to as a two-rail signal. A two-rail signal is considered valid if its

Single signals are not equal in the Boolean sense. Several such two-rail checkers can be combined in one circuit to check for more than two input signal pairs for errors. FIG. 2 shows an equivalent circuit diagram of a conventional two-rail checker 20 with a first input two-rail signal a, consisting of a

Input signal ai and an input signal a ₀ , and a second input two-rail signal b, consisting of an input signal bi and a

Input signal b ₀ , and an output two-rail signal y, consisting of an output signal yi and an output signal y ₀ .

1 shows a truth table 10 for a conventional two-rail checker 20. The truth table 10 shows the valid output signals y ₀ , yi for each valid input combination of the input signals a ₀ , ai, b ₀ , bi. The combinations shown in the truth table represent the error-free case, ie based on the output signal pair y can be closed to valid input signal pairs a, b. An invalid pair of input signals results in an invalid pair of output signals, which is detected by the equality of its individual output signals y ₀ and yi. Show the output signals y ₀ = 1 and yi = 0 or y ₀ = 0 and yi = 1, so there is no error, show the

Output signals y ₀ = 0 and yi = 0 or y ₀ = 1 and yi = 1 is an error.

3 illustrates an implementation of a two-rail checker 20. The two-rail checker 20 consists of four AND gates 30, 31, 32, 33 and two OR gates 34 and 35. On the basis of the output signals y ₀ , yi of a realized in this way two-rail checker can be detected both, whether the input signals a ₀ , ai, b ₀ , bi are valid, as well as whether the two-rail checker 20 operates correctly. In order to determine the accuracy of the two-rail checker 20, a test with the four valid input combinations is performed.

4 shows an error checking circuit 40 with four input signal pairs a, b, c, d. For this purpose, three two-rail checker 20, 20 ', 20 "connected in a cascade, and thus combined to form an output pair y.

Fig. 5 shows an example of a circuit 50, which consists of several

Signal processing blocks 51, 52, 53, 54 consists. An input signal S _in is processed in the circuit to an output signal S _ou t. Everyone

Signal processing block 51, 52, 53, 54 is connected to an error detection circuit Each of the error detection circuits 55, 56, 57, 58 has an output pair d, c, b, a. The output signal pairs d, c, b, a are in turn input signal pairs for the error checking circuit 40 and are combined into a single output pair y. The

Output signal y shows whether there is an error in the circuit 50 or not.

Disclosure of the invention

Advantages of the invention

The circuit according to the invention with the features of independent claim 1 has the advantage that the intrinsically safe circuit in addition to the function of error detection in error-free case transmits information of an input signal pair via an output signal pair. This opens up the possibility to fulfill with the circuit for error checking an additional function, namely the transmission of information, at the same time to the function of error detection.

The measures listed in the dependent claims are advantageous developments and improvements in the independent

Claim specified device possible.

It is particularly advantageous if the information carries a parity of one or more further output signals. In order for the subsequent device can also check whether an error has occurred behind the monitored circuit, which has disturbed the output signals.

Appropriately, a circuit having a plurality of input signals and / or output signals, which integrates an error detection, constructed so that internally identical sub-circuits are used. Such subcircuits can be inexpensively manufactured with a small number of CMOS transistors. Advantageous is the use of a data interface to the secure circuit, wherein an output signal has a word width of several bits, and the output signal pair in the non-error case, another bit supplies.

It is particularly advantageous if the further information as 1-bit information represents the parity of the multi-bit-wide output signal, since thus in a clocked circuit, an error check of a subsequent register is made possible.

Brief description of the drawings It shows

1 is a truth table of a known two-rail checker, which corresponds to the prior art,

2 is an equivalent circuit diagram for a known two-rail checker, which corresponds to the prior art,

Fig. 3 shows an embodiment of a secure circuit for a known

Two-rail checker, which corresponds to the state of the art,

4 shows a fused circuit for the reduction of four two-rail signals to a two-rail signal, which corresponds to the prior art,

Fig. 5 is a multi-level secure circuit with error detection in each

Stage that corresponds to the state of the art,

6 shows a truth table of a two-rail checker according to the invention, FIG. 7 shows an equivalent circuit diagram for a two-rail checker according to the invention, FIGS. 8-11 show various embodiments of a fused circuit of a two-rail checker according to the invention,

12 shows a fused circuit for reducing four two-rail signals to a two-rail signal according to the invention,

Fig. 13 is a secure circuit with output register, and

14-18 different embodiments of a secure circuit of a two-rail checker according to the invention.

Embodiments of the invention FIG. 7 shows an equivalent circuit diagram of a two-rail checker 70 according to the invention. The two-rail checker 70 according to the invention has a first

Input signal pair a, consisting of a first input signal a ₀ and a second input signal ai, and an input signal pair b, consisting of a third input signal b ₀ and a fourth input signal bi, and an output pair y, consisting of a first output signal y ₀ and a second output signal yi, up.

Referring now to Figure 6, a truth table 60 of a two-rail checker 70 of the present invention is valid, i.e., valid. error-free, cases shown. The truth table of a two-rail checker according to the invention shows for an input signal pair a and an input signal pair b all valid combinations and the occupancy of the output signal pair y. The truth table 60 shows that the

Output pair y reproduced the pair of input signals a. If there is no error, can via the input signal pair a, or one of its two

Input signals a ₀ or ai, an information to the output signal pair y, or to one of its two output signals y ₀ or yi, are transmitted. If, for example, the value 0 is desired to be transmitted from the input signal a ₀ to the output signal y ₀ by the two-rail checker 70 according to the invention, the input signal a _{0 is set} to 0 and the input signal ai is set to 1. In this case, the input signal a ₀ and the input signal ai must be different to give a valid input signal pair a. In the event of an error, the transmitted information is not evaluated because it is not ensured that the information is valid. The error case occurs when the output signal pair y is invalid, ie its two output signals y ₀ and yi are equal, ie y ₀ = yi = 1 or y ₀ = yi = 0. If the error occurs, the transmitted information can not be utilized ,

FIG. 8 shows an embodiment of a circuit 80 according to the invention for a two-rail checker 70 according to the invention, which is also known as

Subcircuit can be used. The circuit 80 consists of two conventional identical two-rail checkers 81, 82, two Input signal pairs a, b, and an output signal pair y. The

Signal inputs and signal outputs of the conventional two-rail checkers 81, 82 are specially connected such that, in the error-free case for occupancy of the input signal pairs a, b, the output signal pair y corresponds to the truth table 60. The circuit 80 for a two-rail checker 70 is intrinsically safe, as is a conventional two-rail checker.

Fig. 9 shows a further embodiment of an inventive

intrinsically safe circuit 900 for a two-rail checker 70 according to the invention. The circuit consists of the AND gates 90, 91, 92, 93, 98, 99 and the OR gates 94, 95, 96, 97.

10 shows a further embodiment of a device according to the invention

intrinsically safe circuit 1000 for a two-rail checker 70 according to the invention. The circuit consists of the AND gates 104, 105, 106, 107, the OR gates 100, 101, 102, 103, 108, 109 and the inverses 1080, 1090 ,

Fig. 11 shows a further embodiment of an inventive

intrinsically safe circuit 1100 for a two-rail checker 70 according to the invention. The circuit consists of the AND gates 110, 111, 112, 113, 118, 119, the OR gates 114, 115, 116, 117 and the inverses 1180, 1190 ,

Fig. 14 shows a further embodiment of a device according to the invention

intrinsically safe circuit 1400 for a two-rail checker 70 according to the invention. The circuit consists of the AND gates 144, 145, 146, 147 and the OR gates 140, 141, 142, 143, 148, 149.

Fig. 15 shows a further embodiment of a device according to the invention

intrinsically safe circuit 1500 for a two-rail checker 70 according to the invention. The circuit consists of the AND gates 150, 151, 156, 157, the OR gates 152, 153, 154, 155 and the inverses 158, 159.

Fig. 16 shows a further embodiment of a device according to the invention

intrinsically safe circuit 1600 for a two-rail checker according to the invention 70. The circuit consists of the AND gates 162, 163, 164, 165, the OR gates 160, 161, 166, 167 and the inverses 168, 169.

Fig. 17 shows a further embodiment of an inventive

intrinsically safe circuit 1700 for a two-rail checker according to the invention

70. The circuit consists of the AND gates 170, 171, 176, 177, the OR gates 172, 173, 174, 175 and the inverses 178, 179.

Fig. 18 shows a further embodiment of a device according to the invention

intrinsically safe circuit 1800 for a two-rail checker according to the invention

70. The circuit consists of the AND gates 182, 183, 184, 185, the OR gates 180, 181, 186, 187 and the inverses 188, 189.

FIG. 12 shows a circuit 120 of a cascade, which has two conventional two-rail checkers 121, 121 and a two-rail checker 123 according to the invention, and is used for error checking of four input signal pairs a, b, c, d. The two-rail checkers are combined in such a way that the input signal pair a is transmitted as additional information. Fig. 13 shows a fused circuit 130. The circuit 130 has a

Signal processing block 131 and a register 132 on. In the

Signal processing block 131 is an input signal S _in . The input signal S _in may consist of several input signals, that is to say any one

Have word width. The signal processing block has an output signal S _out and an output signal pair y. The output signal S _out may consist of several

Output signals exist, so have any word width. The

Output pair y consists of the two output signals y ₀ and yi. In the register 132, the output signal S _out and the output signal pair y lead into it. The register 132 has as output signal S _ou t 'and the

Output signal pair y 'on. The output signal S _ou t 'may consist of several

Output signals exist, so have any word width. The

Output signal pair y 'consists of the two output signals y ₀ ' and yi '. Furthermore, the register is provided with a clock T. The signal processing block 131 uses a two-rail checker according to the invention. The transmitted information in error-free case in the output signal pair y is the parity of the output signal S _out . A subsequent circuit can evaluate from the signal S _ou t 'and the output signal pair y', whether both the

Signal processing block 131 and the register 132 and the connections are working properly. This evaluates the subsequent circuit, z. B. a higher-level control device, first off whether the output signal pair y 'indicates a faulty case. This determines if the signal processing is working properly. Further, the subsequent circuit determines the parity of the output signal S _ou t 'and compares the parity with that by the

Output pair y 'transmitted parity. If the two parities are unequal, there is an error in the register or in the transfer.

Claims

claims

1. Intrinsically safe digital circuit (70, 80, 900, 1000, 1100, 1400, 1500, 1600, 1700, 1800, 123, 120, 131) with at least one output signal (S _ou t, yo, yi) and at least four input signals ( S _in, a _0, a i, b _0, bj for detecting a potential fault in the circuit (70, 80, 900, 1000, 1100, 1400, 1500, 1600, 1700, 1800, 123, 120, 131) and / or in one of its input signals (S _in , a ₀ , a i, b ₀ , bi), wherein at least four input signals (a ₀ , ai, b ₀ , bi) form two double-inverted input signal pairs (a, b) and at least two

Output signals (y ₀ , yi) form a two-pronged inverted output signal pair (y), characterized in that the output signal pair (y) a

Information similar to that of an input signal pair (a), if the error is not present.

An intrinsically safe digital circuit (70, 80, 900, 1000, 1100, 1400, 1500, 1600, 1700, 1800, 123, 120, 131) according to claim 1, wherein said circuit (70, 80, 900, 1000, 1100, 123, 120, 131) has one or more further output signals (S _ou t), which are not used for error detection, and the transmitted information is parity information of these further output signals (S _ou t).

An intrinsically safe digital circuit (70, 80, 900, 1000, 1100, 1400, 1500, 1600, 1700, 1800, 123, 120, 131) according to any one of claims 1-2, wherein the circuit (70, 80, 900, 1000, 1100, 123, 120, 131) internally at least one double-track inverted doubled intrinsically safe digital subcircuit (70, 80, 900, 1000, 1100, 1400, 1500, 1600, 1700, 1800, 123) for detecting an error in a first binary one Input signal pair (a) consisting of a first input signal (a ₀ ) and a second input signal (aj, and / or for detecting an error in a second binary input signal pair (b), consisting of a third input signal (b ₀ ) and fourth input signal ( bi), with a binary output pair (y) consisting of a first Output signal (y ₀ ) and a second output signal (yi), wherein in the error-free state, the second input signal (aj the inverted first

Indicates the input signal (aO) and the fourth input signal (bi) indicates the inverted third input signal (b ₀ ), the first output signal (y ₀ ) is equal to the first input signal (a ₀ ), the second output signal (yi) equals the second input signal (aO). aj and the second output signal (yi) is not equal to the first output signal (y ₀ ).

4. Data interface to an intrinsically safe digital circuit (70, 80, 900, 1000, 1100, 1400, 1500, 1600, 1700, 1800, 123, 120, 131) according to one of

Claims 1-3 with an output signal (S _ou t). having a word width of several bits, with an error signal (y) having a first bit (y ₀ ) and a second bit (yi), wherein an error of the protected circuit is signaled when the first bit (y ₀ ) of the Error signal and the second bit (yi) of the error signal are the same, characterized in that the first bit (y ₀ ) of the error signal or the second bit (yi) of the error signal, a 1-bit information from the secure circuit (70, 80, 900, 1000, 1100, 1400, 1500, 1600, 1700, 1800, 123, 120, 131) if no error is signaled.

The data interface of claim 4, wherein the 1-bit information is a

Parity information of the data output (S _ou t) is.

6. A method for detecting errors in a digital circuit (70, 80, 900, 1000, 1100, 1400, 1500, 1600, 1700, 1800, 123, 120, 131) and / or their

Input signals (a ₀ , ai, b ₀ , bi, S _in ), wherein at least four input signals (a ₀ , ai, b ₀ , bi) form two double-inverted input signal pairs (a, b), at least two output signals (y ₀ , yi) is a double-stranded inverted

Output pair (y) form, characterized in that the two output signals (y ₀ , yi) of the pair of output signals (y) are compared, wherein an error is detected when both output signals (y ₀ , yi) are equal, with no error is detected if both output signals (y ₀ , yi) are unequal, with information about the pair of output signals (y)

is transmitted if no error is detected.