EP2556633A1 - Verfahren und apparat zur fehlertoleranten zeitgesteuerten echtzeitkommunikation - Google Patents
Verfahren und apparat zur fehlertoleranten zeitgesteuerten echtzeitkommunikationInfo
- Publication number
- EP2556633A1 EP2556633A1 EP11719144A EP11719144A EP2556633A1 EP 2556633 A1 EP2556633 A1 EP 2556633A1 EP 11719144 A EP11719144 A EP 11719144A EP 11719144 A EP11719144 A EP 11719144A EP 2556633 A1 EP2556633 A1 EP 2556633A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- switch
- message
- fault
- tolerant
- switches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
- G06F11/2005—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication controllers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/004—Error avoidance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40169—Flexible bus arrangements
- H04L12/40176—Flexible bus arrangements involving redundancy
- H04L12/40182—Flexible bus arrangements involving redundancy by using a plurality of communication lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
- H04L49/1515—Non-blocking multistage, e.g. Clos
- H04L49/1523—Parallel switch fabric planes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
- H04L49/205—Quality of Service based
- H04L49/206—Real Time traffic
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
- H04L49/552—Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections
Definitions
- This invention relates to a method and apparatus for fault tolerant timed communication and establishing a fault tolerant global time of known precision in the communication system of a distributed real time computer system.
- a distributed real-time system consists of a number of computer nodes, the end systems in which the application software runs, and a generic communication system via which the messages of the end systems are interchanged.
- a global fault tolerant time base of good precision must be built so that the end systems can verify the time validity of the real-time information and perform synchronized distributed actions.
- the construction of a fault-tolerant global time base requires the execution of complex synchronization algorithms.
- the distributed error-tolerant clock synchronization is carried out according to the invention in the generic communication system, so that the end systems are supplied with the global time via a simple fault-tolerant master-slave synchronization (see textbook [5], chapter 3) can.
- a fault tolerant time is built up not in the end systems but in the communication system.
- a fault-tolerant switching unit ⁇ fault-tolerant switch which contains four independent switching units, each switching unit forming an Fault-Containment Unit (FCU). These four switching units share a fault-tolerant time base by exchanging messages. Two of the four switching units each form a switch pair, so that two switch pairs are contained in the fault-tolerant switching unit.
- Each of the two switching units of a switch pair periodically sends a synchronization message to a comparator, which forwards a synchronization message to an end system only if both received synchronization messages arrive almost simultaneously and are identical in content. Since there are two switch pairs in the fault-tolerant switching unit, this method tolerates any error in a switch pair.
- the object of the invention is achieved by a method for fault-tolerant clock synchronization and fault-tolerant timed real-time communication using a number of end systems and one or more fault-tolerant switches, each connected via at least two communication channels, each fault-tolerant switch containing a first and a second switch pair and where the first switch pair includes first and second switches, and where the second switch pair includes third and fourth switches, and where each of the four switches is connected via communication channels to the other three switches, and where the four switches have a known message-based switch internal fault tolerant
- Synchronization algorithm via the communication channels build an internal global fault-tolerant time base with known precision, and where a plurality of end systems can each be connected via a comparator associated with an end system to the two switch pairs, and where a first end system each have a copy of a message to be sent to an end system sends via the first communication channel to the first switch pair and the second communication channel to the second switch pair and where the first comparator sends the incoming message via a communication channel to the first switch and a communication channel to the second switch and where the third comparator the incoming message sends via a communication channel to the third switch and via a communication channel to the fourth switch and where the four switches transmit the incoming messages and if a message is addressed to the second end system the switches each send a copy of the message via communication channels to the second comparator associated with the second end system, and where the second comparator opens a time slot of duration D immediately after the arrival of the first time message if in this interval D no second copy of this message arrives at the second comparator the second comparator discards the message
- the two pairs of switches are arranged spatially separated.
- signed messages are used in the context of clock synchronization.
- a fault-tolerant switch adjusts its internal synchronized time to the time specified by the external synchronization message after receiving an external synchronization message.
- the switches only delay the messages by a few bit lengths and in the cut-through process they are sent to the comparators.
- the comparators only delay the messages by a few bit lengths and transmit them in the error-free-cut-through method to the end system.
- the end systems connected to a fault-tolerant switch send a mix of event-driven, bandwidth-limited, or timed messages.
- Planning information about the permitted temporal behavior of the end systems is loaded a priori into the switches, so that a switch can recognize a faulty temporal behavior of an end system.
- the a priori planning information to the switch is provided with an electronic signature of the transmitter.
- the a priori scheduling information can be changed dynamically during operation.
- the comparators are operated in a multiplex process.
- the different signal propagation times on the communication channels are compensated by the switch pairs.
- the messages produced and consumed by the end systems conform to the Ethernet standard.
- an apparatus for fault-tolerant time-controlled real-time communication comprising one or more fault-tolerant switches which are each connected via at least two communication channels, each fault-tolerant switch containing two switch pairs and where the first switch pair contains a first and a second switch and where the second switch pair includes a third and a fourth switch, and where each of the four switches is connected to the other three switches via the communication channels and where a plurality of end systems can each be connected to the two switch pairs via a dedicated comparator associated with the end system and where in this apparatus one or more of the above-mentioned process steps are realized.
- the present invention aims to build a fault tolerant global time in a fault tolerant communication system of a distributed real time system.
- a fault-tolerant message switching unit which consists of four independent switching units. These four independent switch units together build a fault-tolerant time.
- the end systems are connected to a fault-tolerant messaging unit via two independent fail-silent communication channels, so that even if a part of the fault-tolerant switching unit or a communication channel fails, the clock synchronization and the network connections remain upright.
- Fig. 1 shows an example of the structure of fault tolerant communication system consisting of several fault tolerant switching units.
- Fig. 2 shows the internal structure of a fault-tolerant switching unit.
- FIG. 1 shows a configuration with three fault-tolerant switching units 101, 102 and 103-referred to below as switches-and eight end systems 111 to 118.
- An end system is a node processor in which a part of a distributed real-time application runs.
- the three switches 101, 102 and 103 are interconnected by means of two respective communication channels 121 and 122, since the failure of a communication channel must be tolerated.
- Each switch e.g., the switch 101, includes two switch pairs, 151 and 152, each switch pair consisting of two switches.
- Each switch forms an autonomous Fault-Containment Unit (FCU).
- the end system 111 is connected via the communication channel 121 to the left switch pair 151 and via the communication channel 122 to the right switch pair 152 of the fault tolerant switch 101.
- the other end systems 112 to 118 are each connected via a communication channel to one switch pair and to the other communication channel with the other switch pair of a fault-tolerant switch.
- n the number of end systems which can be connected to a switch is not defined by this invention and depends on the specific structure of the fault-tolerant switch. Typically, n is between 8 and 16. For example, four end systems can be connected in the fault-tolerant switch 101 on the top and bottom sides. To simplify FIG. 2, only two end systems, the first end system 221 and the second end system 222 are listed in the fault tolerant switch 200.
- the fault-tolerant switch 200 consists of the two switch pairs 201 and 202.
- the first switch pair 201 consists of the two (not fault-tolerant) switches 211 and 213, the first switch 211 and the second switch 213 and the comparators 231 and 233, the first comparator 231 and the second comparator 233.
- the second switch pair 202 consists of the two (not fault tolerant) Switches 212 and 214, the third switch 212 and the fourth switch 214 and the comparators 232 and 234, the third comparator 232 and the fourth comparator 234th
- Each end system is thus assigned two comparators, one from the right and one from the left switch pair.
- the comparators can also be multiplexed so that there is one comparator with n inputs / outputs 251 or 252 to n end systems 221 or 222 in a switch pair.
- Each of the four switches 211, 212, 213, 214 forms an autonomous fault containment unit.
- the four switches 211, 212, 213, 214 are interconnected via communication channels 240, 241.
- the first switch 211 is connected either via the communication channels 240 to the horizontally and vertically adjacent switches, in this case the second switch 213 and the third switch 212, and via this to the fourth switch 214 the first switch 211 is connected via the communication channel 241 to the fourth switch 214 and via this, or corresponding communication channels 240, 241, with the other switches.
- the first switch 211 can be connected via communication channels 240 to the horizontally and vertically adjacent switches (second switch 213 and third switch 212) and connected to the fourth switch 214 via a communication channel 241.
- the communication channels 241 can be dispensed with (see below).
- the two connections 241 are not required.
- a selected switch eg, switch 103 in FIG. 1, or an end system equipped with a time source, eg a GPS time receiver, can specify an external time base to the connected switches. This is done via external synchronization messages that contain the external time. After receiving such an external synchronization message, the receiving fault-tolerant switch must adapt its internal clock synchronization to the externally specified time. If the external time source fails, the fault tolerant internal synchronization algorithm maintains global time.
- the external time source may also be used to dynamically adjust the clocking of the switches 211, 212, 213, 214 to the external time gear.
- this message is sent in parallel via the first communication channel 251 to the first comparator 231 in the first switch pair 201 and via the third communication channel 253 to the third comparator 232 in the second switch pair 202 Posted.
- the format of this message may conform to a given standard, eg the widely used Ethernet standard or the AFDX standard, but also any other standard that specifies that the address information must be included in the header of the message so that the messages from the switches 211, 212, 213 , 214 can be negotiated in a fast cut-through procedure.
- the messages may be timed, bandwidth limited, or event driven by the first end system 221.
- the switches 211, 212, 213, 214 may be provided a priori with scheduling information specifying the allowed times of sending a timed message from an end system. A timed message sent by the first end system 221 at a wrong time may then be detected and discarded by the switches 211, 212, 213, 214.
- the switches 211, 212, 213, 214 may be a priori supplied with scheduling information that specifies the allowed bandwidth of transmitting bandwidth limited messages. If the bandwidth limited messages sent by the first end system 221 exceed the allowed bandwidth, the switches 211, 212, 213, 214 may refuse to accept further messages.
- the a priori scheduling information sent to the switches 211, 212, 213, 214 prior to performing message transmission from a design system may be provided with an electronic signature so that the switches 211, 212, 213, 214 may check, Whether this information comes from an authorized design system.
- the scheduling information can be sent encrypted.
- the a priori scheduling information may be changed dynamically during operation by sending a new message with the new scheduling information and the time from when that new scheduling information is to be applied.
- a message arriving from the first communication channel 251 in the first comparator 231 is relayed by the first comparator 231 via the communication channel 242 to the first switch 211 and via the communication channel 243 to the second switch 213 for switching. Because of the address information contained in the header of a message, the message is forwarded from the first switch 211 via the communication channel 244 and from the second switch 213 via the communication channel 245 to the addressed comparator in the example to the second comparator 233-. As soon as the message addressed in time to the second comparator 233 arrives at the second comparator 233 from one of the two switches 211 or 213, the second comparator 233 opens a time window of the duration predefined a priori.
- the comparator discards the first message, and subsequently the second message (if it ever arrives). If, within this time window D, the second message arrives from the other switch of the first switch pair 201, then the second comparator 233 compares the two Messages bitwise and forwards them immediately via the second communication channel 252 to the addressed (second) end system 222 on. This comparison of the two messages can be done in the error-free-cut-through method, ie the incoming bit streams are only briefly delayed in the second comparator 233, continuously compared and forwarded immediately if the bit comparison is correct. In the event of an error, the bit stream to the (second) end system 222 is aborted. Since each message contains a CRC field, the (second) end system 222 can detect and discard an aborted message.
- the duration of the necessary delay of a message in the second comparator 233 depends on the precision P of the clock synchronization, which is essentially determined by the duration of the synchronization period and the quality of the oscillators used.
- the number of bits to be stored in the comparator depends on the precision P and the bandwidth of the data transmission.
- the comparators 231, 232, 233, 234 are designed so that no complete message can be stored in a comparator and no comparator has the information on how to form a correct CRC field of a message. Thus, it is highly unlikely that a failed comparator may generate a syntactically correct but contentually incorrect message or may send a syntactically correct but substantively incorrect message to a different time than that produced by the first 211 or third switch 212.
- a syntactically correct message is thus forwarded to the (second) end system 222 via the second communication channel 252 only if all four subsystems 231, 211, 213 and 233 function without errors and the message transport via the channels 251, 242, 243 , 244, 245, and 252 runs without errors.
- the first switch pair 201 thus realizes the fail-silent abstraction on the second communication channel 252: it either produces messages which are correct in the range of values and in the time domain or it does not produce any messages.
- the second switch pair 202 functions analogously to the first switch pair 201.
- the fault-tolerant switch 200 In addition to the messages received from the end systems, the fault-tolerant switch 200 periodically sends two internally generated synchronization messages to all connected end systems, almost simultaneously a synchronization message from the left (first) switch pair 201 via the first 251 and second communication channel 252 and a second synchronization message from the right ( second) switch pair via the third 253 and fourth communication channel 254 is sent.
- the time of arrival of a synchronization message at an end system corresponds to that time which is contained in the data field of the synchronization message. Since the signal propagation times on the communication channels 251, 252, 253, 254 are different due to the different length of these signal propagation times on the communication channels, a correction of the arrival time, a synchronization message to the end system may be required. This correction can be done either in the end system or in the switch pairs 201, 202.
- the (second) end system 222 thus receives two correct synchronization messages, one via the (second) communication channel 252 and the other via the (fourth) communication channel 254, the arrival times of which differ at most by the precision P. If in a switch pair a Error occurs, the (second) end system 222 still receives a correct synchronization message.
- the present invention allows standard components, i.e., components that do not have the self-checking capability, to construct a fault tolerant time base and a fault tolerant switch that tolerates any fault in a fault containment unit (FCU).
- FCU fault containment unit
- the following subsystems are error containment units: the four switches 211, 212, 213, 214 and the four comparators 231, 232, 233, 234.
- Particular attention is paid to the last subsystem, the comparator, prior to issuing a message to the end system is arranged.
- the construction measures described can preclude a faulty comparator from producing a syntactically correct but contentually incorrect message, even though the comparator itself does not have to be executed as a self-checking checker.
- the clock synchronization algorithm only needs to be developed, tested and certified once and can be used in a variety of applications.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Computer Security & Cryptography (AREA)
- Hardware Redundancy (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Small-Scale Networks (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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ATA557/2010A AT509700B1 (de) | 2010-04-07 | 2010-04-07 | Verfahren und apparat zur fehlertoleranten zeitgesteuerten echtzeitkommunikation |
PCT/AT2011/000167 WO2011123877A1 (de) | 2010-04-07 | 2011-04-07 | Verfahren und apparat zur fehlertoleranten zeitgesteuerten echtzeitkommunikation |
Publications (2)
Publication Number | Publication Date |
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EP2556633A1 true EP2556633A1 (de) | 2013-02-13 |
EP2556633B1 EP2556633B1 (de) | 2014-01-08 |
Family
ID=44461871
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP11719144.5A Active EP2556633B1 (de) | 2010-04-07 | 2011-04-07 | Verfahren und apparat zur fehlertoleranten zeitgesteuerten echtzeitkommunikation |
Country Status (6)
Country | Link |
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US (1) | US9063837B2 (de) |
EP (1) | EP2556633B1 (de) |
JP (1) | JP5593530B2 (de) |
CN (1) | CN103039046B (de) |
AT (1) | AT509700B1 (de) |
WO (1) | WO2011123877A1 (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AT509700B1 (de) | 2010-04-07 | 2019-05-15 | Tttech Computertechnik Ag | Verfahren und apparat zur fehlertoleranten zeitgesteuerten echtzeitkommunikation |
AT512290B1 (de) | 2011-12-19 | 2013-07-15 | Fts Computertechnik Gmbh | Verfahren zur zeitrichtigen beobachtung von ttethernet nachrichten |
US20130208630A1 (en) * | 2012-02-15 | 2013-08-15 | Ge Aviation Systems Llc | Avionics full-duplex switched ethernet network |
AT512742A1 (de) * | 2012-04-11 | 2013-10-15 | Fts Computertechnik Gmbh | Verfahren und Verteilereinheit zur zuverlässigen Vermittlung von Synchronisationsnachrichten |
JP6152425B2 (ja) * | 2012-11-16 | 2017-06-21 | エフティーエス コンピューターテクニク ジーエムビーエイチ | リアルタイムメッセージの送信方法およびリアルタイムメッセージを送信するためのコンピュータネットワーク |
US10241858B2 (en) * | 2014-09-05 | 2019-03-26 | Tttech Computertechnik Ag | Computer system and method for safety-critical applications |
WO2016049670A1 (de) * | 2014-10-01 | 2016-04-07 | Fts Computertechnik Gmbh | Verteiltes echtzeitcomputersystem und zeitgesteuerte verteilereinheit |
FR3030126B1 (fr) * | 2014-12-10 | 2017-01-13 | Thales Sa | Systeme de transmission d'information avioniques |
CN104618087B (zh) * | 2015-01-30 | 2018-07-17 | 国家电网公司 | 一种广域电网pmu数据时延精确测量的方法 |
US10019292B2 (en) | 2015-12-02 | 2018-07-10 | Fts Computertechnik Gmbh | Method for executing a comprehensive real-time computer application by exchanging time-triggered messages among real-time software components |
EP3468115B1 (de) * | 2017-10-09 | 2020-06-17 | TTTech Computertechnik AG | Verfahren zur verbesserung der erreichbarkeit von echtzeit-computernetzwerken |
CN110493040B (zh) * | 2019-08-02 | 2022-06-14 | 中国航空无线电电子研究所 | 航空机载网络的设计方法和装置 |
EP3902166B1 (de) * | 2020-04-21 | 2022-03-23 | TTTech Computertechnik Aktiengesellschaft | Fehlertoleranter zeitserver für ein echtzeitcomputersystem |
EP3902206B1 (de) * | 2020-04-21 | 2022-02-16 | TTTech Computertechnik Aktiengesellschaft | Fehlertolerante verteilereinheit und verfahren zur bereitstellung einer fehlertoleranten globalen zeit |
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DE59007068D1 (de) * | 1990-04-27 | 1994-10-13 | Siemens Ag | Verfahren und Schaltungsanordnung zur Reduzierung des Verlustes von Nachrichtenpaketen, die über eine Paketvermittlungseinrichtung übertragen werden. |
US5269016A (en) * | 1990-09-24 | 1993-12-07 | Charles Stark Draper Laboratory, Inc. | Byzantine resilient fault tolerant shared memory data processing system |
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AT411948B (de) | 2002-06-13 | 2004-07-26 | Fts Computertechnik Gmbh | Kommunikationsverfahren und apparat zur übertragung von zeitgesteuerten und ereignisgesteuerten ethernet nachrichten |
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AT509700B1 (de) | 2010-04-07 | 2019-05-15 | Tttech Computertechnik Ag | Verfahren und apparat zur fehlertoleranten zeitgesteuerten echtzeitkommunikation |
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2010
- 2010-04-07 AT ATA557/2010A patent/AT509700B1/de active
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2011
- 2011-04-07 JP JP2013502952A patent/JP5593530B2/ja active Active
- 2011-04-07 US US13/639,456 patent/US9063837B2/en active Active
- 2011-04-07 CN CN201180018153.3A patent/CN103039046B/zh active Active
- 2011-04-07 EP EP11719144.5A patent/EP2556633B1/de active Active
- 2011-04-07 WO PCT/AT2011/000167 patent/WO2011123877A1/de active Application Filing
Non-Patent Citations (1)
Title |
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Also Published As
Publication number | Publication date |
---|---|
WO2011123877A1 (de) | 2011-10-13 |
EP2556633B1 (de) | 2014-01-08 |
CN103039046A (zh) | 2013-04-10 |
JP2013531402A (ja) | 2013-08-01 |
AT509700B1 (de) | 2019-05-15 |
US9063837B2 (en) | 2015-06-23 |
JP5593530B2 (ja) | 2014-09-24 |
US20130086432A1 (en) | 2013-04-04 |
AT509700A1 (de) | 2011-10-15 |
CN103039046B (zh) | 2015-07-22 |
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