EP2494856A1 - Dépôt de métal - Google Patents

Dépôt de métal

Info

Publication number
EP2494856A1
EP2494856A1 EP10830472A EP10830472A EP2494856A1 EP 2494856 A1 EP2494856 A1 EP 2494856A1 EP 10830472 A EP10830472 A EP 10830472A EP 10830472 A EP10830472 A EP 10830472A EP 2494856 A1 EP2494856 A1 EP 2494856A1
Authority
EP
European Patent Office
Prior art keywords
substrate
current
voltage
dielectric material
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10830472A
Other languages
German (de)
English (en)
Inventor
Lex Kosowsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shocking Technologies Inc
Original Assignee
Shocking Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shocking Technologies Inc filed Critical Shocking Technologies Inc
Publication of EP2494856A1 publication Critical patent/EP2494856A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00—Processes for servicing or operating cells for electrolytic coating
    • C25D21/12—Process control or regulation
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • C25D5/611—Smooth layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0215—Metallic fillers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details
    • H05K2201/073—High voltage adaptations
    • H05K2201/0738—Use of voltage responsive materials, e.g. voltage switchable dielectric or varistor materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/105—Using an electrical field; Special methods of applying an electric potential
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31678—Of metal

Definitions

  • This invention relates to the field of current-carrying devices and components.
  • the invention relates to a current-carrying device in concert with a voltage switchable dielectric material.
  • Current-carrying structures are generally fabricated by subjecting a substrate to a series of manufacturing steps. Examples of such current- carrying structures include printed circuit boards, printed wiring boards, backplanes, and other micro-electronic types of circuitry.
  • the substrate is typically a rigid, insulative material such as epoxy-impregnated glass fiber laminate.
  • a conductive material, such as copper, is patterned to define conductors, including ground and power planes.
  • Some prior art current-carrying devices are manufactured by layering a conductive material over a substrate.
  • a mask layer is deposited on the conductive layer, exposed, and developed. The resulting pattern exposes select regions where conductive material is to be removed from the substrate.
  • the conductive layer is removed from the select regions by etching.
  • the mask layer is subsequently removed, leaving a patterned layer of the conductive material on the surface of the substrate.
  • an electroless process is used to deposit conductive lines and pads on a substrate.
  • a plating solution is applied to enable conductive material to adhere to the substrate on selected portions of the substrate to form patterns of conductive lines and pads.
  • substrate devices sometimes employ multiple substrates, or use both surfaces of one substrate to include componentry and circuitry. The result in either case is that multiple substrate surfaces in one device need to be interconnected to establish electrical communication between components on different substrate surfaces.
  • sleeves or vias provided with conductive layering extend through the substrate to connect the multiple surfaces.
  • vias extend through at least one substrate to interconnect one surface of that substrate to a surface of another substrate. In this way, an electrical link is established between electrical components and circuitry on two surfaces of the same substrate, or on surfaces of different substrates.
  • via surfaces are plated by first depositing a seed layer of a conductive material followed by an electrolytic process.
  • adhesives are used to attach conductive material to via surfaces. In these devices, the bond between the vias and conductive material is mechanical in nature.
  • voltage switchable dielectric materials Certain materials, referred to below as voltage switchable dielectric materials, have been used in prior art devices to provide over-voltage protection. Because of their electrical resistance properties, these materials are used to dissipate voltage surges from, for example, lightning, static discharge, or power surges. Accordingly, voltage switchable dielectric materials are included in some devices, such as printed circuit boards. In these devices, a voltage switchable dielectric material is inserted between conductive elements and the substrate to provide over-voltage protection.
  • Various embodiments include a method for fabricating a current- carrying formation.
  • Several embodiments address fabricating formations on or with a Voltage Switchable Dielectric Material (VSDM).
  • VSDM may include a characteristic voltage, whose magnitude defines a threshold below which the VSDM is substantially electrically insulative, and above which the VSDM is substantially electrically conductive.
  • a method may include providing a conductive backplane, forming a layer of VSDM on at least a portion of the conductive backplane, and depositing an electrically conductive material on at least a portion of the voltage switchable dielectric material.
  • a conductive backplane may include a metal, a conductive compound, a polymer and/or other materials.
  • a conductive backplane may include a substrate.
  • a conductive backplane may also act as a substrate.
  • a substrate may be removed after deposition.
  • Deposition may include electrochemical deposition, and may include creating a voltage greater than a characteristic voltage associated with the VDSM, causing current to flow and deposition and/or etching to occur.
  • a package e.g., a polymer
  • a VSDM voltage-driven VSDM
  • components e.g., a substrate
  • Removal may be facilitated by a decohesion layer disposed between two materials whose separability be desired.
  • a method comprises providing a VSDM, depositing an intermediate layer on at least a portion of the VSDM, and depositing a material on at least a portion of the intermediate layer.
  • An intermediate layer may improve adherence, mechanical properties, electrical properties, and the like.
  • An intermediate layer may provide for a controlled release or decohesion.
  • An intermediate layer may include a diffusion barrier.
  • an intermediate layer is deposited on a VSDM, and an additional material (e.g., a polymer and/or electrical conductor) is deposited on at least a portion of the intermediate layer.
  • An insulating material e.g., a polymer
  • a conductor may be deposited on an intermediate layer.
  • An intermediate layer may be formed using electrografting.
  • a method comprises providing a substrate having a VSDM and depositing a current-carrying material on at least a portion of the VSDM.
  • a package may be attached to at least a portion of the VSDM and/or at least a portion of the current-carrying formation.
  • a package may include a polymer.
  • a package and/or a VSDM may include one or more vias, which may be filled. Certain embodiments include a plurality of electrical connections through a package.
  • a method includes applying a contact mask to a surface of a VSDM.
  • a contact mask may be removably attached such that it seals or otherwise blocks a first portion of the VSDM from deposition, and exposes a second portion of the VSDM for deposition of a material (e.g., a current-carrying formation).
  • a material e.g., a current-carrying formation
  • a contact mask may include an insulating foot that contacts a surface of the VSDM and demarcates or defines one or more portions.
  • a contact mask may also include an electrode, typically separated from the surface by the insulating foot.
  • a sandwich of the VSDM and contact mask may be immersed in (or otherwise exposed to) a solution that provides a source of ions associated with a desired material to be deposited.
  • a voltage greater than the characteristic voltage of the VSDM may be created, that causes deposition of the desired material in or on the exposed portions of the VSDM.
  • a conductor deposited on a VSDM may be etched, typically using a mask, in a fashion that removes the conductor from certain regions of the VSDM.
  • the unetched regions may form current- carrying formations according to certain embodiments.
  • a VSDM may include regions having different characteristic voltages. Certain embodiments include a VSDM having first and second regions. A first region may have a first characteristic voltage, and a second region may have a second characteristic voltage. According to different processing conditions, a material may be deposited on either of the first and second regions, or both regions. In some cases, deposition on both regions may be followed by a preferential etching of the deposited material from one region, but not the other region. In some embodiments, current-carrying formations are formed on different regions independently of each other.
  • FIG. 1 illustrates a single-sided substrate device including a voltage switchable dielectric material, under an embodiment of the invention.
  • FIG. 2 illustrates electrical resistance characteristics of a voltage switchable dielectric material, under an embodiment of the invention.
  • FIGs. 3A-3F show a flow process for forming the device of FIG. 1.
  • FIG. 3A illustrates a step for forming a substrate of voltage switchable dielectric material.
  • FIG. 3B illustrates a step of depositing a non-conductive layer on the substrate.
  • FIG.3C illustrates a step of patterning a non-conductive layer on the substrate.
  • FIG. 3D illustrates a step of forming a conductive layer using the pattern of the non-conductive layer.
  • FIG. 3E illustrates a step of removing the non-conductive layer from the substrate.
  • FIG. 3F illustrates the step of polishing the conductive layer on the substrate.
  • FIG. 4 details a process for electroplating current-carrying structures on a substrate formed from voltage switchable dielectric material, under an embodiment of the invention.
  • FIG. 5 illustrates a dual-sided substrate device formed from voltage switchable dielectric material and including a via interconnecting current- carrying formations on both sides of the substrate, under an embodiment of the invention.
  • FIG. 6 illustrates a flow process for forming the device of FIG. 5.
  • FIG. 7 illustrates a multi-layered substrate device including substrates formed from voltage switchable dielectric material, under an embodiment of the invention.
  • FIG. 8 illustrates a process for forming the multi-substrate device of FIG. 7.
  • FIG. 9 illustrates an exemplary waveform for a pulse plating process according to an embodiment of the invention.
  • FIG. 10 illustrates an exemplary waveform for a reverse pulse plating process according to an embodiment of the invention.
  • FIG. 11 illustrates a segment of an interior structure of a connector, the segment having exposed pin receptacles according to an embodiment of the invention.
  • FIG. 12 shows a perspective view of a portion of the segment of FIG. 11 with a mask disposed thereon, according to an embodiment of the invention.
  • FIG. 13 illustrates certain embodiments associated with intermediate layers.
  • FIG. 14 illustrates an exemplary method and structure that
  • FIG. 15 is a diagrammatic illustration of attaching a package, according to some embodiments.
  • FIGS. 16A and 16B illustrate cross section and perspective views (respectively) of a removable contact mask, according to certain
  • FIG. 17 illustrates deposition of a current-carrying material to form a current-carrying formation, according to certain embodiments.
  • FIG. 18 illustrates a current-carrying formation fabricated using an etching process, according to certain embodiments.
  • FIG. 19 illustrates a voltage switchable dielectric material (VSDM) 1910 having regions with different characteristic voltages, according to certain embodiments.
  • VSDM voltage switchable dielectric material
  • FIGS. 20A-C illustrate the deposition of one or more current-carrying formations, according to certain embodiments.
  • Embodiments of the invention use a class of material, referred to herein as voltage switchable dielectric materials, to develop current-carrying elements on a structure or substrate.
  • the electrical resistivity of a voltage switchable dielectric material can be varied between a non-conductive state and a conductive state by an applied voltage.
  • Methods of the invention render the substrate or structure conductive by applying a voltage to the voltage switchable dielectric material, and then subjecting the substrate or structure to an electrochemical process. This process causes current-carrying material to be formed on the substrate.
  • the current-carrying materials can be deposited on select regions of the substrate to form a patterned current- carrying layer.
  • embodiments of the invention provide significant advantages over previous devices having current-carrying structures. Among other advantages, current-carrying material can be patterned onto the substrate with fewer steps, thus avoiding costly and time-consuming steps such as etching and electroless processes.
  • Voltage switchable dielectric materials may also be used for dual-sided and multi-substrate devices having two or more substrate surfaces containing electrical components and circuitry. Vias in substrates formed from voltage switchable dielectric materials can interconnect electrical components and circuitry on different substrate surfaces.
  • a via can include any opening of a substrate or device that can be provided with a conductive layer for the purpose of electrically interconnecting two or more substrate surfaces. Vias include voids, openings, channels, slots, and sleeves that can be provided with a conductive layer to interconnect electrical components and circuitry on the different substrate surfaces.
  • plating a via can be accomplished during a relatively simple electrochemical process. For example, vias in a voltage switchable dielectric material substrate may be plated using an electrolytic process. The vias can also be formed concurrently during the electrolytic process used to pattern one or more conductive layers on a substrate surface or surfaces of the device.
  • a current-carrying structure is formed from a voltage switchable dielectric material.
  • a current-carrying formation can be formed on one or more selected sections of a surface of the substrate.
  • current carrying refers to an ability to carry current in response to an applied voltage.
  • Examples of current-carrying materials include magnetic and conductive materials.
  • formed includes causing the current-carrying formation to form through a process in which a current-carrying material is deposited in the presence of a current applied to the substrate. Accordingly, current-carrying material may be electrodeposited onto the surface of the substrate through processes such as electroplating, plasma deposition, vapor deposition, electrostatic processes, or hybrids thereof. Other processes may also be used to form the current- carrying formation in the presence of an electrical current. The current- carrying formation may be incrementally formed so that a thickness of the current-carrying formation is developed by deposition of like material onto selected sections of the substrate.
  • An electrobonding interface is formed between the current-carrying formation and the substrate.
  • the electrobonding interface comprises an interface layer of electrobonds between the current-carrying formation and the substrate.
  • the electrobonds are bonds formed between molecules of the substrate and molecules of the current-carrying material that are
  • the electrodeposited onto the substrate forms in regions of the substrate where additional current-carrying material is deposited to form the current-carrying formation.
  • electrobonds exclude bonds formed as a result of electroless processes where molecules of the current- carrying material may be mechanically or otherwise added to the surface. Electrobonds exclude bonds formed in processes that include, for example, seeding conductive material onto the substrate using adhesives and other types of mechanical or chemical bonds. Examples of processes where current- carrying material may be electrodeposited to form electrobonds include electroplating, plasma deposition, vapor deposition, electrostatic processes, and hybrids thereof.
  • a nonconductive layer may be patterned onto the surface of the substrate to define the selected sections of the substrate. The substrate is then subjected to an electrochemical process to incrementally form the current- carrying formation on the selected regions of the substrate.
  • the non- conductive layer may comprise a resist layer that is removed once the current- carrying formation is formed on the select regions of the substrate.
  • the non- conductive layer can also be formed from screened resist patterns, which can either be permanent or removable from the substrate.
  • a voltage switchable dielectric material is a material that is non- conductive until a voltage is applied that exceeds a characteristic threshold voltage value. Above the characteristic threshold voltage value the material becomes conductive. Therefore, a voltage switchable dielectric material is switchable between a non-conductive state and a conductive state.
  • An electrochemical process includes a process in which conductive elements are bonded to a voltage switchable dielectric material while the voltage switchable dielectric material is in the conductive state.
  • An example of an electrochemical process is an electrolytic process.
  • an electrode is immersed in a fluid along with another material. A voltage is applied between the electrode and the other material to cause ions from the electrode to transfer and form on the other material.
  • a device in one embodiment, includes a single-sided substrate formed from voltage switchable dielectric material.
  • a non-conductive layer is patterned onto the substrate to define regions on the surface of substrate.
  • the substrate is subjected to an electrolytic process when the voltage switchable dielectric material is in a conductive state.
  • the electrolytic process causes conductive material to incrementally form on the substrate in the regions defined by the pattern of the non-conductive layer.
  • One advantage of this embodiment is that the current-carrying formation can be fabricated on the structure with a reduced thickness relative to previous substrate devices.
  • the patterned current-carrying formation can be formed without implementing some fabrication steps used with prior art structures, such as, for example, steps of etching, or multiple steps of masking, imaging, and developing resist layers.
  • a dual-sided substrate is formed to include vias to electrically connect components on both sides of the substrate.
  • a patterned current-carrying layer is formed on each side of the substrate.
  • One or more vias extend through the substrate.
  • the substrate can be subjected to one or more electrochemical processes while in the conductive state, causing current-carrying material to be formed on selected sections of the substrate, including on surfaces defining the vias.
  • the selected sections of the substrate can be defined by a non-conductive layer, patterned in a previous step.
  • vias are plated only after the substrate is provided with conductive elements on the substrate's surfaces. Failures in the plated vias may not be noticed or caused until at least some or all of the substrates in the device are assembled. If plating a via fails, re-plating the via is not feasible in the assembled device. Often, the entire device has to be discarded. Thus, one failed via in a device having several vias and substrates is enough to cause the entire device, including all of the fabricated substrates, to be discarded. [057] Among other advantages of this embodiment, problematic methods for forming current-carrying formations on surfaces defining vias are avoided.
  • the surfaces of the vias are uniform surfaces of a voltage switchable dielectric material. Thus, electrical continuity through the vias is ensured.
  • a multi-substrate device in another embodiment, includes two or more substrates each formed from a voltage switchable dielectric material. Each substrate can be subjected to an electrochemical process to form a conductive layer. A pattern of each conductive layer is predetermined by patterning a non-conductive layer to define the pattern for the current-carrying formation. One or more vias may be used to electrically connect current-carrying formations on one or more of the substrates. Each via may be formed when the respective substrates are subjected to the electrochemical process.
  • multi-substrate devices use the conductive state of the voltage switchable dielectric material to plate vias interconnecting the different substrate surfaces. Therefore, current-carrying materials can be formed on vias during an electrolytic processes without having to alter the substrate in regions that define the vias. The resulting current-carrying layers formed in the vias significantly reduce the risk that the vias will fail to establish electrical contact between substrates. In contrast, prior art multi-substrate devices have been plagued by occasionally ineffective vias, which often resulted in the entire multi-substrate device having to be discarded.
  • Another advantage provided to embodiments of the invention is that inclusion of a substrate formed from a voltage switchable dielectric material also provides voltage regulation protection to the device as a whole.
  • Embodiments of the invention may be employed for use with, for example, substrate devices such as PCBs, surface mount components, pin connectors, smart cards, and magnetically layered materials.
  • substrate devices such as PCBs, surface mount components, pin connectors, smart cards, and magnetically layered materials.
  • FIG. 1 is a cross-sectional view of a device incorporating a voltage switchable dielectric material, under an embodiment of the invention.
  • the voltage switchable dielectric material is used to form a substrate 10 of the device.
  • the voltage switchable dielectric material is non- conductive but, as previously noted, can be switched to a conductive state by applying a voltage having a magnitude that exceeds a characteristic voltage of the material.
  • Numerous examples of a voltage switchable dielectric material have been developed, including those described below with reference to FIG. 2.
  • Applications in which current-carrying substrates are used include, for example, printed circuit boards (PCBs), printed wiring boards, semiconductor wafers, flex circuit boards, backplanes, and integrated circuit devices. Specific applications of integrated circuits include devices having computer processors, computer readable memory devices, motherboards, and PCBs.
  • the voltage switchable dielectric material in the substrate 10 allows for the fabrication of a patterned current-carrying formation 30.
  • the current- carrying formation 30 is a combination of individual current-carrying elements 35 formed onto the substrate 10 according to a predetermined pattern.
  • the current-carrying formation 30 includes conductive materials.
  • the current-carrying formation 30 is formed from precursors deposited on the substrate 10 during an electrochemical process in which the voltage switchable dielectric material is rendered conductive by an applied voltage (see FIG. 2).
  • the precursors are ions deposited from an electrode into a solution.
  • the substrate 10 is exposed to the solution while the voltage switchable dielectric material is maintained in the conductive state.
  • the precursors selectively deposit on the substrate 10 according to a predetermined pattern.
  • the predetermined pattern is formed by patterning a non-conductive layer 20 such as a resist layer (see FIGS. 3B-3D).
  • a non-conductive layer 20 such as a resist layer
  • the precursors deposit only on the exposed regions of the substrate 10.
  • the voltage switchable dielectric material in the conductive state can form electrochemical bonds with the precursors in the exposed sections of the substrate 10.
  • the non-conductive layer 20 (FIGS, 3B-3D) is formed from a resist layer deposited over the substrate 10. The resist layer is then masked and exposed to create the pattern, as is well known.
  • FIG. 2 illustrates the resistive properties of voltage switchable dielectric materials as a function of applied voltage.
  • the voltage switchable dielectric materials that can be used to form the substrate have a characteristic voltage value (Vc) specific to the type, concentration, and particle spacing of the material's formulation.
  • a voltage (Va) can be applied to the voltage switchable dielectric material to alter the electrical resistance properties of the material. If the magnitude of Va ranges between 0 and Vc, the voltage switchable dielectric material has a high electrical resistance and is therefore non-conductive. If the magnitude of Va exceeds Vc, the voltage switchable dielectric material transforms into a low electrical resistance state in which it is conductive. As shown by FIG. 2, the electrical resistance of the substrate preferably switches sharply from high to low, so that the transformation between states is immediate.
  • Vc ranges between 1 and 100 volts to render the voltage switchable dielectric material conductive.
  • Vc is between 5 and 50 volts, using one of the compositions for voltage switchable dielectric material listed below.
  • a voltage switchable dielectric material is formed having a thickness such that the material switches from an insulating to conducting state at a voltage characterized in terms of a field (e.g., a voltage across the thickness of the material).
  • a switching field may be between 10 and 1000 volts/mil. In some embodiments, a switching field may be between 50 and 300 volts/mil.
  • a voltage switchable material is formed from a mixture comprising conductive particles, filaments, or a powder dispersed in a layer including a non-conductive binding material and a binding agent.
  • the conductive material may comprise the greatest proportion of the mixture.
  • Other formulations that have the property of being non-conductive until a threshold voltage is applied are also intended to be included as voltage switchable dielectric material under embodiments of this invention.
  • a specific example of a voltage switchable dielectric material is provided by a material formed from a 35% polymer binder, 0.5% cross linking agent, and 64.5% conductive powder.
  • the polymer binder includes Silastic 35U silicone rubber
  • the cross-linking agent includes Varox peroxide
  • the conductive powder includes nickel with a 10 micron average particle size.
  • Another formulation for a voltage switchable material includes 35% polymer binder, 1.0% cross linking agent, and 64.0% conductive powder where the polymer binder, the cross-linking agent, and the conductive powder are as described above.
  • conductive particles, powders, or filaments for use in a voltage switchable dielectric material can include aluminum, beryllium, iron, silver, platinum, lead, tin, bronze, brass, copper, bismuth, cobalt, magnesium, molybdenum, palladium, tantalum carbide, boron carbide, and other conductive materials known in the art that can be dispersed within a material such as a binding agent.
  • the non-conductive binding material can include organic polymers, ceramics, refractory materials, waxes, oils, and glasses, as well as other materials known in the art that are capable of inter- particle spacing or particle suspension. Examples of voltage switchable dielectric material are provided in references such as U.S. Patent No.
  • FIGS. 3A-3F illustrate a flow process for forming a single layer current- carrying structure on a substrate as shown in FIG. 1, under an embodiment of the invention.
  • the flow process exemplifies a process in which the electrical properties of a voltage switchable dielectric material are used to develop a current-carrying material according to a predetermined pattern.
  • a substrate 10 is provided that is formed from a voltage switchable dielectric material.
  • the substrate 10 has dimensions, shape, composition and properties as necessary for a particular application.
  • the composition of the voltage switchable dielectric material can be varied so that the substrate is rigid or flexible, as required by the application.
  • the voltage switchable dielectric material can be shaped for a given
  • embodiments described herein disclose essentially planar substrates, other embodiments of the invention may employ a voltage switchable dielectric material that is molded or shaped into a non-planar substrate, such as for use with connectors and semiconductor components.
  • a non-conductive layer 20 is deposited over the substrate 10.
  • the non-conductive layer 20 can be formed from a photoimageable material, such as a photoresist layer.
  • the non-conductive layer 20 is formed from a dry film resist.
  • FIG. 3C shows that the non-conductive layer 20 is patterned on the substrate 10.
  • a mask is applied over the non-conductive layer 20.
  • the mask is used to expose a pattern of the substrate 10 through a positive photoresist.
  • the pattern of the exposed substrate 10 corresponds to a pattern in which current-carrying elements will subsequently be formed on the substrate 10.
  • FIG. 3D shows that the substrate 10 subjected to an electrolytic process while the voltage switchable dielectric material is maintained in a conductive state.
  • the electrolytic process forms a current-carrying formation 30 that includes current-carrying elements 35.
  • the electroplating process deposits current-carrying elements 35 on the substrate 10 in gaps 14 in the non-conductive layer 20 created by masking and exposing the photoresist. Additional details of the electrolytic process as employed under an embodiment of the invention are described with FIG. 4.
  • the non-conductive layer 20 is removed as necessary from the substrate 10.
  • the photoresist may be stripped from the surface of the substrate 10 using a base solution, such as a potassium hydroxide (KOH) solution.
  • KOH potassium hydroxide
  • other embodiments may employ water to strip the resist layer.
  • the resulting conductive layer 30 patterned onto the substrate 10 may be polished.
  • An embodiment employs chemical-mechanical polishing (CMP) means.
  • FIG. 4 details the development of current-carrying elements on the substrate by use of an electroplating process.
  • the electroplating process includes forming an electrolytic solution.
  • the composition of the current-carrying elements depends on the composition of an electrode used to form the electrolytic solution. Accordingly, the composition of the electrode is selected according to factors such as cost, electrical resistance, and thermal properties.
  • the electrode can be gold, silver, copper, tin, or aluminum.
  • the electrode can be immersed in a solution including, for example, sulfate plating, pyrophosphate plating, and carbonate plating.
  • a voltage that exceeds the characteristic voltage of the voltage switchable dielectric material is applied to the substrate 10 while the substrate 10 is immersed in the electrolytic solution.
  • the substrate 10 switches to a conductive state, such as is illustrated by FIG. 2.
  • the applied voltage makes the substrate 10 conductive, causing precursors in the electrolytic solution to bind to the voltage switchable dielectric material.
  • ions from the electrolytic solution bond to the substrate 10 in areas of the substrate 10 that are exposed by the non-conductive layer 20.
  • ions are precluded from bonding to regions where the photoresist has been exposed and developed. Therefore, the pattern of conductive material formed on the substrate 10 matches the positive mask used to pattern the non-conductive layer 20. Exposed regions of the substrate 10 attract and bond to the ions, in some embodiments, because the substrate is maintained at a voltage relative to the electrode so that the substrate, the electrode, and the electrolytic solution together comprise an electrolytic cell, as is well known in the art.
  • current-carrying elements 35 are patterned onto the substrate 10 in a process requiring fewer steps than prior art processes. For example, in an
  • current-carrying elements 35 are deposited to form circuitry on the substrate 10 without etching, and therefore also without deposition of a buffer or masking layer for an etching step.
  • embodiments of the invention allow for the current-carrying elements 35 to be formed directly on the substrate 10 instead of on a seed layer. This allows a vertical thickness of the current-carrying elements 35 to be reduced relative to that in similar devices formed by other processes.
  • Certain devices include substrates that employ electrical components on two or more sides.
  • the number of current-carrying elements that can be retained on a single substrate increases when two sides are used.
  • dual-sided substrates are often used when a high-density distribution of components is desired.
  • Dual-sided substrates include, for example, PCBs, printed wiring boards, semiconductor wafers, flex circuits, backplanes, and integrated circuit devices.
  • vias or sleeves are typically used to interconnect both planar sides of the substrate. The vias or sleeves establish an electrical connection between the current-carrying elements on each planar side of the substrate.
  • FIG. 5 displays an embodiment in which a device includes a dual-sided substrate 310 having one or more plated vias 350.
  • the vias 350 extend from a first planar surface 312 of the substrate to a second planar surface 313 of the substrate.
  • the first surface 312 includes a current-carrying formation 330 having a plurality of current-carrying elements 335.
  • the second surface 313 includes a current-carrying formation 340 having a plurality of current- carrying elements 345.
  • the current-carrying formations 330, 340 are fabricated on the respective sides 312, 313 of the substrate 310 by an electrochemical process.
  • an electrolytic process is used to form a solution of precursors that are deposited on the respective first or second surface of the substrate when a voltage switchable dielectric material is in a conductive state.
  • the precursors deposit on the substrate 310 according to a pattern of a pre-existing non-conductive layer on the respective first or second surface 312, 313.
  • a via 350 is formed in the substrate 310 before the substrate is subjected to the electrolytic process.
  • Each side 312, 313 of the substrate 310 includes a patterned non-conductive layer (not shown).
  • the patterned non-conductive layers are photoresist layers that are patterned to expose select regions on the first and second side 312, 313 of the substrate 310.
  • the via 350 is positioned so that a plated surface of the via 350 subsequently contacts one or more of the current-carrying elements 335, 345 on the first and second side 312, 313.
  • the via 350 is plated while current-carrying formations 330 and 340 are fabricated.
  • the via 350 is provided with a conductive sleeve or side-wall 355 to extend an electrical connection from one of the current-carrying elements 335 on the first surface 312 with one of the current-carrying elements 345 on the second side 313 of the substrate 310.
  • FIG. 6 displays a flow process for developing a dual-sided substrate 310, according to an embodiment of the invention.
  • the substrate 310 is formed from a voltage switchable dielectric material and provided with dimensions, shape, properties, and characteristics necessary for a desired application.
  • a non-conductive layer 320 is deposited over the first and second side 312, 313 of the substrate 310.
  • the non- conductive layer 320 is patterned on the first side 312 of the substrate 310.
  • non-conductive material on at least the first side 312 of the substrate 310 is a photo-imageable material, such as a photoresist that is patterned using a positive mask.
  • the positive mask allows select regions of the substrate 310 to be exposed through the non-conductive layer 320.
  • the non-conductive layer 320 is patterned on the second side 313 of the substrate 310.
  • the non-conductive layer 320 on the second side 313 of the substrate 310 is similarly also a photoresist that is subsequently masked and exposed to form another pattern. The resulting pattern exposes the substrate 310 through the photoresist layer.
  • a step 450 one or more vias 350 are formed through the substrate 310. On each side 312, 313 of the substrate 310, the vias 350 intersect an uncovered portion of the substrate 310. The vias 350 are defined by side-walls formed through the substrate 310.
  • the substrate 310 is subjected to one or more electrolytic processes to plate the first side 312, second side 313, and the side-walls of the vias 350.
  • the substrate 310 is subjected to a single electrolytic process while an external voltage is applied to the voltage switchable dielectric material so that the substrate is in a conductive state.
  • the conductive state of the substrate 310 causes ions in the electrolytic solution to bond to the substrate 310 in uncovered regions on the first and second surfaces 312, 313.
  • the electrolytic fluid also moves through the vias 350 so that ions bond to the side-walls of the vias 350, forming conductive sleeves 355 that extend through the vias 350.
  • the vias 350 intersect current-carrying elements on the first and second sides 312, 313 to electrically connect the current-carrying formation 330 on the first side 312 with the current-carrying formation 340 on the second side 313.
  • the non-conductive layer 320 is removed as necessary from the substrate in a step 470.
  • the photoresist may be stripped from the surface of the substrate 310 using a base solution, such as a KOH solution.
  • a step 480 the resulting current-carrying formation 330 and/or 340 is polished.
  • CMP is employed to polish the current-carrying formation 330.
  • a first non-conductive layer can be deposited on the first surface 312, and a second non-conductive layer can be deposited on the second surface 313 in a separate step.
  • the first and second non-conductive layers can be formed from different materials, and can provide different functions other than enabling patterns to be formed for plating the substrate.
  • the first non-conductive material can be formed from a dry resist
  • the second non-conductive material can be formed from a photo-imageable insulative material. While the dry resist is stripped away after a current-carrying layer is formed on the first side 312, the photo-imageable insulative material is permanent and retained on the second surface 313.
  • different plating processes can be used to plate the first surface 312, the second surface 313, and the surface 355 of the vias 350.
  • the second surface 313 of the substrate 310 can be plated in a separate step from the first surface 312 to allow the first and second surfaces 312, 313 to be plated using different electrodes and/or electrolytic solutions. Since embodiments of the invention reduce steps necessary to form current- carrying layers, forming current-carrying layers 330 and 340 on the dual-sided substrate 310 is particularly advantageous.
  • the use of different plating processes facilitates the fabrication of different materials for the current- carrying formations on opposite sides of the substrate 310. Different types of current-carrying material can be provided as simply as switching the electrolytic baths to include different precursors.
  • a first side of a device such as a PCB is intended to be exposed to the environment, but the opposite side requires a high-grade conductor.
  • a nickel pattern can be plated on the first side of the substrate, and a gold pattern can be plated on the second side of the substrate. This enables the PCB to have a more durable current-carrying material on the exposed side of the PCB.
  • Any number of vias can be drilled, etched, or otherwise formed into the substrate. Vias can interconnect current-carrying elements, including electrical components or circuitry. Alternatively, a via can be used to ground a current-carrying element on one side of the substrate to a grounding element accessible from a second side of the substrate.
  • precursors from the electrode form an electrochemical bond to the surfaces of the vias 350.
  • the vias 350 are therefore securely plated, with minimal risks of a discontinuity that would interrupt electrical connection between the two sides of the substrate 310.
  • FIG. 7 illustrates a multi-substrate device 700.
  • the device 700 includes first, second and third substrates 710,810,910.
  • Each substrate 710-910 is formed from a voltage switchable dielectric material.
  • the substrates 710-910 are non-conductive absent an applied voltage that exceeds the characteristic voltage of the voltage switchable dielectric material.
  • FIG. 7 illustrates an embodiment of three substrates, other embodiments may include more or fewer substrates. It will be appreciated that substrates may also be aligned in different configurations other than being stacked, such as adjacent or orthanormal to one another.
  • Each substrate 710, 810, 910 is provided with at least one current- carrying formation 730, 830, 930 respectively.
  • Each current-carrying formation 730, 830, 930 is formed from a plurality of current-carrying elements 735, 835, 935 respectively.
  • the current-carrying elements 735, 835, 935 are each formed when their respective substrates 710, 810, 910 are subjected to an electrochemical process while in a conductive state.
  • the substrates 710, 810, 910 are mounted on one another after the respective current-carrying layers 735, 835, 935 are formed.
  • the device 700 includes a first plated via 750 to electrically connect current-carrying elements 735 on the first substrate 710 to current-carrying elements 935 on the third substrate 910.
  • the device 700 also includes a second plated via 850 to electrically connect current-carrying elements 835 on the second substrate 810 with current-carrying elements 935 on the third substrate 910. In this way, the current-carrying formations730, 830, 930 of the device 700 are electrically interconnected.
  • the arrangement of plated vias 750, 850 shown in the device 700 is only exemplary, as more or less vias can also be employed.
  • additional vias can be used to connect one of the current- carrying elements 735, 835, 935 to any other of the current-carrying elements on another substrate.
  • the first and second plated vias 750, 850 are formed in the substrates 710, 810, 910 before the substrates 710, 810, 910 are individually plated.
  • the plated vias 750, 850 are formed through the substrates 710, 810, 910 in predetermined positions so as to connect the current-carrying elements 735, 835, 935 of the different substrates as necessary.
  • first plated via 750 openings are formed in the substrates 710, 810, 910 at the predetermined positions before any of the substrates are plated.
  • second plated via 850 openings are formed in the substrates 810, 910 at predetermined positions prior to those substrates being plated.
  • the predetermined positions for the first and second plated via 750 and 850 correspond to uncovered regions on surfaces of the respective substrates in which current-carrying material will form. During subsequent electrolytic processes, precursors deposit in these uncovered regions of the substrates, as well as within the openings formed in each substrate to accommodate the vias 750, 850.
  • the first substrate 710 includes gaps 714 between the current-carrying elements 735.
  • gaps 714 are formed by masking a photoresist layer and then removing remaining photoresist after the current-carrying elements 735 are fabricated on the substrate 710.
  • Similar processes are used to form second and third substrates 810, 910.
  • the first substrate 710 is mounted over the current-carrying formation 830 of the second substrate 810.
  • the second substrate 810 is mounted directly over the current-carrying formation 930 of the third substrate 910.
  • one or more substrates in the device 700 may be dual-sided.
  • the third substrate 910 may be dual-sided, since the location of the third substrate 910 at the bottom of the device 700 readily enables the third substrate to incorporate a double- sided construction. Therefore, the device 700 may include more current- carrying formations than substrates to maximize the density of componentry and/or minimize the overall footprint of the device.
  • composition of the substrates 710, 810, 910, as well as the particular current-carrying material used for each substrate may vary from substrate to substrate.
  • the current-carrying formation of the first substrate 710 maybe formed from nickel, while the current-carrying formation 830 of the second substrate 810 is formed from gold.
  • FIG. 8 illustrates a flow process for developing a device having multi- layered substrates, such as the device 700, where two or more of the substrates are formed from a voltage switchable dielectric material.
  • the device can be formed from a combination of single and/or double-sided substrates.
  • the multi-substrate device 700 comprises separately formed substrates having current-carrying formations.
  • the first substrate 710 is formed from a voltage switchable dielectric material.
  • a first non-conductive layer is deposited over the first substrate 710.
  • the first non-conductive layer can be, for example, a photo- imageable material such as aphotoresist layer.
  • the first non- conductive layer is patterned to form selected regions in which the substrate 710 is exposed.
  • a photoresist layer is masked and then exposed to form the pattern, so that the substrate is exposed according to the pattern of the positive mask.
  • the first via 750 is formed in the substrate 710.
  • the first via 750 is preferably formed by etching a hole in the substrate 710. Additional vias can be formed as needed in the substrate 710.
  • the via 750 is etched in a location on the substrate that is predetermined to be where select current- carrying elements 735 will be located to connect to current-carrying elements of other substrates in the device 700.
  • the first substrate 710 is subjected to an electrolytic process.
  • the electrolytic process employs an electrode and a solution according to design requirements for the first substrate 710. Components of the electrolytic process, including the electrode and the composition of the electrolytic solution, are selected to provide the desired precursors, i.e.
  • a step 660 the remaining non-conductive layer on the first substrate 710 is removed.
  • the current-carrying elements 735 on the first substrate 710 may then be polished in a step 670, preferably using CMP. [099] Once the first substrate 710 is formed, additional substrates 810, 910 can be formed in step 680 to complete the multi-substrate device 700.
  • Subsequent substrates 810, 910 are formed using a combination of the steps 610-670.
  • One or more additional vias, such as the second via 850, may be formed in another substrate as described according to steps 640 and 650.
  • the device 700 may include additional substrates formed as described in steps 610-680, or as described for double-sided substrates above.
  • substrates used in the device can have voltage switchable dielectric materials with different compositions. Accordingly, the external voltage applied to each substrate to overcome the characteristic voltage can vary between substrates. Materials used for the non-conductive layers can also be varied from substrate to substrate. Additionally, the non-conductive layers can be patterned with, for example, different masking, imaging, and/or resist development techniques. Further, the materials used to develop current-carrying elements on the surfaces of the substrates can also be varied from substrate to substrate. For instance, the electrodes used to plate each substrate can be altered or changed for the different substrates, depending on the particular design parameters for the substrates.
  • the process can include the construction of at least one double-sided substrate, such as at an end of the stack of substrates.
  • the third substrate 910 can be formed to include current-carrying elements 935 on both planar sides.
  • a non-conductive layer is deposited on the first side and the second side of the third substrate 910.
  • the non-conductive layer on the second side can be made of the same material as the non-conductive layer on the first side, although in some applications the second side of the substrate may require a different type of photo-imageable material or other non-conductive surface.
  • the non- conductive layers on each side of the third substrate 910 are then individually patterned.
  • the third substrate 910 is uncovered on the first and second sides when the respective non-conductive layers are patterned. Exposed regions on each side of the substrate may be plated together or in separate plating steps.
  • Embodiments such as shown above can be used in PCB devices.
  • PCBs have a variety of sizes and applications, such as for example, for use as printed wiring boards, motherboards, and printed circuit cards.
  • a high density of current-carrying elements such as electrical components, leads, and circuitry, are embedded or otherwise included with PCBs.
  • the size and function of the PCBs can be varied.
  • a device including a PCB under an embodiment of the invention has a substrate formed from a voltage switchable dielectric material.
  • a photoresist such as a dry film resist can be applied over the substrate.
  • dry film resist includes Dialon FRA305, manufactured by Mitsubishi Rayon Co.
  • the thickness of the dry film resist deposited on the substrate is sufficient to allow the substrate to become exposed at selected portions corresponding to where the resist was exposed by the mask.
  • An electroplating process such as described with respect to FIG. 3 is used to plate conductive materials on exposed regions of the substrate.
  • Substrates formed from a voltage switchable dielectric material can be used for various applications.
  • the voltage switchable dielectric material can be formed, shaped, and sized as needed for the various printed circuit board applications.
  • Examples of printed circuit boards include, for example, (i) motherboards for mounting and interconnecting computer components; (ii) printed wiring boards; and (iii) personal computer (PC) cards and similar devices.
  • An embodiment of the invention employs a pulse plating process.
  • a pulse plating process an electrode and a substrate comprising a voltage switchable dielectric material are immersed in an electrolytic solution.
  • a voltage is applied between the electrode and the substrate so that the voltage switchable dielectric material becomes conductive.
  • the applied voltage also causes ions in the electrolytic solution to deposit onto exposed areas of the substrate, thereby plating a current-carrying formation.
  • the voltage is modulated and follows a waveform such as the exemplary waveform 900 shown in FIG. 9.
  • the waveform 900 resembles a square-wave, but further includes a leading edge spike 910.
  • the leading edge spike 910 is preferably a very short duration voltage spike sufficient to overcome a trigger voltage, Vt, of the voltage switchable dielectric material, where the trigger voltage is a threshold voltage that must be exceeded in order for the voltage switchable dielectric material to enter the conductive state.
  • Vt a trigger voltage
  • the trigger voltage is relatively large, such as between 100 and 400 volts.
  • the voltage switchable dielectric material will remain in the conductive state for as long as the voltage applied to the voltage switchable dielectric material remains above a lower clamping voltage, Vc.
  • Vc lower clamping voltage
  • the leading edge spike 910 is followed by a plateau 920 at a voltage above the clamping voltage.
  • the plateau 920 is followed by a relaxation period in which the voltage returns to a baseline 930, such as 0 volts, then the cycle repeats.
  • FIG. 10 Another embodiment of the invention employs a reverse pulse plating process. This process is essentially the same as the pulse plating process described above, except that in place of the plateau 920 (FIG. 9) the polarity of the voltage is reversed so that plating occurs at the electrode instead of the substrate.
  • An exemplary waveform 1000 is shown in FIG. 10 in which the positive and negative portions have essentially the same magnitude but opposite polarity. The shape of the negative portion need not match that of the positive portion in either magnitude or duration, and in some
  • the negative portion of the waveform 1000 does not include a leading edge voltage spike.
  • Another embodiment of the invention employs a silk-screening method to develop a patterned non-conductive layer on a substrate formed from a voltage switchable dielectric material.
  • This embodiment avoids the use of materials such as photoresist to develop the pattern for depositing current-carrying materials on the substrate.
  • a robotic dispenser applies a dielectric material to the surface of the substrate according to a preprogrammed pattern.
  • the silkscreen liquid applicant is typically a form of plastic or resin, such as Kapton.
  • silk- screened Kapton is permanently applied to the surface of the substrate.
  • silk-screening offers advantages of combining steps for depositing and patterning non-conductive material on the substrate, as well as eliminating steps for removing non-conductive material from the surface of the substrate.
  • current-carrying elements may be fabricated onto a surface of a substrate from two or more types of current-carrying materials.
  • the substrate including the voltage switchable dielectric material is adaptable to be plated by several kinds of current-carrying materials.
  • two or more electrolytic processes can be applied to a surface of the substrate to develop different types of current-carrying particles.
  • a first electrolytic process is employed to deposit a first conductive material in a first pattern formed on the surface of the substrate.
  • a second non-conductive layer is patterned on the substrate including the first conductive material.
  • a second electrolytic process may then be employed to deposit a second conductive material using the second pattern.
  • a substrate may include multiple types of conductive material.
  • copper can be deposited to form leads on the substrate and another conductive material, such as gold, can be deposited elsewhere on the same surface where superior conduction is necessary.
  • another conductive material such as gold
  • Embodiments of the invention include various devices with a substrate of a voltage switchable dielectric material upon which a current-carrying formation has been deposited.
  • the current-carrying formation can comprise circuits, leads, electrical components, and magnetic material. Exemplary applications for embodiments of the invention are described or listed below. The applications described or listed herein are merely illustrative of the diversity and flexibility of this invention, and should therefore not be construed as an exhaustive list.
  • a pin connector is provided.
  • the voltage switchable dielectric material is used to form an interior structure of a female pin connector.
  • the voltage switchable dielectric material can be used to form contact leads within the interior structure of the female pin connector.
  • the voltage switchable dielectric material may be shaped into the interior structure using, for example, a mold that receives the voltage switchable dielectric material in a liquid form.
  • the resulting interior structure includes a mating surface that opposes a corresponding male pin connector when the two connectors are mated. Pin receptacles are accessible through holes in the mating surface. The holes and pin receptacles correspond to where pins from the male connector will be received.
  • the interior structure may be separated into segments 1100 to expose the lengths of the pin receptacles 1110 that extend to the holes in the mating surface 1120.
  • a non-conductive layer 1200 shown in FIG. 12, such as a photoresist layer may be deposited on one of the segments 1100.
  • the non- conductive layer 1200 may then be patterned so that a bottom surface 1210 of each pin receptacle 1110 is exposed through the non-conductive layer 1200.
  • One or both segments 1100 of the interior structure may then be subjected to an electrolytic plating process. During the plating process, a voltage is applied to the interior structure so that the voltage switchable dielectric material is conductive.
  • a conductive material is then plated on the bottom surface 1210 of each pin receptacle 1110 in the interior structure. Once the contact leads are formed in the pin receptacles 1110, the non-conductive layer 1200 can be removed and the segments 1100 rejoined.
  • the interior structure may also be housed within a shell to complete the female pin connector.
  • Plating the interior structure enables a large number of pin receptacles to be included in the interior structure in one plating process. Further, because the lead contacts can be made thinner, pin receptacles can be formed closer together to reduce dimensions of the pin connector.
  • the pin connector can also provide over-voltage protection properties that are inherent to voltage switchable dielectric materials.
  • Surface mount packages mount electronic components to a surface of a printed circuit board.
  • Surface mount packages house, for example, resistors, capacitors, diodes, transistors, and integrated circuit devices (processors, DRAM etc.).
  • the packages include leads directed internally or outwardly to connect to the electrical component being housed.
  • Specific examples of surface mounted semiconductor packages include small outline packages, quad flat packages, plastic leaded chip carriers, and chip carrier sockets.
  • Manufacturing surface mount packages involves forming a frame for the leads of the package.
  • the frame is molded using a material such as epoxy resin. Thereafter, leads are electroplated into the molded frame.
  • a voltage switchable dielectric material can be used to form the frame.
  • a non-conductive layer is formed on the frame to define the locations of the leads.
  • the non-conductive layer can be formed during the molding process, during a subsequent molding process, or through a masking process using a photo-imageable material such as described above.
  • a voltage is applied to the frame during the electroplating process to rendering the frame conductive.
  • the leads form on the frame in locations defined by a pattern of the non-conductive layer.
  • leads can be made thinner or smaller, allowing for a smaller package that occupies a smaller footprint on the PCB.
  • the voltage switchable dielectric material also inherently provides over-voltage protection to protect contents of the package from voltage spikes.
  • FIG. 13 illustrates certain embodiments associated with intermediate layers.
  • These layers may have appreciable thickness (e.g., greater than tens of nm, a few microns, tens of microns, or even tens of mm), or may be as thin as monolayers (e.g., having a thickness of the order of an atom, a few atoms, or a molecule).
  • such layers are termed intermediate layers.
  • FIG. 13 includes a diagrammatic representation of exemplary processing steps (left side) and corresponding structures (right side) associated with the use of intermediate layers according to some
  • a VSDM 1302 is provided.
  • the VSDM may be provided as a layer or coating on a substrate 1304.
  • a VSDM may have a characteristic voltage, above which the VSDM becomes conductive.
  • the characteristic voltage of a VSDM is above a typical "use" voltage associated with an electronic device (e.g., above 3 Volts, 5 Volts, 12 Volts, or 24 Volts).
  • the electronic device e.g., above 3 Volts, 5 Volts, 12 Volts, or 24 Volts.
  • characteristic voltage of a VSDM is above a typical voltage used for electroplating a material (e.g., above 0.5 volts, 1.5 volts, or 2.5 volts). In some cases, electroplating may require a voltage that is both above a typical plating voltage and above the characteristic voltage.
  • VSDM 1302 may be masked using mask 1312, although masking may not be required for certain applications.
  • mask 1312 defines an exposed portion 1314 of the VSDM upon which a current-carrying formation will be formed, and a "masked" region (e.g., beneath the mask) upon which a current-carrying material is not deposited.
  • mask 1312 defines an exposed portion 1314 of VSDM 1302 upon which a current-carrying formation may be fabricated.
  • an intermediate layer 1322 may be deposited on at least part of the exposed portion 1314.
  • Intermediate layer 1322 may be sufficiently thick that certain desirable properties are manifest (e.g., adherence, diffusion blocking, improved electrical properties and the like).
  • an intermediate layer may be used to attach a polymer to VSDM 1302.
  • an intermediate layer may be sufficiently thin and/or conductive that subsequent deposition of a current-carrying material on intermediate layer 1322 may be performed.
  • Intermediate layer 1322 may form an insulating barrier, and in some cases, may provide for conductivity via tunneling and/or other nonlinear effects.
  • a current-carrying material 1332 may be deposited on the intermediate layer.
  • mask 1312 may be removed after formation of the current-carrying formation.
  • step 1340 illustrates the removal of mask 1312, yielding a current-carrying formation 1342 comprising a current-carrying material and an intermediate layer.
  • An intermediate layer may include a diffusion barrier to reduce or prevent diffusion between a current-carrying material (e.g., Cu) and a VSDM material.
  • exemplary diffusion barriers include metals, nitrides, carbides, silicides, and in some cases combinations thereof.
  • Exemplary diffusion barriers include TiN, TaN, Ta, W, WN, SiC, Si3N4, TaTiN, SiON, Re, MoSi2, TiSiN, WCN, composites thereof, and other materials.
  • An intermediate layer may be electrically conductive. For very thin intermediate layers (e.g., less than lOOnm, 50nm, or even less than lOnm), even relatively resistive materials may provide for sufficient current densities that electrical current may flow from the depositing current-carrying material to the VSDM phase.
  • An intermediate layer may be a conductive polymer, such as certain doped polythiophenes and/or polyanilines.
  • Intermediate layers may be fabricated using line-of sight deposition, physical vapor deposition, chemical vapor deposition, electrodeposition, spin coating, spraying, and other methods.
  • Various embodiments include electrodeposition of current-carrying materials.
  • a VSDM (optionally including an intermediate layer) is immersed in a plating solution, after which a plating bias is created to cause electroplating of a current-carrying material.
  • the plated VSDM is removed from the plating bath while still subject to the plating bias.
  • Electrodeposition may include imposing electrical currents between 0.1 and 10 milliamps/square cm.
  • An exemplary plating solution may include copper ions at a concentration between 0.4 and lOOmM, a copper complexing agent such as [ethylamine, pyridine, pyrrolidine,
  • hydroxyethyldiethylamine, aromatic amines, and nitrogen heterocycles having a molar ratio between 0.1 and 2 and a pH between 3 and 7.
  • Some embodiments may use procedures and materials as described in U.S. patent publication numbers 2007/0062817 Al and 2007/0272560 Al, the disclosures of which are incorporated by reference herein.
  • Certain embodiments include electrografting one or more layers, as described, for example, in U.S. patent application publication number 2005/0255631 Al, the disclosure of which is incorporated by reference herein.
  • depositing an intermediate layer may include electrografting the intermediate layer.
  • electrografting may be used to deposit insulating layers (e.g., insluating polymers) on a VSDM material by incorporating an electrografted
  • Electrografting may be described as the electrochemical bonding (e.g., electrobonding) of a polymer, and may include immersing a VSDM in a solution having a dissolved organic precursor. Application of an appropriate voltage (including a voltage profile) may cause the VSDM to conduct electrons, which may result in an electrochemical deposition of the dissolved polymer onto the surface of the VSDM. As such, a polymer may be electrobonded to the VSDM.
  • An exemplary electrografting embodiment may include immersing the VSDM in a solution comprising an organic precursor.
  • An exemplary solution may include butylmethacrylate in a solution comprising 5E-2 mol/L of tetraethylammonium perchlorate in DMF, in an amount of 5 mol of butylmethacrylate/L of solution.
  • the VSDM may be the working electrode, with a Pt counterelectrode, and Ag reference electrode.
  • the immersed VSDM may be subject to a voltage profile sufficient to cause the VSDM to conduct (e.g., cyclic voltage between -0.1 and -2.6 V/(Ag+-Ag), and cycled (e.g., at a rate of 100 mV/s) to deposit an organic film (e.g, poly-butylmethacrylate).
  • a voltage profile sufficient to cause the VSDM to conduct (e.g., cyclic voltage between -0.1 and -2.6 V/(Ag+-Ag), and cycled (e.g., at a rate of 100 mV/s) to deposit an organic film (e.g, poly-butylmethacrylate).
  • a poly-methyl-methacrylate (pMMA) film may be electrografted to a VSDM material by immersing the VSDM in a solution comprising MMA (e.g., 3.125 mol/L of MMA, 1E-2 mol/L of 4- nitrophenyldiazonium tetrafluoroborate and 2.5E-2 mol/L of Na-nitrate in DMF), and subjecting the immersed VSDM to a voltage cycle sufficient to cause the VSDM to become conductive.
  • An exemplary voltage cycle may include cycling between -0.1 and -3 V/(Ag+/Ag) at 100 mV/sec to form a pMMA layer on the VSDM.
  • FIG. 14 illustrates an exemplary method and structure that
  • FIG. 14 is a diagrammatic representation of exemplary processing steps (left side) and corresponding structures (right hand side) associated with a conductive backplane, according to certain embodiments.
  • a conductive backplane 1402 is provided.
  • the conductive backplane may be incorporated into or onto a substrate.
  • a conductive backplane may act as a substrate itself (e.g., a thick metal foil or sheet).
  • a voltage switchable dielectric material 1412 may be deposited on at least a portion of the conductive backplane (e.g., by spin coating).
  • VSDM 1412 may be masked to demarcate exposed regions for subsequent creation of a current-carrying formation. In other embodiments, VSDM 1412 may be unmasked. In optional step 1420, mask 1422 may be applied to VSDM 1412, defining a region 1424 where a current-carrying formation may be deposited.
  • a current carrying formation 1432 may be formed by depositing a conductive material on the VSDM 1412 (in this example, in region 1424).
  • mask 1422 may be removed.
  • a conductive backplane may reduce the distance or thickness of VSDM through which electrical current passes (e.g., the conductive backplane may act as a "bus bar").
  • a conductive backplane may improve (e.g., smooth out or make more uniform) the current density distribution through the VSDM.
  • Embodiments without a conductive backplane may require some current passage in a horizontal dimension (i.e., normal to the thickness of a VSDM layer).
  • Embodiments with a conductive backplane may provide for reduced distances of current passage, in that electrical current may pass from a current-carrying formation through the VSDM layer to the conductive backplane in a direction orthogonal to the layer.
  • a conductive backplane may improve the uniformity of current density during deposition (e.g., of a current carrying formation) and may improve the performance of a VSDM in certain electrostatic discharge (ESD) events.
  • a conductive backplane may result in a reduced distance over which current passes, which may provide for lower resistance as compared to a VSDM layer not disposed on a conductive backplane.
  • a thinner VSDM layer may be combined with a conductive backplane to yield properties equivalent to a thicker VSDM layer without a conductive backplane.
  • a conductive backplane may be metallic (e.g., Cu, Al, TiN); a conductive backplane may include a conductive polymer.
  • FIG. 15 is a diagrammatic illustration of attaching a package, according to some embodiments.
  • a package may be attached to a current-carrying formation and/or a voltage switchable dielectric material.
  • the attached components may be protected (e.g., from dust, moisture and the like) using the package.
  • a package may provide for improved mechanical properties (e.g., strength, stiffness, resistance to warping) and/or may improve the ease with which packaged components may be further processed (e.g., attaching leads to a device). Vias, studs, lines, wires and/or other connections to a device contained within the package may be included with a package.
  • FIG. 15 illustrates attachment of a package 1502 to a component including a current-carrying formation 1504 deposited on a voltage switchable dielectric material 1505.
  • voltage switchable dielectric material 1505 may be disposed on an optional conductive backplane 1506, which may be disposed on an optional substrate 1508.
  • a package may be attached to a current-carrying formation and/or VSDM without a conductive backplane and/or without a substrate.
  • a package 1502 is attached, typically to at least a portion of the voltage switchable dielectric material 1504 and current-carrying formation 1505.
  • a package may include a polymer, a composite, a ceramic, a glass, or other material.
  • a package may be insulating.
  • a package may include a polymer coating, such as a phenolic, an epoxy, a ketone (e.g., poly-ether-ether ketone, or PEEK) and/or various materials used in microelectronics packaging and/or the fabrication of printed wiring boards.
  • substrate 1508 may be removed.
  • Certain embodiments include a substrate that is dissolvable, etchable, or meltable.
  • a substrate may include a wax or other material that melts at temperatures below 50 Celsius.
  • a substrate may include a metal foil.
  • a decohesion layer may be incorporated at the interface between the substrate and the conductive backplane (or the VSDM, as the case may be), which may provide for improved removability of the substrate.
  • a decohesion layer may include an intermediate layer.
  • conductive backplane 1506 may be removed.
  • a conductive backplane may be dissolved or etched (e.g., in an appropriate acid).
  • a conductive backplane comprising an electrically conducting polymer may be dissolved in an organic solvent.
  • a conductive backplane may be thermally etched, plasma etched, ashed, or otherwise removed.
  • a VSDM may be disposed directly on a substrate, and the substrate may be removed after formation of a current- carrying formation, and often after having attached a package.
  • a VSDM may be disposed on a conductive backplane without a substrate, and the conductive backplane may be removed after having formed a current-carrying formation.
  • a decohesion layer may aid removal in these and other applications.
  • FIGS. 16A and 16B illustrate cross section and perspective views (respectively) of a removable contact mask, according to certain
  • substrate 1600 having a layer of voltage switchable dielectric material (VSDM) 1602 is shown, although a contact mask may be used with a voltage switchable dielectric material without a substrate.
  • VSDM voltage switchable dielectric material
  • a contact mask 1610 includes an insulating foot 1620 and an electrode 1630. Electrode 1630 may connect to one or more electrical leads 1632, which may provide for electrochemical reactions.
  • Contact mask 1610 typically includes one or more openings 1640, which may be openings in insulating foot 1620.
  • Insulating foot 1620 may sealingly attach contact mask 1610 to VSDM 1602 in such a manner as to form a seal. The sealed regions of VSDM 1602 are masked from deposition or other reaction. In some embodiments, contact mask 1610 may be pressed against VSDM 1602. Typically, insulating foot 1620 may be sufficiently compliant that contact mask 1610 masks a region of VSDM 1602 from formation of a current-carrying structure and defines a portion 1650 of VSDM 1602 upon which a current-carrying formation may be formed.
  • Insulating foot 1620 may separate electrode 1630 from VSDM 1602 by a distance 1660. Distance 1660 may be less than 1cm, 5mm, 1mm, or even less than 500 microns. Insulating foot 1620 may also support electrode 1630 substantially parallel to VSDM 1602, which may improve the uniformity of current-density (e.g., during deposition) through portion 1650. Insulating foot 1620 may be fabricated from a variety of ceramic, polymer, or other insulating materials, such as polyimide, poly-tetrafluoroethylene, latex, photoresist materials, epoxy, polyethylene, and spin-on polymers. In some embodiments, polyimide, poly-tetrafluoroethylene, latex, photoresist materials, epoxy, polyethylene, and spin-on polymers. In some embodiments, polyimide, poly-tetrafluoroethylene, latex, photoresist materials, epoxy, polyethylene, and spin-on polymers.
  • an intermediate layer may be used to improve adherence and/or sealing of an insulating foot to an electrode. In some embodiments, an intermediate layer may be used to improve sealing and/or adherence of an insulating foot to a VSDM.
  • Openings 1640 may be configured to expose one or more portions 1650 to a fluid (e.g., a liquid, gas, plasma and the like) containing ions associated with formation of a current-carrying structure.
  • a fluid e.g., a liquid, gas, plasma and the like
  • depositing a copper conductor may include exposing portion 1650 to a solution having copper ions.
  • openings 1640 are sufficiently large and/or plentiful that a deposition fluid may be supplied "continuously" or fast enough that the supply of deposition fluid does not limit deposition.
  • Electrode 1630 may be fabricated from a suitably conductive material.
  • electrode 1630 may include a metal foil, such as a Ti, Pt, or Au foil.
  • Contact mask 1610 may also include additional materials, such as layers that improve mechanical properties, layers that improve adherence, layers that improve deposition quality and the like.
  • Electrode 1630 and insulating foot 1620 may each comprise a plurality of materials.
  • a die (not shown) having a pattern (e.g., that matches the shape of portions 1650) is used to apply uniform pressure to a "top" side of contact mask 1610.
  • Formation of one or more current-carrying formations may include electrochemical deposition, and in some cases, may include electrochemical pattern replication (ECPR) as described in U.S. patent application publication number 2004/0154828 Al, the disclosure of which is incorporated herein by reference.
  • ECPR electrochemical pattern replication
  • FIG. 17 illustrates deposition of a current-carrying material to form a current-carrying formation, according to certain embodiments. Exemplary steps in a deposition process are shown on the left side of FIG. 17, along with exemplary structures on the right side of FIG. 17.
  • contact mask 1610 may be applied to a voltage switchable dielectric material (VSDM) 1710 to form a "sandwich" 1720.
  • Sandwich 1720 may optionally include a substrate 1712.
  • VSDM 1710 and substrate 1712 may be planar and sufficiently stiff that contact mask 1610 may be sealingly attached to VSDM 1710.
  • contact mask 1610 is removably attached to VSDM 1710, for example using a clamp or other means of applying pressure.
  • sandwich 1720 may be immersed in a fluid 1732 that provides a source of ions associated with a current-carrying material.
  • fluid 1732 may be a plating solution.
  • a solution having copper ions may be used to fabricate a copper current-carrying formation, with metallic copper forming the electrical conductor of the formation.
  • Fluid 1732 may be circulated and/or agitated such that it passes through openings 1640, exposing portions 1650 to the fluid.
  • a voltage 1742 may be created between electrode 1630 and VSDM 1710.
  • voltage 1742 is larger (in magnitude) than a characteristic voltage associated with VSDM 1710, such that VSDM 1710 conducts current under voltage 1742.
  • Voltage 1742 may cause a deposition of a current-carrying formation 1744 on portion 1650.
  • Fluid 1732 may be replenished (e.g., via openings 1640) sufficiently fast that current-carrying formation plates uniformly.
  • step 1750 contact mask 1610 may be removed. In some embodiments,
  • a contact mask may be re-used for multiple depositions.
  • a voltage may be applied prior to immersion of the VSDM/contact mask into the plating solution. In some embodiments, the applied voltage may be maintained until after the VSDM/contact mask has been removed from the plating solution.
  • FIG. 18 illustrates a current-carrying formation fabricated using an etching process, according to certain embodiments. Exemplary steps are shown on the left side of FIG. 18, along with exemplary structures on the right side of FIG. 18.
  • a contact mask 1610 may be applied to a conductor 1802 disposed on a voltage switchable dielectric material (VSDM) 1804, which may be disposed on top of a substrate 1806, forming a "sandwich" 1808.
  • Contact mask 1610 defines one or more portions 1814 of conductor 1802 to be exposed to an etching solution, and prevents etching of regions of conductor 1802 in regions beneath the mask.
  • sandwich 1808 may be immersed in an etching solution 1812.
  • Etching solution 1812 may be chosen to electrochemically etch conductor 1802, often using an applied voltage.
  • Etching solution 1812 may pass through openings 1640, reaching exposed portions 1814.
  • a deposition solution may also be operated as an etching solution by reversing the sign (or polarity) of the applied voltage.
  • a voltage 1822 may be applied between electrode 1630 and VSDM 1804.
  • Voltage 1822 may be chosen to match a composition of etching solution 1812 and optionally the circulation of etching solution 1812 through openings 1640, such that conductor 1802 may be etched.
  • voltage 1822 is greater than a characteristic voltage associated with VSDM 1804, which may be greater than a typical etching voltage (e.g., 1 volt, 3 volts, or 5 volts).
  • the regions of conductor 1802 remaining unetched may become one or more current-carrying formations 1824.
  • step 1830 contact mask 1610 may be removed.
  • conductor 1802 may be deposited as a sufficiently thick layer (e.g., several microns or more) that current-carrying formation 1824 may be used as-etched.
  • an additional current-carrying material 1842 may incorporated into current-carrying formation 1824.
  • current-carrying material 1824 may be deposited on current-carrying formation 1824.
  • FIG. 19 illustrates a voltage switchable dielectric material (VSDM) 1910 having regions with different characteristic voltages, according to certain embodiments. Such a configuration may improve an ability to fabricate current-carrying formations in different regions.
  • VSDM 1910 may have regions having different deposition and/or etching characteristics.
  • a first region 1940 may include one or more voltage switchable dielectric materials having a first characteristic voltage
  • a second region 1950 may include one or more voltage switchable dielectric materials having a second characteristic voltage.
  • a current-carrying formation may be formed on first region 1940, or second region 1950, or both regions, according to different deposition conditions.
  • VSDM 1910 may be disposed on a conductive backplane 1920, which may optionally be disposed on a substrate 1930.
  • first region 1940 may be characterized by a first thickness 1942 between conductive backplane 1920 and the surface of region 1940.
  • a second region 1950 may be characterized by a second thickness 1952 between conductive backplane 1920 and the surface of region 1950.
  • regions 1940 and 1950 may also be
  • deposition may include immersing VSDM 1910 in a deposition solution having ions associated with a material to be deposited.
  • diffusion of ions from the bulk solution to the surfaces of regions 1940 and 1950 may be slow enough that a difference between depths 1946 and 1956 has an appreciable effect on the relative deposition and/or etching rates at the respective surfaces.
  • a cyclic voltage may be imposed, and in some cases, the frequency of the cyclic voltage is chosen pursuant to diffusion times associated with diffusion of ions within depths 1946 and 1956.
  • Deposition may include the use of an electrode 1960, which may be a planar electrode.
  • deposition and/or etching in regions 1940 and 1950 may be modified by choosing an appropriate distance from the respective surface to electrode 1960.
  • first distance 1944 may characterize a length from the surface of region 1940 to electrode 1960
  • second distance 1954 may characterize a length from the surface of region 1950 to electrode 1960.
  • first region 1940 may have a different characteristic voltage than that of second region 1950. In some cases, this difference may be due to different thicknesses of the VSDM in each region, which may cause a difference in the field densities associated with the regions.
  • a different VSDM may be used in each region.
  • a VSDM layer may include a plurality of VSDM materials (e.g., arranged in layers). For example, a first VSDM may have a depth equal to second thickness 1952, and a combination of first VSDM and second VSDM may have a depth equal to first thickness 1942.
  • Regions having different characteristic voltages may be fabricated by stamping or other physical forming. Regions having different characteristic voltages may be fabricated by ablating, laser-ablating, etching, or otherwise removing material.
  • a first region may be formed using a first mask (e.g., a photoresist), and a second region may be formed using a second mask.
  • FIGS. 20A-C illustrate the deposition of one or more current-carrying formations, according to certain embodiments.
  • VSDM 1920 is used as an example for illustrative purposes only.
  • VSDM 1920 includes a first region 1940 having a first characteristic voltage, and a second region 1950 having a second characteristic voltage.
  • a current-carrying formation may be formed on first region 1940, or second region 1950, or both regions 1940 and 1950, according to different processing conditions.
  • FIG. 20A illustrates a structure comprising a first electrical conductor 2010, formed on second region 1950.
  • Electrical conductor 2010 may be formed, for example, by exposing VSDM 1910 to a source of ions (associated with the conductor). A voltage difference may be created between VSDM 1910 and the source of ions that is greater than the characteristic voltage associated with second region 1950 and less than the characteristic voltage associated with first region 1940.
  • First region 1940 may remain insulating, while second region 1950 becomes conducting, and deposition may occur only on second region 1950.
  • FIG. 20B illustrates a structure comprising a first electrical conductor 2020 formed on first region 1940 and a second electrical conductor 2030 formed on second region 1950.
  • Electrical conductors 2020 and 2030 may be formed, for example, by exposing VSDM 1910 to a source of ions (associated with the conductor). A voltage difference may be created between VSDM 1910 and the source of ions that is greater than the characteristic voltages associated with both first region 1940 and second region 1950. Deposition may occur on both first region 1940 and second region 1950.
  • FIG. 20C illustrates a structure having a first electrical conductor 2020 formed on first region 1940 having a characteristic voltage that is greater than the characteristic voltage associated with second region 1950.
  • a structure may be formed, for example, by selectively etching a structure formed according to FIG. 20B.
  • electrical conductors 2020 and 2030 may be formed by exposing VSDM 1910 to a source of ions (associated with the conductor). A voltage difference may be created between VSDM 1910 and the source of ions that is greater than the characteristic voltages associated with both first region 1940 and second region 1950. Deposition may occur on both first region 1940 and second region 1950, forming two (or more) current-carrying formations.
  • electrical conductor 2030 may be preferentially etched (e.g., to the point of its complete removal), leaving electrical conductor 2020 as shown.
  • a conductor may be etched by reversing the polarity of a deposition voltage. In such cases, etching may be associated with current flow through a region. By choosing an etching voltage that is greater than the characteristic voltage associated with second region 1950, but less than the characteristic voltage associated with first region 1940, preferential etching associated with second region 1950 may be achieved.
  • Embodiments of the invention also provide micro-circuit board applications.
  • smart cards are credit-card size substrate devices having one or more embedded computer chips.
  • a smart card typically includes a mounted micro-memory module and conductors for
  • micro-memory module interconnecting the micro-memory module with other components such as a sensor for detecting smart card readers. Due to the size of the smart card, as well as the size of the components embedded or mounted to the smart card, conductive elements on the substrate of the smart card also have to be very small.
  • a voltage switchable dielectric material is used for the substrate of a smart card.
  • An electrolytic plating process such as described above is used to produce a pattern of connectors on the smart card to connect the memory module to other components.
  • a conductive layer comprising the pattern of connectors is plated onto the surface of the substrate through a photoresist mask as described above.
  • the pattern of connectors can be plated onto the substrate without having to etch. This can reduce the thickness of the conductive layer on the substrate.
  • Another micro-circuit board application includes a circuit board that packages two or more processors together.
  • the circuit board includes leads and circuits that enable high-level communications between the several processors mounted on the board so that the processors act substantially as one processing unit. Additional components such as a memory can also be mounted to the circuit board to communicate with the processors. Fine circuitry and lead patterns are therefore required to preserve processing speed for communications that pass between two or more processors.
  • the micro-circuit board also includes a substrate formed from a voltage switchable dielectric material.
  • a fine resist layer is patterned onto the substrate to define a pattern for selected regions of conductive material to be subsequently deposited.
  • An electrolytic process is used to plate conductive material in selected regions according to a pattern to interconnect processors subsequently mounted to the circuit board.
  • one advantage provided by using voltage switchable dielectric materials is that conductive layers can be made with reduced thicknesses. Another advantage is that plating conductive material with fewer fabrication steps reduces manufacturing costs for the micro-circuit board. Still another advantage is that a micro-circuit board can be developed to have conductive elements formed from more than one type of conductive material. This is particularly advantageous for interconnecting processors on one micro-circuit board because material requirements of the conductors may vary for each processor, depending on the quality, function, or position of each processor. For example, processors of the micro-circuit board that are exposed to the environment may require more durable conductive elements, for example made from nickel, to withstand temperature fluctuations and extremes.
  • a processor for handling more computationally demanding functions, and located away from the environment can have contacts and leads formed from a material with a higher electrical conductivity such as gold or silver.
  • a substrate is integrated into a memory device that includes a plurality of memory cells.
  • Each memory cell includes a layer of a magnetic material.
  • the orientation of a magnetic field of the layer of the magnetic material stores a data bit.
  • the memory cells are accessed by electrical leads. Voltages applied to the memory cells via the electrical leads are used to set and to read the orientations of magnetic fields.
  • Transistors mounted to, or formed in, the substrate are used to select the memory cells to be set and to be read.
  • the substrate used in the memory device is formed from a voltage switchable dielectric material.
  • a first non- conductive layer is deposited and patterned on the substrate to define regions where the layer of magnetic material is to be fabricated.
  • a first electrolytic process as described above, is used to plate the layer of magnetic material on the substrate.
  • the electrolytic process for example, can be used to plate a cobalt-chromium (CoCr) film as the layer of magnetic material.
  • a second non-conductive layer may be deposited and masked on the substrate to define regions where the electrical leads are to be located. A second electrolytic process is then used to plate the electrical leads.
  • a multi-substrate memory device includes a plurality of substrates each formed from a voltage switchable dielectric material. The substrates are stacked and are electrically
  • the vias are plated with a current-carrying layer by an electrolytic process.
  • the vias can be plated during a fabrication step with one or more of the current- carrying formations formed on the surface of the respective substrates.
  • the plating on the surface of the vias is also less expensive to produce and more reliable than plated vias produced by previous methods, such as by seeding the surfaces of the vias or using adhesives.
  • Flex circuit board devices generally include a high density of electrical leads and components. Unfortunately, increasing the density of electrical and conductive elements can diminish the speed and/or capacity of the flex circuit board.
  • Embodiments of the invention provide a flex circuit board that advantageously uses a voltage switchable dielectric material to increase the density of electrical and conductive components on the flex circuit board.
  • a composition of a voltage switchable dielectric material is selected and molded into a flexible and thin circuit board.
  • a resist layer is patterned onto the substrate to define finely spaced regions, as above.
  • a voltage exceeding the characteristic voltage of the particular voltage switchable dielectric material is applied to the voltage switchable dielectric material and a current-carrying formation is plated to form leads and contacts in the finely spaced regions.
  • a voltage switchable dielectric material By using a voltage switchable dielectric material, current-carrying precursors are deposited directly on the surface of the substrate to form the current-carrying formation. This allows the current-carrying formation to have a reduced thickness in comparison to previous flex circuit board devices. Accordingly, the respective electrical and conductive elements on the surface of the flex circuit board can be thinner and spaced more closely together.
  • An application for a flex circuit board under an embodiment of the invention includes a print head for an ink jet style printer.
  • the use of a voltage switchable dielectric material enables the flex circuit board to have more finely spaced electrical components and leads resulting in increased printing resolution from the print head.
  • Yet another embodiment of the invention provides RFID tags.
  • the method of the invention can also be used to fabricate antennas and other circuitry on substrates for RFID and wireless chip applications.
  • a layer of a voltage switchable dielectric material can be used as an encapsulant.
  • a multilayer structure comprising:

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Abstract

L'invention concerne des systèmes et des procédés consistant à déposer au moins un matériau sur un matériau diélectrique à commutation de tension. Dans certains aspects, un matériau diélectrique à commutation de tension est disposé sur un fond de panier conducteur. Dans certains modes de réalisation, le matériau diélectrique comprend des zones présentant des tensions caractéristiques différentes associées au dépôt sur ledit matériau. Certains modes de réalisation consistent à réaliser un masquage, notamment au moyen d'un masque de contact amovible. Certains autres modes de réalisation consistent à réaliser un électro-greffage. Certains autres modes de réalisation encore concernent une couche intermédiaire disposée entre deux couches.
EP10830472A 2009-10-29 2010-10-28 Dépôt de métal Withdrawn EP2494856A1 (fr)

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US12/608,309 US20100040896A1 (en) 1999-08-27 2009-10-29 Metal Deposition
PCT/US2010/054569 WO2011059771A1 (fr) 2009-10-29 2010-10-28 Dépôt de métal

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AU6531600A (en) 1999-08-27 2001-03-26 Lex Kosowsky Current carrying structure using voltage switchable dielectric material
US20100038121A1 (en) * 1999-08-27 2010-02-18 Lex Kosowsky Metal Deposition
US20100038119A1 (en) * 1999-08-27 2010-02-18 Lex Kosowsky Metal Deposition
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KR20120095943A (ko) 2012-08-29
TW201125038A (en) 2011-07-16
WO2011059771A1 (fr) 2011-05-19
CN102714914A (zh) 2012-10-03
US20100040896A1 (en) 2010-02-18

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