Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• the invention relates to a power supply control device of a computer.
• the medium of electronic circuits and related components is an area that has grown particularly strongly.
• IPs parts
• SoC System on Chip
• the invention improves the situation.
• the invention proposes a device for controlling a computer capable of being powered on several voltage levels, comprising a controller arranged for receiving load, expiry, and instantaneous speed data for said calculator, for calculating a reference speed which enables said calculator to execute a computation quantity derived from the load data in a duration derived from the expiry data, and for calculating a voltage level and a control operating frequency for said computer from the reference speed.
• At least one of the reference speed and the operating frequency is calculated from the instantaneous speed data.
• This device is particularly advantageous because it makes it possible to issue power commands that are adapted to the logic requirements emitted by the operating system that uses the computer, while maximizing the energy consumption of the computer.
• FIG. 1 represents a generic view of a power control device according to the invention
• FIG. 2 represents a schematic diagram of an operating loop of the device of FIG. 1,
• FIG. 3 represents a first variant embodiment of the device of FIG. 1,
• FIG. 4 represents a second variant embodiment of the device of FIG. 1,
• FIG. 5 represents a third variant embodiment of the device of FIG. 1,
• FIG. 6 represents a fourth alternative embodiment of the device of FIG. 1;
• FIG. 7 represents another embodiment adapted to operate with a calculator comprising several cores, and
• FIG. 8 represents an alternative embodiment of the device of FIG. 7.
• the drawings and the description below contain, for the most part, elements of a certain character. They can therefore not only serve to better understand the present invention, but also contribute to its definition, if any.
• the invention finds particular application in CMOS circuits.
• CMOS circuits three main sources of energy consumption exist: the switching of the electrical doors of the circuit, the currents of short circuit, and - the currents of leakage.
• the instantaneous power of a given circuit can therefore be seen as the sum of these three powers, which is reflected by the formula (10) of Annex A.
• This formula shows the predominant role of the supply voltage V of the circuit. A solution to reduce consumption is therefore to lower the voltage.
• FIG. 1 shows a power control device 2 according to the invention.
• the device 2 controls the power supply of a computer 4.
• Computer any electronic system capable of performing logical operations in fact data processing or calculation.
• this includes, but is not limited to, processors, microprocessors, SoC chips, FPGA type programmable chips, and the like.
• the power control device 2 receives data Ci and Ni on the one hand and data w on the other hand.
• the data Ci and Ni respectively represent load data for the computer 4, and maturity data for the load data.
• the data Ci and Ni are received by the power control device 2 from a higher level logical layer, for example from the operating system which exploits the computer 4.
• the data w which is received by the power control device 2 represents the operational processing speed of the computer 4.
• This operational processing speed is used by the power control device 2 as feedback information to avoid any drift with respect to the instructions it emits.
• the computer 4 can be controlled in voltage and frequency. In fact, the computer 4 can operate at different voltage levels, at each voltage level corresponding to a range of possible operational frequencies. This voltage level V_lvl and the operating frequency f_op are outputs of the power control device 2.
• the computer 4 operates by clock cycles controlled by the operating frequency f_op.
• the power control device 2 operates in a similar manner.
• the power control device 2 operates by time period Ts, each period corresponding to the duration between two successive control calculations.
• the period Ts is generally of the order of several clock cycles of the computer 4.
• the controller 2 transmits the voltage level and operating frequency commands calculated in the previous period.
• the period Ts of the power control device 2 may be a fixed parameter which is chosen according to the calculator 4.
• This period can also be adapted dynamically, that is to say that it can be set to a multiple of the duration of a cycle of the computer 4.
• the multiplier has the value '10' (ten). However, this value could be set at higher multiples.
• the power control device 2 analyzes the data Ci, Ni, and w, and returns the data f_op and V_lvl to the computer 4.
• the power control device 2 sends power control data, and not the power supply itself.
• the portion of the circuit charged to power the computer 4 based on the control data from the power control device 2 is not discussed here.
• Fig. 2 shows an operating loop of the power control device 2. As discussed above, the power control device 2 operates by calculation periods.
• the operating loop of the power control device 2 therefore begins with an operation 20 in which the data Ci, Ni and w that will serve are received.
• the power control device 2 calculates a reference speed w_ref.
• the power control device 2 will therefore implement a dynamic control of the power supply of the computer 4 so as to comply with the following instructions: - to finish the calculation load before the expiry, and to minimize as much as possible the voltage used during this calculation.
• the power control device 2 starts at each period by calculating what is the "average" processing speed that the computer 4 should have to finish at the time indicated by the data. Ci data. Then, this average speed is optimized from an energy consumption point of view to obtain a reference speed w__ref.
• Average speed is here called delta. To calculate the delta velocity, equation 20 must be applied.
• the average speed is the amount of computation that remains to be processed, i.e. the load derived from the data Ci minus the amount of calculation that has already been processed, that is, ie, the sum of the instantaneous velocities w received multiplied by the time step of the power control device 2, divided by the time Li remaining before the expiry, which is designated by the data Ni.
• equation 20 amounts to writing that the average speed to have is the amount of data to be calculated minus the amount already calculated, all divided by the time remaining.
• Equations 30 and 32 show the application of equation 20 to the particular case of periodwise operation of the feeder 2.
• the power control device 2 will determine the reference speed w_ref.
• the principle of the reference speed is to note that it is advantageous to operate at maximum frequency for a given voltage level, in order to be able to go down from the voltage level as soon as possible.
• the power control device 2 determines whether this speed corresponds to the frequency range of the voltage level established in the previous period.
• the power control device 2 determines the voltage level which corresponds to the average delta speed.
• the appropriate voltage level is that for which the average delta velocity is just below the maximum velocity, and higher than the maximum velocity of the next voltage level.
• the power control device 2 proceeds in the same manner as described above to calculate the value of the reference speed w_ref.
• the power control device 2 calculates the operating frequency f_op which corresponds to the reference speed w_ref, and derives the corresponding voltage level V_lvl.
• the power control device 2 uses the data w to calculate the operational frequency f_op, using a system of order 1, according to the equations 40 and 42.
• Equation 40 shows the calculation of the "error” between the reference speed w_ref and the instantaneous speed w received from the computer 4, and the equation 42 shows how this error is used to calculate the operational frequency f_op of the time step next.
• Ts represents the period of the power control device 2
• K is a gain
• FIG. 3 represents an alternative embodiment of the power control device 2.
• the calculation of the reference speed w_ref is separated from that of the operating frequency f_op and the voltage level V_lvl.
• the power control device 2 thus comprises a reference speed calculation unit 6 and a control calculation unit 8.
• the reference speed calculation unit 6 receives the data Ci, Ni and w, and returns the reference speed w_ref.
• control calculation unit 8 receives the reference speed w_ref and the data w, and returns the operational frequency data f_op and voltage level V_lvl.
• the computer 4 is controlled on two voltage levels, respectively called VIo (the lowest) and Vhi (the highest).
• VIo the lowest
• Vhi the highest
• the part of the operation 30 which determines the speed w_ref is to compare the average speed delta with the maximum value of the frequency for the voltage level VIo. If delta is greater than this value, then w_ref receives the maximum frequency value of the Vhi level, and otherwise w_ref receives delta.
• the control calculation unit 8 can therefore use the most recent data to establish the operating frequency f_op and the voltage level V_lvl, which ensures better performance.
• the power control device shown in FIG. 4 represents a variant of the device of FIG. 3 in which the data w are only received by the reference speed calculation unit 6, and are transmitted to the calculation unit. order 8.
• control calculation unit 8 can operate with data w a little less recent than in the case of Figure 3.
• this embodiment has the advantage of being more simple to manufacture and implement.
• the power control device shown in FIG. 5 represents an even more simplified variant of the control device of FIG. 3, in which the instantaneous speed data w is transmitted only to the reference speed calculation unit. 6, the control calculation unit 8 receiving here only the reference speed data w_ref.
• the operation 40 is greatly simplified, since the operational frequency f_op is fixed with the value w_ref, and the voltage level V_lvl directly deduced from this value.
• This embodiment offers performance even a little lower in energy terms. On the other hand, it allows manufacture and implementation of a remarkable simplicity.
• the embodiment shown in FIG. 6 is a variant in which only the control calculation unit 8 receives the instantaneous speed data w.
• the reference speed calculation unit 6 only receives the reference speed data w ref that it has previously calculated.
• the calculation of the operating frequency f_op of the operation 40 implemented by the control calculation unit 8 is made more robust, with the use of a system of order 2.
• a first error is calculated according to the formula 50, and this error is integrated over the period of the reference velocity calculation unit 6 according to the formula 52.
• the operating frequency f_op is determined by means of the formula 54, in which ⁇ represents the time constant of the system once looped, and K is the gain.
• FIG. 7 represents a device 2 adapted to the control of a computer 14 which comprises several cores. This means that, within the computer 14, it contains in the example described four calculation units similar to the calculator 4 can be addressed independently.
• the calculator 14 may in other embodiments include as many cores as necessary, that is to say at least two and more than four, for example 32 or more.
• a first approach to solve this problem is to look for a level of tension and frequency that constitutes a "consensus". However, this is not acceptable because a critical task can not be executed in time.
• a second approach is to operate all the cores at the voltage level and the frequency of the most critical task. However, this tends to wipe out energy gains.
• a limiter 10 is introduced into the device 2.
• the function of the limiter 10 is to calculate for each heart the ratio between the frequency of the most critical task of all the tasks and the frequency that this heart should use to implement work its task in the mono-heart case.
• the ratios determined by the limiter 10 are used so that each heart performs its task at a speed that corresponds substantially to that it would have used in the single-core case.
• the computer 14 can integrate a hardware solution by means of a specific electronics that suspends the clock nodes 4 of the computer 14.
• each heart functions as in mono-core mode, but at a voltage level that can be higher (it depends on the critical task).
• clock-gating allows the transmission or non-transmission of the clock fronts to different nodes 4 of the computer 14 and can be achieved for example by means of a door AND.
• the electronics can be replaced by a software solution.
• we will "sleep" selectively, so that on a significant amount of cycles, each heart performs its task at a speed that corresponds substantially to that it would have used in the mono-heart case.
• This variant has the advantage of being more scalable, because software. This means that updating the firmware will allow it to evolve.
• the reference speed calculation 6 and the control calculation unit 8 are replicated as many times as there are cores.
• the instantaneous velocity data is a multiplet w_m and the reference velocity data w_m_ref is also a multiplet.
• the control calculation unit 8 transmits a multiplet of frequencies f_m and a multiplet of voltage levels V_m.
• the limiter 10 is disposed at the output of the control calculation unit 8. It therefore receives the frequency multiplet f_m and the multiplet of voltage levels V_m.
• the limiter 10 will compare all the frequencies of the multiplet f_m and select the highest. This frequency will be transmitted as f_op instruction to the computer 14 and the corresponding heart is called critical heart.
• the limiter 10 selects the voltage level of the multiplet V_m which corresponds to the critical core designated above. This voltage level will be transmitted as setpoint V_lvl to the computer 14.
• the limiter 10 calculates a multiplet rat_m which contains the ratio between each of the frequencies of the multiplet f_m and the frequency f_op.
• the Applicant has identified that an order of magnitude of the order of 1000 is advantageous in the context of the invention.
• the system which controls the tasks sent to the computer will operate with a frequency of the order of 1 kHz
• the control device of the invention will operate with a frequency of the order of 1 MHz
• the computer itself will operate with a frequency of the order of IGHz.
• the invention relates to the implementation of a power control of an electronic system that performs calculations.
• this command is made dynamic and adaptive through the use of order 1 and 2 systems.
• order system 1 and 2 is meant a system whose function which performs the calculation of the command includes a polynomial whose highest monomial is 1 or 2. Higher order systems could also be used.
• the power control device 2 has been described here as an element external to the computers 4 and 14, and separate therefrom. This means that the calculations that are implemented to calculate the power control are not performed within the calculator.
• the power control device 2 could be integrated in the computer, and the implementation of the calculations of the power control could then be performed by the computer 4 or 14, the control taking into account this calculation overhead.
• the Applicant has described a power control device in which the computer can be powered on several levels.
• a particular example has been described for a two-level voltage supply.
• a voltage level rise / fall loop is described to determine the adapted frequency range.
• the controller 2 can be simplified to contain only one block of calculation of the frequency and voltage levels, that is to say that the units 6 and 8 can be merged.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Power Sources (AREA)

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• 2009
  • 2009-03-31 FR FR0901576A patent/FR2943806A1/fr not_active Withdrawn
  • 2009-10-01 FR FR0904686A patent/FR2943807A1/fr not_active Withdrawn
• 2010
  • 2010-03-29 JP JP2012502730A patent/JP5519769B2/ja not_active Expired - Fee Related
  • 2010-03-29 CN CN2010800146751A patent/CN102378949A/zh active Pending
  • 2010-03-29 EP EP10713694A patent/EP2414909A2/fr not_active Ceased
  • 2010-03-29 US US13/262,087 patent/US20120110361A1/en not_active Abandoned
  • 2010-03-29 WO PCT/FR2010/000264 patent/WO2010112700A2/fr active Application Filing

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