EP2410562A4 - Semiconductor device, method for manufacturing same, electronic device and electronic component - Google Patents
Semiconductor device, method for manufacturing same, electronic device and electronic componentInfo
- Publication number
- EP2410562A4 EP2410562A4 EP09841905.4A EP09841905A EP2410562A4 EP 2410562 A4 EP2410562 A4 EP 2410562A4 EP 09841905 A EP09841905 A EP 09841905A EP 2410562 A4 EP2410562 A4 EP 2410562A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- electronic
- manufacturing same
- semiconductor device
- electronic component
- electronic device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H01L23/4985—Flexible insulating substrates
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Combinations Of Printed Boards (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009069091 | 2009-03-19 | ||
PCT/JP2009/067856 WO2010106703A1 (en) | 2009-03-19 | 2009-10-15 | Semiconductor device, method for manufacturing same, electronic device and electronic component |
Publications (3)
Publication Number | Publication Date |
---|---|
EP2410562A1 EP2410562A1 (en) | 2012-01-25 |
EP2410562A4 true EP2410562A4 (en) | 2014-09-24 |
EP2410562B1 EP2410562B1 (en) | 2016-04-13 |
Family
ID=42739369
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP09841905.4A Not-in-force EP2410562B1 (en) | 2009-03-19 | 2009-10-15 | Semiconductor device, method for manufacturing same, electronic device and electronic component |
Country Status (5)
Country | Link |
---|---|
US (3) | US9318425B2 (en) |
EP (1) | EP2410562B1 (en) |
JP (1) | JP5590027B2 (en) |
CN (1) | CN102356461B (en) |
WO (1) | WO2010106703A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10896898B2 (en) | 2015-10-28 | 2021-01-19 | Indiana Integrated Circuits, LLC | Edge interconnect self-assembly substrate |
US10182498B2 (en) * | 2015-10-28 | 2019-01-15 | Indiana Integrated Circuits, LLC | Substrates with interdigitated hinged edge interconnects |
US9806030B2 (en) | 2015-10-28 | 2017-10-31 | Indiana Integrated Circuits, LLC | Prototyping of electronic circuits with edge interconnects |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6050832A (en) * | 1998-08-07 | 2000-04-18 | Fujitsu Limited | Chip and board stress relief interposer |
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JP2005268544A (en) * | 2004-03-18 | 2005-09-29 | Nec Saitama Ltd | Substrate for connecting between substrates, and connecting structure between substrates |
EP1667225A1 (en) * | 2003-09-24 | 2006-06-07 | Ibiden Co., Ltd. | Interposer and multilayer printed wiring board |
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US20090121346A1 (en) * | 2007-11-08 | 2009-05-14 | Texas Instruments Incorporated | Flexible Interposer for Stacking Semiconductor Chips and Connecting Same to Substrate |
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JPH05114627A (en) | 1991-10-23 | 1993-05-07 | Hitachi Ltd | Semiconductor device |
JPH08236898A (en) | 1995-02-27 | 1996-09-13 | Matsushita Electric Ind Co Ltd | Stress relaxing connecting medium, stress relaxing mounting body and stress relaxing component |
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US6208521B1 (en) * | 1997-05-19 | 2001-03-27 | Nitto Denko Corporation | Film carrier and laminate type mounting structure using same |
JP4526651B2 (en) | 1999-08-12 | 2010-08-18 | 富士通セミコンダクター株式会社 | Semiconductor device |
US6710457B1 (en) * | 2000-10-20 | 2004-03-23 | Silverbrook Research Pty Ltd | Integrated circuit carrier |
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US7358444B2 (en) * | 2004-10-13 | 2008-04-15 | Intel Corporation | Folded substrate with interposer package for integrated circuit devices |
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2009
- 2009-10-15 JP JP2011504709A patent/JP5590027B2/en not_active Expired - Fee Related
- 2009-10-15 WO PCT/JP2009/067856 patent/WO2010106703A1/en active Application Filing
- 2009-10-15 EP EP09841905.4A patent/EP2410562B1/en not_active Not-in-force
- 2009-10-15 CN CN200980158127.3A patent/CN102356461B/en not_active Expired - Fee Related
-
2011
- 2011-08-18 US US13/212,467 patent/US9318425B2/en not_active Expired - Fee Related
-
2016
- 2016-03-07 US US15/062,477 patent/US9565755B2/en not_active Expired - Fee Related
- 2016-03-07 US US15/062,480 patent/US9585246B2/en not_active Expired - Fee Related
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US6050832A (en) * | 1998-08-07 | 2000-04-18 | Fujitsu Limited | Chip and board stress relief interposer |
US20030047801A1 (en) * | 2001-09-07 | 2003-03-13 | Nec Corporation | Semiconductor device and manufacturing method of the same |
EP1667225A1 (en) * | 2003-09-24 | 2006-06-07 | Ibiden Co., Ltd. | Interposer and multilayer printed wiring board |
EP1677349A1 (en) * | 2004-02-24 | 2006-07-05 | Ibiden Co., Ltd. | Substrate for mounting semiconductor |
JP2005268544A (en) * | 2004-03-18 | 2005-09-29 | Nec Saitama Ltd | Substrate for connecting between substrates, and connecting structure between substrates |
US20090121346A1 (en) * | 2007-11-08 | 2009-05-14 | Texas Instruments Incorporated | Flexible Interposer for Stacking Semiconductor Chips and Connecting Same to Substrate |
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Also Published As
Publication number | Publication date |
---|---|
US20160192498A1 (en) | 2016-06-30 |
US9565755B2 (en) | 2017-02-07 |
US9585246B2 (en) | 2017-02-28 |
JP5590027B2 (en) | 2014-09-17 |
EP2410562A1 (en) | 2012-01-25 |
CN102356461A (en) | 2012-02-15 |
US20110299255A1 (en) | 2011-12-08 |
WO2010106703A1 (en) | 2010-09-23 |
JPWO2010106703A1 (en) | 2012-09-20 |
CN102356461B (en) | 2014-05-07 |
EP2410562B1 (en) | 2016-04-13 |
US20160192479A1 (en) | 2016-06-30 |
US9318425B2 (en) | 2016-04-19 |
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