EP2346172B1

EP2346172B1 - Analog-to-digital converter and digital-to-analog converter

Info

Publication number: EP2346172B1
Application number: EP10195603A
Authority: EP
Inventors: Yasutaka Kanayama
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 2010-01-08
Filing date: 2010-12-17
Publication date: 2013-02-13
Anticipated expiration: 2030-12-17
Also published as: KR101200145B1; US20110169675A1; EP2346172A1; KR20110081778A; JP4864145B2; US8368573B2; JP2011142588A

Description

FIELD

The present invention generally relates to Analog-to-Digital (A/D) converters and Digital-to-Analog (D/A) converters, and more particularly to a sigma-delta (ΣΔ) modulation A/D converter and a ΣΔ modulation D/A converter.

BACKGROUND

US5908235 A refers to a second order Sigma-Delta based analog to digital converter having analog components and having a programmable comb filter coupled to the digital signal processor. The second order Sigma-Delta modulator comprises amplifiers which are class AB OTAs, which have cross coupled NMOS driven input stages, and cascoded output stages. The common mode voltages are biasing points, and these voltages are kept constant by a differential input stage, by a PV independent temperature dependent current generator, by device size, and by a common mode feedback circuitry. The programmable comb filter receives the coarsely digitized 1-bit output of the modulator at oversampling frequency FS, and provides a representation of the input signal to the DSP at sampling rate of FS/N. In addition, the comb filter uses a 20-bit data path to provide 16 bits of resolution to the DSP. The output of the programmable comb filter is then supplied to an FIR filter which is realized in the DSP.
US6304608 B1 refers to multibit sigma-delta converters. An N-level sigma-delta analog-to-digital converter includes an analog loop filter, an N-level quantizer, an element selection logic, an internal N-level digital-to-analog converter (DAC), and a decimation filter, where N is an integer greater than two. Adding k extra unit elements to the internal N-level DAC, which totally comprises (N-1+k) unit elements, shifts the sigma-delta modulator tones and intermodulation distortions outside the baseband, where k is a positive integer. A cyclical selection of (N-1+k) unit elements in the internal N-level DAC is in accordance with an element selection logic which receives an output of the N-level quantizer and produces a set of control signals for the element selection of the internal N-level DAC.
The paper "A 3.3-V Single-Poly CMOS Audio ADC Delta-Sigma Modulator with 98-dB Peak SINADand 105-dB Peak SFDR" by Eric Fogleman et al. relates to a second-order ΔΣ modulator for audio-band analog-to-digital conversion implemented in a 3.3-V, 0.5-µm, single-poly CMOS process using metal-metal capacitors that achieves 98-dB peak signal-to-noise-and-distortion ratio and 105-dB peak spurious-free dynamic range. The design uses a low-complexity, first-order mismatch shaping 33-level digital-to-analog converter and a 33-level flash analog-to-digital converter with digital common-mode rejection and dynamic element matching of comparator offsets.
The ΣΔ modulation A/D converter may improve the bit accuracy of the pass-band due to the effects of oversampling and noise shaping.
The oversampling refers to the sampling of an analog signal at a high sampling rate that is a multiple of several tens to several hundreds the sampling rate necessary for the pass-band. FIGS. 1A and 1B are diagrams for explaining scattering of quantization noise by oversampling. In FIGS. 1A and 1B, the ordinate indicates the noise level in arbitrary units, and the abscissa indicates the sampling frequency in arbitrary units. Further, fs₁ denotes the sampling frequency before the oversampling, and fs₂ denotes the sampling frequency after the oversampling. The noise illustrated in FIG. 1A may be scattered by the oversampling such that the quantization noise having a total amount that is constant is scattered in the wider frequency band illustrated in FIG. 1B, in order to obtain the effect of reducing the amount of noise included in the pass-band.
The noise shaping refers to the shaping and shifting of the quantization noise having a flat distribution into the high-frequency range. The ΣΔ modulator performs the noise shaping using a feedback circuit, but the noise shaping characteristic or the sharpness of the noise waveform after the noise shaping may be varied by the circuit structure thereof.
FIGS. 2A and 2B are diagrams for explaining an example of a first order ΣΔ modulation A/D converter that is used in a ΣΔ modulation A/D converter. FIG. 2A illustrates the structure of the first order ΣΔ modulator, and FIG. 2B illustrates a noise waveform after noise shaping by the first order ΣΔ modulator. In FIG. 2B, the ordinate indicates the noise level in arbitrary units, and the abscissa indicates the sampling frequency in arbitrary units. The first order ΣΔ modulator includes adders 1 and 2, an integrator 3, a comparator 4, and a 1-bit D/A converter 5 that are connected as illustrated in FIG. 2A. A digital output data Y(z) of the first order ΣΔ modulator with respect to an analog input data X(z) may be represented by Y(z) = z^-1X ( z ) + ( 1-z^-1) Q ( z ) , and the value of the noise shaping of the noise waveform corresponds to the term (1-z^-1) Q (z) , where Q(z) denotes the quantization noise.
FIGS. 3A and 3B are diagrams for explaining an example of a second order ΣΔ modulation A/D converter that is used in the ΣΔ modulation A/D converter. FIG. 3A illustrates the structure of the second order ΣΔ modulator, and FIG. 3B illustrates a noise waveform after noise shaping by the second order ΣΔ modulator. In FIG. 3B, the ordinate indicates the noise level in arbitrary units, and the abscissa indicates the sampling frequency in arbitrary units. The second order ΣΔ modulator includes adders 1, 2, 11 and 12, integrators 3 and 13, a comparator 4, a 1-bit D/A converter 5, and a multiplier 15 that are connected as illustrated in FIG. 3A. A digital output data Y(z) of the second order ΣΔ modulator with respect to an analog input data X(z) may be represented by Y(z) = z^-2X(z) + (1-z^-1)²Q(z), and the value of the noise shaping of the noise waveform corresponds to the term (1-z^-1)²Q(z), where Q(z) denotes the quantization noise.
The ΣΔ modulation A/D converter may have a structure including the ΣΔ modulator illustrated in FIG. 2 or FIG. 3, a digital lowpass filter (not illustrated), and a decimator (not illustrated), for example. In this case, the digital lowpass filter eliminates the quantization noise that is shifted in the high-frequency range by the ΣΔ modulator. The decimator decimates the output data of the digital lowpass filter, that has been eliminated of the quantization noise, in order to convert the analog data input to the ΣΔ modulator into high-precision digital data.
The ΣΔ modulator is also applicable to a ΣΔ modulation D/A converter. FIGS. 4 are diagrams for explaining an example of a second order ΣΔ modulation A/D converter that is used in the ΣΔ modulation D/A converter. FIG. 4A illustrates digital data input to the ΣΔ modulator, and FIG. 4B illustrates the structure of the ΣΔ modulator. The ΣΔ modulator includes adders 21, 22, 31 and 32, integrators 2 and 33, a comparator 24, a 16-bit A/D converter 25, and a multiplier 35 that are connected as illustrated in FIG. 4B. Q(z) denotes the quantization noise.
The digital data is input to the ΣΔ modulator, and the analog data is output from the ΣΔ modulator. The ΣΔ modulation D/A converter may have a structure including the ΣΔ modulator illustrated in FIG. 4B, an interpolator (not illustrated), and a D/A conversion and lowpass filter part (not illustrated), for example. In this case, the digital data input to the ΣΔ modulator is oversampled at a high rate by an interpolation performed by the interpolator. For example, the 16-bit digital data is converted into data of 1 bit or several bits by the digital processing of the ΣΔ modulator, in order to form a ΣΔ modulation D/A converter that is uneasily affected by inconsistencies in the characteristics of analog elements. In addiction, the high-frequency noise within the digital data may easily be eliminated by the D/A conversion and lowpass filter part.
The ΣΔ modulation A/D converter and the ΣΔ modulation D/A converter using the ΣΔ modulator described above may be utilized in various fields including audio equipments and measuring equipments, where high-precision A/D conversion or high-precision D/A conversion is required.
FIG. 5 is a diagram for explaining an example of the ΣΔ modulation A/D converter using the ΣΔ modulator. The ΣΔ modulation A/D converter includes an analog part 41 and a digital part 42. The analog part 41 includes a ΣΔ modulator 411, a Delay Flip-Flip (D-FF) 412, and a level converting part 413 including level converters 4131 and 4132, which are connected as illustrated in FIG. 5. The level converter 4131 is provided with respect to a clock signal, and the level converter 4132 is provided with respect to ΣΔ modulated data. The digital part 42 includes a lowpass filter 421, and a decimator 422 which are connected as illustrated in FIG. 5. For example, a power supply voltage Va = 5.0 V is supplied to the analog part 41, and a power supply voltage Vd = 1.8 V is supplied to the digital part 42. In FIG. 5, GNDa denotes the ground for the analog part 41, and GNDd denotes the-ground for the digital part 42. The level converting part 412 receives both the power supply voltage Va and the power supply voltage Vd.
FIG. 6 is a diagram for explaining an example of the ΣΔ modulation D/A converter using the ΣΔ modulator. The ΣΔ modulation D/A converter includes a digital part 51 and an analog part 52. The digital part 51 includes an interpolator 511, a ΣΔ modulator 512, and a D-FF 513 which are connected as illustrated in FIG. 6. In addition, the analog part 52 includes a level converting part 521, a D-FF 522, and a D/A conversion and lowpass filter part 523 which are connected as illustrated in FIG. 6. The level converting part 521 includes a level converter provided with respect to the clock signal, and a level converter provided with respect to the ΣΔ modulated data, similarly to the level converting part 413 illustrated in FIG. 5. For example, the power supply voltage Vd = 1.8 V is supplied to the digital part 51, and the power supply voltage Va = 5.0 V is supplied to the analog part 52. GNDd denotes the ground for the digital part 51, and GNDa denotes the ground for the analog part 52. The level converting part 521 receives both the power supply voltage Va and the power supply voltage Vd.
In the circuits illustrated in FIGS. 5 and 6 in which the analog part and the digital part coexist, the ground GNDa for the analog part and the ground GNDd for the digital part may be provided separately for the purposes of reducing the noise or reducing the power consumption. In this case, a level converting part is provided at an interface, and a delay circuit, such as a D-FF, is provided for clock signal synchronization. However, in the level converting part and the D-FF, a relatively large current may flow for an instant at a data transition point where the input data value makes a transition from "0" to "1" or makes a transition from "1" to "0", and the relatively large current may cause power supply noise of the power supply or the ground.
FIGS. 7A, 7B, and 7C are diagrams for explaining an example of the power supply noise generated at the data transition point. FIG. 7A illustrates the input data to the level converting part (413 or 521), and the power supply noise with respect to the analog part (41 or 52). FIG. 7B illustrates the input clock signal and the input data with respect to the D-FF (412 or 513), and the power supply noise with respect to the analog part (41 or 52). In FIGS. 7A and 7B, the ordinate indicates the signal level in arbitrary units, and the abscissa indicates the time in arbitrary units. In addition, FIG. 7C illustrates the ΣΔ modulated data output from the ΣΔ modulator (411 or 512), and a relative value of the amount of power supply noise with respect to the analog part (41 or 52).
The power supply noise with respect to the analog part includes a frequency component different from that of the ΣΔ modulated data, but as may be seen from FIGS. 8 through 10, the power supply noise component is dependent on the input data frequency or the clock signal frequency. FIG. 8 is a diagram illustrating an example of a ΣΔ modulated data spectrum for a case where the input data frequency is 1020 Hz, with the ordinate indicating the signal level and the abscissa indicating the frequency. FIG. 9 is a diagram illustrating an example of a power supply noise spectrum for the case where the input data frequency is 1020 Hz, with the ordinate indicating the relative value of the noise level and the abscissa indicating the frequency. FIG. 10 is a diagram illustrating an example of an output signal spectrum affected by power supply noise for the case where the input data frequency is 1020 Hz, with the ordinate indicating the signal level and the abscissa indicating the frequency. In FIG. 8 and the like, a 32k-mode signal is subjected to a 64-times oversampling, for example, and the oversampling frequency is 2.048 MHz.
In the ΣΔ modulation A/D converter, the power supply noise may generate an error in the sampling value of the input analog data. In this case, the ΣΔ modulated data may include the power supply noise component.
On the other hand, in the ΣΔ modulation D/A converter, the power supply noise may mix into the output analog data. In this case, if the ΣΔ modulation D/A converter is used in an audio equipment, for example, the power supply noise that mixes into the output analog data may be heard as non-negligible noise.
Recently, a method has been proposed to output a multi-valued output having three or more values from the comparator of the ΣΔ modulator, instead of a binary output that is "0" or "1", particularly for use in the ΣΔ modulation D/A converter. When the multi-valued output having three or more values is output from the comparator, it is possible to reduce the noise component corresponding to the term (1-z^-1)Q(z) in FIGS. 2A and 2B. FIGS. 11A and 11B are diagrams for explaining quantization noise for a case where the comparator output is the binary output and a 11-valued output, with the amount of noise indicated in arbitrary units. FIG. 11A illustrates the quantization noise Q for the case where the binary output is output from the comparator, and FIG. 11B illustrates the quantization noise Q for the case where the 11-valued output is output from the comparator. As may be seen from a comparison of FIGS. 11A and 11B, the amount of the quantization noise Q for the 11-valued output of the comparator is smaller than the amount of the quantization noise Q for the binary output of the comparator.
However, the inconsistencies in the characteristics of the analog elements, which do not greatly affect the ΣΔ modulation D/A converter when the comparator outputs the binary output, may cause non-negligible effects when the comparator outputs the multi-valued output having three or more values. For this reason, it may be desirable to average the inconsistencies in the characteristics of the analog elements by employing a technique such as the Dynamic Element Matching (DEM). In one example of the DEM, the analog element that is used is shifted one analog element at a time, as illustrated in FIG. 12A. FIGS . 12A and 12B are diagrams for explaining an example of the DEM. FIG. 12A illustrates the ΣΔ modulated data, and FIG. 12B illustrates the power supply noise. In FIGS. 12A and 12B, it is assumed for the sake of convenience that the ΣΔ modulated data includes'10 bits DT01 through DT10, and the value of the ΣΔ modulated data changes as MD1 → MD2 → MD3 → MD4, that is, changes as 4 → 5 → 5 → 4.
When the value of the ΣΔ modulated data changes as MD1 → MD2, a number of logic inversions (or the amount of data change) becomes "3" as indicated by hatching in FIG. 12A. When the ΣΔ modulation changes as MD2 → MD3, the number of logic inversions becomes "2" as indicated by the hatching in FIG. 12A. In addition, when the value of the ΣΔ modulated data changes from MD3 → D4, the number of logic inversions becomes "1", as indicated by the hatching in FIG. 12A. FIG. 12B illustrates the power supply noise for the case where the number of logic inversions is "3", "2", and "1". In FIG. 12B, the ordinate indicates the noise level in arbitrary units, and the abscissa indicates the time in arbitrary units.
When the multi-valued output of the comparator has three or more values, the number of level converting parts, the number of the D-FFs and the like that are used become larger than those used in the case where the comparator outputs the binary output. Consequently, the circuit scale increases even when the DEM or the like is employed, and the power supply noise tends to increase with the increase in the circuit scale for the case where the comparator outputs the multi-valued output having three or more values. The power supply noise component for the case where the comparator outputs the multi-valued output having three or more values is dependent on the input data frequency or the clock signal frequency, similarly to the case where the comparator outputs the binary output, as may be seen from FIGS. 13 through 15 which illustrate the case where the comparator outputs the 11-valued output. FIG. 13 is a diagram illustrating an example of a ΣΔ modulated data spectrum for the case where the input data frequency is 1020 Hz, with the ordinate indicating the signal level and the abscissa indicating the frequency. FIG. 14 is a diagram illustrating an example of a power supply noise spectrum for the case where the input data frequency is 1020 Hz, with the ordinate indicating the relative value of the noise level and the abscissa indicating the frequency. In addition, FIG. 15 is a diagram illustrating an example of an output signal spectrum affected by the power supply noise for the case where the input data frequency is 1020 Hz, with the ordinate indicating the signal level and the abscissa indicating the frequency.
Japanese Laid-Open Patent Publications No. 6-232857 and No. 3-101411 relate to technological background.
According to the above described A/D converters and D/A converters, it is difficult to reduce the noise, as described above.

SUMMARY

Accordingly, it is an object in one aspect of the embodiment to provide an A/D converter and a D/A converter, in which the noise may be reduced using a relatively simple structure.
One aspect of the present invention is to provide an analog-to-digital converter comprising a ΣΔ modulator configured to receive analog data and to output ΣΔ modulated data; an adjusting circuit configured to generate dummy data, adjust a sum of an amount of change of the ΣΔ modulated data output from the ΣΔ modulator and an amount of change of the dummy data to be constant by outputting an inverted value of the dummy data of one clock before as present output data if the ΣΔ modulated data does not change, and by outputting the dummy data of one clock before as the present dummy output data if the ΣΔ modulated data changes; and a level converting part including a first level converter configured to receive the ΣΔ modulated data and to output level converted ΣΔ modulated data by converting a level of the ΣΔ modulated data, and a second level converter configured to receive the dummy data output from the adjusting circuit and to cancel a frequency dependence of noise with respect to the ΣΔ modulated data by interpolating dummy noise, wherein the ΣΔ modulator, the adjusting circuit and the level converting part receive a common clock signal.
According to one aspect of the present invention, there is provided a digital-to-analog converter comprising a ΣΔ modulator configured to receive digital data and to output ΣΔ modulated data; an adjusting circuit configured to generate dummy data, adjust a sum of an amount of change of the ΣΔ modulated data output from the ΣΔ modulator and an amount of change of the dummy data to be constant by outputting an inverted value of the dummy data of one clock before as present output data if the ΣΔ modulated data does not change, and by outputting the dummy data of one clock before as the present dummy output data if the ΣΔ modulated data changes; and a level converting part including a first level converter configured to receive the ΣΔ modulated data and to output the level converted ΣΔ modulated data by converting a level of the ΣΔ modulated data, and a second level converter configured to receive the dummy data output from the adjusting circuit and to cancel a frequency dependence of noise with respect to the ΣΔ modulated data by interpolating dummy noise, wherein the ΣΔ modulator, the adjusting circuit and the level converting part receive a common clock signal.
The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are diagrams for explaining scattering of quantization noise by the oversampling;
FIGS. 2A and 2B are diagrams for explaining an example of a first order ΣΔ modulation A/D converter that is used in a ΣΔ modulation A/D converter;
FIGS. 3A and 3B are diagrams for explaining an example of a second order ΣΔ modulation A/D converter that is used in the ΣΔ modulation A/D converter;
FIGS. 4A and 4B are diagrams for explaining an example of a second order ΣΔ modulation A/D converter that is used in a ΣΔ modulation D/A converter;
FIG. 5 is a diagram for explaining an example of the ΣΔ modulation A/D converter using the ΣΔ modulator;
FIG. 6 is a diagram for explaining an example of the ΣΔ modulation D/A converter using the ΣΔ modulator;
FIGS. 7A, 7B, and 7C are diagrams for explaining an example of power supply noise generated at a data transition point;
FIG. 8 is a diagram illustrating an example of a ΣΔ modulated data spectrum;
FIG. 9 is a diagram illustrating an example of a power supply noise spectrum;
FIG. 10 is a diagram illustrating an example of an output signal spectrum affected by power supply noise;
FIGS. 11A and 11B are diagrams for explaining quantization noise for a case where a comparator output is a binary output and a 11-valued output;
FIGS. 12A and 12B are diagrams for explaining an example of Dynamic Element Matching (DEM);
FIG. 13 is a diagram illustrating an example of a ΣΔ modulated data spectrum;
FIG. 14 is a diagram illustrating an example of a power supply noise spectrum;
FIG. 15 is a diagram illustrating an example of an output signal spectrum affected by power supply noise;
FIG. 16 is a diagram for explaining an A/D converter in a first embodiment of the present invention;
FIG. 17 is a diagram for explaining a D/A converter in the first embodiment of the present invention;
FIGS. 18A, 18B, and 18C are diagrams for explaining an example of power supply noise generated at a data transition point;
FIG. 19 is a diagram for explaining an A/D converter in a second embodiment of the present invention; and
FIG. 20 is a diagram for explaining a D/A converter in the second embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

Preferred embodiments of the present invention will be described with reference to the accompanying drawings.
According to one aspect of the present invention, the disclosed A/D converter includes an adjusting circuit and a level converting part. The adjusting circuit adjusts a total of an amount of change of ΣΔ modulated data output from a ΣΔ modulator which receives analog data, and an amount of change of dummy data, to become constant. The level converting part includes a first level converter that outputs the ΣΔ modulated data by converting the level of the ΣΔ modulated data, and a second level converter that receives the dummy data from the adjusting circuit and interpolates the dummy noise, in order to cancel the frequency dependence of the noise with respect to the ΣΔ modulated data by the second level converter.
According to one aspect of the present invention, the disclosed D/A converter includes an adjusting circuit and a level converting part. The adjusting circuit adjusts a total of an amount of change of ΣΔ modulated data output from a ΣΔ modulator which receives digital data, and an amount of change of dummy data, to become constant. The level converting part includes a first level converter that outputs the ΣΔ modulated data by converting the level of the ΣΔ modulated data, and a second level converter that receives the dummy data from the adjusting circuit and interpolates the dummy noise, in order to cancel the frequency dependence of the noise with respect to the ΣΔ modulated data by the second level converter.
The frequency dependence of the noise with respect to the ΣΔ modulated data may be cancelled by providing a dummy digital element, such as the level converter that interpolates the dummy noise dependent on the input data frequency or the clock signal frequency.
A description will now be given of the A/D converter and the D/A converter in each embodiment according to the present invention.

(First Embodiment)

FIG. 16 is a diagram for explaining the A/D converter in a first embodiment of the present invention. In FIG. 16, those parts that are the same as those corresponding parts in FIG. 5 are designated by the same reference numerals, and a description thereof will be omitted.
FIG. 16 illustrates a ΣΔ modulation A/D converter using a ΣΔ modulator. The ΣΔ modulation A/D converter includes an analog part 141-1 and a digital part 142-1. The analog part 141-1 includes a ΣΔ modulator 411, an adjusting circuit 61-1 configured to maintain power supply noise constant, Delay Flip-Flops (D-FFs) 62 and 63, and level converters 64, 65 and 66 that are connected as illustrated in FIG. 16. The level converters 64, 65 and 66 form a level converting part. The D-FF 62 corresponds to the D-FF 412 illustrated in FIG. 5, and the level converters 64 and 65 correspond to the level converters 4131 and 4132 illustrated in FIG. 5. The D-FF 63 forms a dummy D-FF provided with respect to the D-FF 62, and the level converter 66 forms a dummy level converter provided with respect to the level converter 65.
On the other hand, the digital part 142-1 includes a lowpass filter 421 and a decimator 422 that are connected as illustrated in FIG. 16. For example, a power supply voltage Va = 5.0 V is supplied to the analog part 141-1, and a power supply voltage Vd = 1.8 V is supplied to the digital part 142-1. GNDa denotes the ground for the analog part 141-1, and GNDd denotes the ground for the digital part 142-1.
The adjusting circuit 61-1 includes D- FFs 71 and 72, an exclusive-NOR (XNOR) circuit 73, and an exclusive-OR (XOR) circuit 74 that are connected as illustrated in FIG. 16. The XOR circuit 74 outputs the dummy data (or dummy signal), as will be described later. The XNOR circuit 73 obtains an exclusive-NOR between the present (or current) ΣΔ modulated data and the ΣΔ modulated data of one clock before in order to observe the amount of change of the ΣΔ modulated data from the ΣΔ modulator 411. The output data of the XNOR circuit 73 is supplied to one input of the XOR circuit 74. The output data of the XNOR circuit 73 has a data value "1" if two successive ΣΔ modulated data have the same data value "0" or "1" (that is, the data value does not change), and has a data value "0" if the two successive ΣΔ modulated data make a transition from "0" to "1" or from "1" to "0" (that is, the data value changes). The XOR circuit 74 obtains an exclusive-OR between the output data of the XNOR circuit 73 and the output dummy data of the XOR circuit 74 of one clock before. The present (or current) output dummy data of the XOR circuit 74 is supplied to the D-FF 63.
An inverted value of the dummy data of one clock before becomes the present output data if the ΣΔ modulated data does not change (that is, makes no transition). On the other hand, the dummy data of one clock before becomes the present output data if the ΣΔ modulated data changes (that is, makes a transition). For this reason, the adjusting circuit 61-1 may carry out a control so that a sum of the amount of change of the ΣΔ modulated data and the amount of change of the dummy data becomes "1", in order to maintain the power supply noise constant. In addition, even in the case where the ΣΔ modulator outputs the multi-valued output having three or more values, the power supply noise may be maintained constant by providing the structure described above in multiple. In other words, the frequency dependence of the power supply noise with respect to the ΣΔ modulated data may be cancelled by providing the dummy digital elements, such as the D-FF and the level converter, which interpolate dummy power supply noise dependent on the input data frequency or the clock signal frequency.
FIG. 17 is a diagram for explaining the D/A converter in the first embodiment of the present invention. In FIG. 17, those parts that are the same as those corresponding parts in FIG. 6 are designated by the same reference numerals, and a description thereof will be omitted.
FIG. 17 illustrates a ΣΔ modulation D/A converter using a ΣΔ modulator. The ΣΔ modulation D/A converter includes a digital part 151-1 and an analog part 152-1. The digital part 151-1 includes an interpolator 511, a ΣΔ modulator 512, an adjusting circuit 81-1 configured to maintain power supply noise constant, and Delay Flip-Flops (D-FFs) 82 and 83 that are connected as illustrated in FIG. 17. The D-FF 82 corresponds to the D-FF 513 illustrated in FIG. 6. The D-FF 83 forms a dummy D-FF provided with respect to the D-FF 82.
On the other hand, the analog part 152-1 includes level converters 91, 92 and 93, D- FFs 94 and 95, and a D/A conversion and lowpass filter part 523 that are connected as illustrated in FIG. 17. The level converters 91, 92 and 93 form a level converting part. The level converters 91 and 92 correspond to the two level converters within the level converting part 521 illustrated in FIG. 6. The level converter 93 forms a dummy level converter provided with respect to the level converter 92. The D-FF 94 corresponds to the D-FF 522 illustrated in FIG. 6. The D-FF 95 forms a dummy D-FF provided with respect to the D-FF 94. For example, a power supply voltage Vd = 1.8 V is supplied to the digital part 151-1, and a power supply voltage Va = 5.0 V is supplied to the analog part 152-1. GNDd denotes the ground for the digital part 151-1, and GNDa denotes the ground for the analog part 152-1.
The adjusting circuit 81-1 includes D- FFs 71 and 72, an exclusive-NOR (XNOR) circuit 73, and an exclusive-OR (XOR) circuit 74 that are connected as illustrated in FIG. 17. The XOR circuit 74 outputs the dumpy data (or dummy signal), as will be described later. The XNOR circuit 73 obtains an exalusive-NOR between the present (or current) ΣΔ modulated data and the ΣΔ modulated data of one clock before in order to observe the amount of change of the ΣΔ modulated data from the ΣΔ modulator 512. The output data of the XNOR circuit 73 is supplied to one input of the XOR circuit 74. The output data of the XNOR circuit 73 has a data value "1" if two successive ΣΔ modulated data have the same data value "0" or "1" (that is, the data value does not change), and has a data value "0" if the two successive ΣΔ modulated data make a transition from "0" to "1" or from "1" to "0" (that is, the data value changes). The XOR circuit 74 obtains an exclusive-OR between the output data of the XNOR circuit 73 and the output dummy data of the XOR circuit 74 of one clock before. The present (or current) output dummy data of the XOR circuit 74 is supplied to the D-FF 83. Hence, the structure of the adjusting circuit 81-1 may be the same as the structure of the adjusting circuit 61-1 illustrated in FIG. 16.
An inverted value of the dummy data of one clock before becomes the present output data if the ΣΔ modulated data does not change (that is, makes no transition). On the other hand, the dummy data of one clock before becomes the present output data if the ΣΔ modulated data changes (that is, makes a transition). For this reason, the adjusting circuit 81-1 may carry out a control so that a sum of the amount of change of the ΣΔ modulated data and the amount of change of the dummy data becomes "1", in order to maintain the power supply noise constant. In addition, even in the case where the ΣΔ modulator outputs the multi-valued output having three or more values, the power supply noise may be maintained constant by providing the structure described above in multiple. In other words, the frequency dependence of the power supply noise with respect to the ΣΔ modulated data may be cancelled by providing the dummy digital elements, such as the D-FF and the level converter, which interpolate dummy power supply noise dependent on the input data frequency or the clock signal frequency.
In the circuits illustrated in FIGS. 16 and 17 in which the analog part and the digital part coexist, the ground GNDa for the analog part and the ground GNDd for the digital part may be provided separately for the purposes of reducing the noise or reducing the power consumption. In this case, a level converting part (or level converter) may be provided at an interface, and a delay circuit, such as a D-FF, is provided for clock signal synchronization. However, in the level converting part and the D-FF, a relatively large current may flow for an instant at a data transition point where the input data value makes a transition from "0" to "1" or makes a transition from "1" to "0", and the relatively large current may cause the power supply noise of the power supply or the ground. In other words, the power supply noise with respect to the analog part includes a frequency component different from that of the ΣΔ modulated data, but the power supply noise is dependent on the input data frequency or the clock signal frequency. In this embodiment, the dummy digital elements, such as the D-FF and the level converters are provided to interpolate the dummy power supply noise that is dependent on the input data frequency or the clock signal frequency, in order to cancel the frequency dependence of the power supply noise with respect to the ΣΔ modulated data.
FIGS. 18A, 18B, and 18C are diagrams for explaining an example of the power supply noise generated at the data transition point. FIG. 18A illustrates the input data to the level converter (65 or 92) and the power supply noise with respect to the analog part (141-1 or 152-1), the input dummy data of the level converter (66 or 93) and the dummy power supply noise with respect to the analog part (141-1 or 152-1), and the total (or combined) power supply noise corresponding to the total (or combination) of the power supply noise with respect to the input data and the dummy power supply noise with respect to the input dummy data. FIG. 18B illustrates the input clock signal and the input data with respect to the D-FF (62 or 94) and the power supply noise with respect to analog part (141-1 or 152-1), the input dummy data to the D-FF (63 or 95) and the dummy power supply noise with respect to the analog part (141-1 or 152-1), and the total (or combined) power supply noise corresponding to the total (or combination) of the power supply noise with respect to the input data and the dummy power supply noise with respect to the input dummy data. In FIGS. 18A and 18B, the ordinate indicates the signal level in arbitrary units, and the abscissa indicates the time in arbitrary units. In addition, FIG. 18C illustrates the ΣΔ modulated data output from the ΣΔ modulator (411 or 512), the relative value of the amount of power supply noise with respect to the analog part (141-1 or 152-1), the dummy data, the amount of dummy power supply noise, and the total amount of power supply noise corresponding to the total (or combination) of the amount of power supply noise and the amount of dummy power supply noise. It was also confirmed from FIGS. 18A through 18C that the frequency dependence of the power supply noise with respect to the ΣΔ modulated data may be cancelled by interpolating the dummy power supply noise dependent on the input data frequency of the clock signal frequency.

(Second Embodiment)

FIG. 19 is a diagram for explaining the A/D converter in a second embodiment of the present invention. In FIG. 19, those parts that are the same as those corresponding parts in FIG. 16 are designated by the same reference numerals, and a description thereof will be omitted.
An adjusting circuit 61-2 includes D- FFs 71 and 72, an exclusive-OR (XOR) circuit 75, and an exclusive-NOR (XNOR) circuit 76 that are connected as illustrated in FIG. 19. The XNOR circuit 76 outputs the dummy data (or dummy signal), as will be described later. The XOR circuit 75 obtains an exclusive-OR between the present (or current) ΣΔ modulated data and the ΣΔ modulated data of one clock before in order to observe the amount of change of the ΣΔ modulated data from the ΣΔ modulator 411. The output data of the XOR circuit 75 is supplied to one input of the XNOR circuit 76. The output data of the XOR circuit 75 has a data value "0" if two successive ΣΔ modulated data have the same data value "0" or "1" (that is, the data value does not change), and has a data value "1" if the two successive ΣΔ modulated data make a transition from "0" to "1" or from "1" to "0" (that is, the data value changes). The XNOR circuit 76 obtains an exclusive-NOR between the output data of the XOR circuit 75 and the output dummy data of the XNOR circuit 76 of one clock before. The present (or current) output dummy data of the XNOR circuit 76 is supplied to the D-FF 63.
An inverted value of the dummy data of one clock before becomes the present output data if the ΣΔ modulated data does not change (that is, makes no transition). On the other hand, the dummy data of one clock before becomes the present output data if the ΣΔ modulated data changes (that is, makes a transition). For this reason, the adjusting circuit 61-2 may carry out a control so that a sum of the amount of change of the ΣΔ modulated data and the amount of change of the dummy data becomes "1", in order to maintain the power supply noise constant. In addition, even in the case where the ΣΔ modulator outputs the multi-valued output having three or more values, the power supply noise may be maintained constant by providing the structure described above in multiple. In other words, the frequency dependence of the power supply noise with respect to the ΣΔ modulated data may be cancelled by providing the dummy digital elements, such as the D-FF and the level converter, which interpolate dummy power supply noise dependent on the input data frequency or the clock signal frequency.
FIG. 20 is a diagram for explaining the D/A converter in the second embodiment of the present invention. In FIG. 20, those parts that are the same as those corresponding parts in FIG. 17 are designated by the same reference numerals, and a description thereof will be omitted.
An adjusting circuit 81-2 includes D- FFs 71 and 72, an exclusive-OR (XOR) circuit 75, and an exclusive-NOR (XNOR) circuit 76 that are connected as illustrated in FIG. 20. The XNOR circuit 76 outputs the dummy data (or dummy signal), as will be described later. The XOR circuit 75 obtains an exclusive-OR between the present (or current) ΣΔ modulated data and the ΣΔ modulated data of one clock before in order to observe the amount of change of the ΣΔ modulated data from the ΣΔ modulator 512. The output data of the XOR circuit 75 is supplied to one input of the XNOR circuit 76. The output data of the XOR circuit 75 has a data value "0" if two successive END modulated data have the same data value "0" or "1" (that is, the data value does not change), and has a data value "1" if the two successive ΣΔ modulated data make a transition from "0" to "1" or from "1" to "0" (that is, the data value changes). The XNOR circuit 76 obtains an exclusive-NOR between the output data of the XOR circuit 75 and the output dummy data of the XNOR circuit 76 of one clock before. The present (or current) output dummy data of the XOR circuit 76 is supplied to the D-FF 83. Hence, the structure of the adjusting circuit 81-2 may be the same as the structure of the adjusting circuit 61-2 illustrated in FIG. 19.
An inverted value of the dummy data of one clock before becomes the present output data if the ΣΔ modulated data does not change (that is, makes no transition). On the other hand, the dummy data of one clock before becomes the present output data if the ΣΔ modulated data changes (that is, makes a transition). For this reason, the adjusting circuit 81-2 may carry out a control so that a sum of the amount of change of the ΣΔ modulated data and the amount of change of the dummy data becomes "1", in order to maintain the power supply noise constant. In addition, even in the case where the ΣΔ modulator outputs the multi-valued output having three or more values, the power supply noise may be maintained constant by providing the structure described above in multiple. In other words, the frequency dependence of the power supply noise with respect to the ΣΔ modulated data may be cancelled by providing the dummy digital elements, such as the D-FF and the level converter, which interpolate dummy power supply noise dependent on the input data frequency or the clock signal frequency.
In the circuits illustrated in FIGS. 19 and 20 in which the analog part and the digital part coexist, the ground GNDa for the analog part and the ground GNDd for the digital part may be provided separately for the purposes of reducing the noise or reducing the power consumption. In this case, a level converting part (or level converter) may be provided at an interface, and a delay circuit, such as a D-FF, is provided for clock signal synchronization. However, in the level converting part and the D-FF, a relatively large current may flow for an instant at a data transition point where the input data value makes a transition from "0" to "1" or makes a transition from "1" to "0", and the relatively large current may cause the power supply noise of the power supply or the ground. In other words, the power supply noise with respect to the analog part includes a frequency component different from that of the ΣΔ modulated data, but the power supply noise is dependent on the input data frequency or the clock signal frequency. In this embodiment, the dummy digital elements, such as the D-FF and the level converter, are provided to interpolate the dummy power supply noise that is dependent on the input data frequency or the clock signal frequency, in order to cancel the frequency dependence of the power supply noise with respect to the ΣΔ modulated data.

(Modification)

The amount of power supply noise may also differ depending on a physical distance and the like of the element from the power supply or the ground. For this reason, it may be desirable in each of the embodiments described above to arrange the dummy digital elements, such as the dummy D-FF and the dummy level converter, adjacent to (or close to) the digital elements, such as the D-FF and the level converter, that are provided within the analog part or the digital part. In addition, in the case where the multi-valued ΣΔ modulated data has three or more values, it may be desirable to employ a layout in which the digital element and the corresponding dummy digital element are alternately arranged. In this case, it may be desirable for each digital element and the corresponding dummy digital element to use the same power supply or the same ground, and it may be desirable to maintain the wiring distances of the digital element and the corresponding digital element from the power supply or the ground to be the same.
Although the embodiments are numbered with, for example, "first," "second," or "third," the ordinal numbers do not imply priorities of the embodiments.

Claims

An analog-to-digital converter comprising:
a ΣΔ modulator (411) configured to receive analog data and to output ΣΔ modulated data;

characterised by

an adjusting circuit (61-1, 61-2) configured to generate dummy data,
adjust a sum of an amount of change of the ΣΔ modulated data output from the ΣΔ modulator and an amount of change of the dummy data to be constant by

outputting an inverted value of the dummy data of one clock before as present summy output data if the ΣΔ modulated data does not change, and by outputting the dummy data of one clock before as the present dummy output data if the ΣΔ modulated data changes; and

a level converting part (64, 65, 66) including
a first level converter (64, 65) configured to receive the ΣΔ modulated data and to output level converted ΣΔ modulated data by converting a level of the ΣΔ modulated data, and

a second level converter (66) configured to receive the dummy data output from the adjusting circuit and to cancel a frequency dependence of power supply noise with respect to the ΣΔ modulated data by interpolating dummy noise,

wherein the ΣΔ modulator, the adjusting circuit and the level converting part receive a common clock signal.
The analog-to-digital converter as claimed in claim 1, further comprising:
a first delay circuit (62) coupled between the ΣΔ modulator and the first level converter; and

a second delay circuit (63) coupled between the adjusting circuit and the second level converter,

wherein the first delay circuit and the second delay circuit receive the common clock signal, and

the second delay circuit as well as the second level converter are configured to cancel the frequency dependence of the power supply noise with respect to the ΣΔ modulated data by interpolating the dummy noise.
The analog-to-digital converter as claimed in any of claims 1 to 2, wherein the first level converter and the second level converter receive a common power supply voltage.
The analog-to-digital converter as claimed in any of claims 1 to 3, further comprising:
a digital lowpass filter (421) configured to receive data output from the first level converter, and to eliminate quantization noise shifted in a high-frequency range by the ΣΔ modulator.
The analog-to-digital converter as claimed in claim 4, further comprising:
an decimator (422) configured to decimate output data of the digital lowpass filter, eliminated of the quantization noise, to have a predetermined sampling rate.
A digital-to-analog converter comprising:
a ΣΔ modulator (512) configured to receive digital data and to output ΣΔ modulated data;

characterised by

an adjusting circuit (81-1, 81-2) configured to generate dummy data,
adjust a sum of an amount of change of the ΣΔ modulated data output from the ΣΔ modulator and an amount of change of the dummy data to be constant by

outputting an inverted value of the dummy data of one clock before as present dummy output data if the ΣΔ modulated data does not change, and by outputting the dummy data of one clock before as the present dummy output data if the ΣΔ modulated data changes; and

a level converting part (91, 92, 93) including
a first level converter (91, 92) configured to receive the ΣΔ modulated data and to output the level converted ΣΔ modulated data by converting a level of the ΣΔ modulated data, and

a second level converter (93) configured to receive the dummy data output from the adjusting circuit and to cancel a frequency dependence of power supply noise with respect to the ΣΔ modulated data by interpolating dummy noise,

wherein the ΣΔ modulator, the adjusting circuit and the level converting part receive a common clock signal.
The digital-to-analog converter as claimed in claim 6, further comprising:
a first delay circuit (82) coupled between the ΣΔ modulator and the first level converter; and

a second delay circuit (83) coupled between the adjusting circuit and the second level converter,

wherein the first delay circuit and the second delay circuit receive the common clock signal, and

the second delay circuit as well as the second level converter are configured to cancel the frequency dependence of the power supply noise with respect to the ΣΔ modulated data by interpolating the dummy noise.
The digital-to-analog converter as claimed in any of claims 6 to 7, wherein the first level converter and the second level converter receive a common power supply voltage.
The digital-to-analog converter as claimed in any of claims 6 to 8, further comprising:
an interpolator (511) configured to interpolate the input digital data before supplying the same to the ΣΔ modulator, so that the ΣΔ modulator carries out an oversampling.
The digital-to-analog converter as claimed in any of claims 6 to 9, further comprising:
a digital-to-analog conversion and lowpass filter part (523) configured to receive data output from the first level converter.
The digital-to-analog converter as claimed claim 10, further comprising:
a delay circuit (94) coupled between the first level converter and the digital-to-analog conversion and lowpass filter part.