JP2014112775A - Cascade δς modulator and digital-analog converter with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cascade ΔΣ modulator and a digital-analog converter therewith which have a smaller digital area than existing ΔΣ modulator configurations.SOLUTION: A digital-analog converter 2 includes a cascade ΔΣ modulator 30, and a switched capacitor circuit 40 connected to the cascade ΔΣ modulator 30. The cascade ΔΣ modulator 30 includes a first modulator 31, a first multiplier 32 for multiplying quantization noise of the first modulator by a factor of K, a second modulator 33 connected to the first multiplier, and a plurality of differentiators 34 connected to the second modulator and cascade-connected according to the order. The order of the first modulator is the same value as the order of the differentiators. The switched capacitor circuit 40 includes a second multiplier 41 for multiplying an output of the differentiators 34 by a factor of 1/K, and an adder 42.

Description

  The present invention relates to a cascade ΔΣ modulator and a digital-analog converter thereof, and more specifically, a cascade ΔΣ modulator that converts a digital input signal into an analog output signal and a digital that performs digital-analog conversion after performing ΔΣ modulation. The present invention relates to an analog converter, and more particularly to a switched capacitor type ΔΣ modulator and its digital-analog converter.

  Conventionally, a ΔΣ (delta-sigma) type D / A converter has been proposed as a high-resolution D / A (digital-analog) converter that can reduce aliasing noise and quantization noise by oversampling and noise shaping. This ΔΣ-type D / A converter generally has a ΔΣ modulator that converts a multi-bit digital input signal into a 1-bit digital signal, and removes a high-frequency component of the output signal of the ΔΣ modulator, thereby providing an analog signal. It has an analog filter (LPF) that outputs an output signal, and high linearity can be realized at a clock frequency lower than that of the PWM modulator by oversampling or noise shaping. In other words, this type of ΔΣ D / A converter has the advantages of reducing power consumption and improving accuracy compared to a PWM D / A converter.

  The delta-sigma type D / A converter complements the digital input in the time direction to increase the sampling frequency by several tens of times (oversampling). By passing this output through a ΔΣ modulator, low-bit oversampling data is obtained. The purpose of the ΔΣ modulator is to turn a high bit digital input into a low bit “dithered” digital output by digital processing. If the output is 1 bit, the output is similar to the pulse width modulation, but a better pulse waveform is obtained by the ΔΣ modulator. This low-bit output is D / A converted and passed through a low-pass filter in the same manner as in the pulse width modulation type, thereby removing aliasing noise components and quantization error components to obtain an analog output.

Incidentally, an audio ΔΣ D / A converter (DAC) for high-end applications requires a high S / N ratio. As a method for increasing the SN ratio of the digital part of the ΔΣ DAC, it is conceivable to increase the number of output bits of the ΔΣ modulator. Each time the output bit is increased by one bit, the SN ratio can be improved by 6 dB.
However, in a switched capacitor filter (SCF) type ΔΣ DAC, increasing the number of output bits of the ΔΣ modulator increases the number of analog segments in the subsequent SCF section.

  FIG. 1 is a circuit configuration diagram of a conventional switched capacitor filter. The switched capacitor filter (SCF) includes an analog segment unit including sampling switch groups SW1 and SW4 and a sampling cap group Cs, an integration cap Ci, an operational amplifier, and the like. In the DAC, the capacitive element is charged according to the signal level of the digital input signal, and the operational amplifier outputs an analog output signal according to the charging voltage of the capacitive element. When the number of output bits of the ΔΣ modulator is N, the analog area increases because the number of analog segments is proportional to 2 to the Nth power.

On the other hand, according to Patent Document 1, for example, by forming a ΔΣ modulator in a cascade configuration, the number of analog segments can be reduced because only a small number of output bits are required to achieve the same precision SN ratio. It is said that.
FIG. 2 is a circuit configuration diagram for explaining a conventional digital-analog converter. In the figure, reference numeral 1 is a digital-analog (D / A) converter, 10 is a cascade ΔΣ modulator, 11 is a first modulator MOD1 at the first stage, 12 is a first multiplier, and 13 is a second multiplier. 2 modulators MOD2 and 20 are switched capacitor circuits, 21 is a second multiplier, and 22 is an adder.

  The D / A converter 1 shown in FIG. 2 includes a cascade ΔΣ modulator 10 and a switched capacitor circuit 20. The cascade ΔΣ modulator 10 is connected to the first-stage modulator (MOD 1) 11, a first multiplier 12 connected to the modulator 11 for multiplying the gain by K, and the first multiplier 12. And a second-stage modulator (MOD2) 13. The switched capacitor circuit 20 includes a second multiplier 21 connected to the modulator 13 for multiplying the gain by 1 / K, and an adder 22 connected to the second multiplier 21. Has been.

  That is, the switched capacitor circuit 20 is provided at the subsequent stage of the cascade ΔΣ modulator 10. As described above, the switched capacitor circuit 20 includes an analog segment unit including a sampling switch group and a sampling cap group, an integration cap Ci, an operational amplifier, and the like. In FIG. This is expressed by a second multiplier 21 for multiplying by K and an adder 22 for analog addition.

A signal obtained by multiplying-(1-z ^-1 ) Q1 obtained by shaping the quantization noise Q1 of the modulator 11 by K by the multiplier 12 is output to the modulator 13 at the next stage. The difference between the input and the output of the modulator 11 becomes − (1-z ⁻¹ ) Q1 as it is. The output of the modulator 11 and the output of the modulator 13 are analog-added by the sampling cap of the switched capacitor circuit 20. Although the output of the modulator 13 needs to be multiplied by 1 / K with respect to the output of the modulator 11, it can be multiplied by 1 / K by setting the sampling cap ratio of the switched capacitor circuit 20 to K: 1. .

  As shown in FIG. 2, when the output of the modulator (MOD1) 11 is P1, and the output of the modulator (MOD2) 13 is 1 / K times P2, the respective signals are expressed by the following equations (1) and (2). expressed.

   Since the final signal Y is the sum of P1 and P2, the transfer function of the cascade ΔΣ modulator described in Patent Document 1 is expressed by the following equation (3).

   From Expressions (1) and (2), the quantization noise Q1 of MOD1 is canceled in the upper path P1 and the lower path P2. Therefore, the quantization noise Q1 of MOD1 does not appear in the output in the transfer function of Equation (3). The quantization noise characteristic of the cascade ΔΣ modulator is 1 / K times the Lth-order noise-shaped quantization noise Q2.

  From the transfer function equation (3) described above, increasing the input gain K reduces the coefficient of Q2, so a high S / N ratio can be realized. Further, increasing K = 2 times is equivalent to increasing the number of output bits of MOD2 by 1 and both can improve the SN ratio by about 6 dB. In other words, when it is desired to obtain an equivalent S / N ratio, by increasing K, the number of output bits of MOD2 can be reduced correspondingly, so that the number of analog segments of MOD2 can be reduced.

Further, as shown in FIG. 2, when the final addition of the output of MOD1 and the output of MOD2 is performed, it is necessary to add at a ratio of K: 1. Considering digital addition, the number of analog segments cannot be reduced because the number of bits needs to be expanded to increase the output of MOD2 by 1 / K times and the number of bits increases.
Therefore, the number of analog segments of the final output can be suppressed by multiplying the sampling cap ratio by 1: K and adding the MOD1 output and the MOD2 output path in an analog manner. When the number of output bits of MOD1 is B1 and the number of output bits of MOD2 is B2, the number of bits of the final output Y is √ (B1 ² + B2 ² ).

FIG. 3 is a circuit configuration diagram of optimization of a digital-analog converter for realizing a secondary 8-bit precision S / N ratio using a conventional cascade ΔΣ modulator, which is disclosed in Patent Document 1 described above. It is a cascade configuration.
In order to realize an S / N ratio with a secondary 8-bit accuracy, a primary 5-bit MOD1, a secondary 5-bit MOD2, and a multiplier 12 with a gain of 8 are provided. At this time, consider increasing the input gain to K = 8. From equation (3) of the transfer function, doubling K is equivalent to increasing the output bit by 1 and both can improve the SN ratio by 6 dB. That is, K = 8 has the effect of increasing the output bit of MOD2 by 3 bits. Therefore, the SN ratio of the secondary 8-bit accuracy can be obtained from the secondary 5 bits of MOD2 from the transfer function equation (3). If K is increased by 8 or more, the ΔΣ system may not be stable. The stability of ΔΣ does not become stable when the input gain is increased too much, but can be quantitatively confirmed using a system simulation or the like.

Since the number of analog segments at this time is 5 bits for MOD1 and 5 bits for MOD2, the total number of analog segments may be √ (5 ² +5 ² ) = 6 bits. Therefore, it can be reduced by 2 bits as compared with the case where the secondary 8-bit ΔΣ modulator is configured as a single unit.
For example, Patent Document 2 discloses a cascaded ΔΣ modulator. Patent Document 3 discloses a ΔΣ modulator provided with a switched capacitor circuit. Patent Document 4 discloses a ΔΣ D / A converter including a ΔΣ modulator.

US Pat. No. 7,903,015 (B1) JP 2002-135120 A JP 2006-2111045 A JP 2008-35038 A

  However, taking the form of the cascade configuration described above requires two ΔΣ modulators, and there is a problem that an increase in digital area is inevitable. In order to solve such a problem, the present invention provides a first modulator constituting a cascade ΔΣ modulator and a plurality of differentiators connected in cascade after the second modulator, By making the order of the modulator and the orders of the differentiators different from each other, the order of the second modulator and the number of output bits can be lowered, so that the digital area can be reduced compared to the conventional one. It is. However, Patent Documents 1 and 2 described above do not disclose any configuration for solving such a problem. Patent Documents 3 and 4 described above only disclose a ΔΣ modulator having a switched capacitor circuit and a ΔΣ type D / A converter having a ΔΣ modulator, as in the present invention. There is no disclosure about the configuration of such a cascade ΔΣ modulator and its digital-analog converter.

  The present invention has been made in view of such a problem, and an object of the present invention is to provide a cascaded ΔΣ modulator and a digital circuit thereof capable of making the digital area smaller than that of a conventional ΔΣ modulator. It is to provide an analog converter.

  The present invention has been made to achieve such an object, and the invention according to claim 1 has a cascade configuration and a cascade ΔΣ modulator (30) configured to reduce the number of output bits. ), The first modulator (31) to which the input signal (X) is supplied, and the quantization noise of the first modulator (31) connected to the first modulator (31) by K times (K Is a first multiplier (32) that is an integer greater than or equal to 2; a second modulator (33) connected to the first multiplier (32); and a second modulator (33). A plurality of differentiators (34) cascade-connected according to the order, and the order of the first modulator (31) and the order of the plurality of differentiators (34) are the same value. Features. (Fig. 4)

  According to a second aspect of the present invention, in the first aspect of the present invention, the first modulator (31) includes a first arithmetic unit (311) that adds the input signals, and the first modulator (311). A comparator (312) connected to the computing unit (311); a second computing unit (313) connected to the comparator (312) for subtracting an output signal of the comparator (312); And a delay circuit (314) connected to the second computing unit (313), and extracting quantization noise (-Q1) from the second computing unit (313). (Fig. 5)

  According to a third aspect of the present invention, there is provided the cascade ΔΣ modulator (30) according to the first or second aspect and a switched capacitor circuit (40) connected to the cascade ΔΣ modulator (30). It is a digital-analog converter characterized by having. (Fig. 4)

  According to a fourth aspect of the present invention, in the invention of the third aspect, the switched capacitor circuit (40) is connected to the differentiator (34), and the output of the differentiator (34) is 1 / A second multiplier (41) for multiplying by K; and an adder (42) connected to the first modulator (31) and the second multiplier (41) and adding their outputs. It is characterized by being. (Fig. 4)

  According to the present invention, a first modulator constituting a cascaded ΔΣ modulator and a plurality of cascaded differentiators are provided after the second modulator, and the order of the first modulator and the plurality of differentiators are provided. Since the order of the second modulator and the number of output bits can be reduced by setting the same value to the order of the digital signal, the digital area can be reduced as compared with the conventional one.

It is a circuit block diagram of the conventional switched capacitor filter. It is a circuit block diagram for demonstrating the conventional digital-analog converter. It is a circuit block diagram of the optimization of the digital-analog converter for implement | achieving the S / N ratio of the secondary 8 bit precision using the conventional cascade delta-sigma modulator. It is a circuit block diagram for demonstrating the digital-analog converter provided with the cascade delta-sigma modulator by this invention. FIG. 5 is a circuit configuration diagram of a first modulator shown in FIG. 4. It is a circuit block diagram of the optimization of the digital-analog converter for implement | achieving the SN ratio of the secondary 8 bit precision using the cascade delta-sigma modulator by this invention.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 4 is a circuit configuration diagram for explaining a digital-analog converter including a cascade ΔΣ modulator according to the present invention. In the figure, reference numeral 2 is a digital-analog (D / A) converter, 30 is a cascade ΔΣ modulator, 31 is a first modulator MOD1, 32 is a first multiplier, and 33 is a second stage. 2 MODs 2 and 34 are differentiators, 40 is a switched capacitor circuit, 41 is a second multiplier, and 42 is an adder.

The digital-analog converter 2 of the present invention includes a cascade ΔΣ modulator 30 and a switched capacitor circuit 40 connected to the cascade ΔΣ modulator 30.
The cascade ΔΣ modulator 30 of the present invention is a cascade ΔΣ modulator having a cascade configuration and configured to reduce the number of output bits. A first modulator 31 to which an input signal X is supplied, and a first multiplier connected to the first modulator 31 and multiplying the quantization noise of the first modulator 31 by K times (K is an integer of 2 or more) And a second modulator 33 connected to the first multiplier 32, and a plurality of differentiators 34 connected to the second modulator 33 and connected in cascade according to the order. . The order of the first modulator 31 and the order of the plurality of differentiators 34 are configured to be the same value.

The switched capacitor circuit 40 is connected to a differentiator 34, and is connected to a second multiplier 41 that multiplies the output of the differentiator 34 by 1 / K, a first modulator 31, and a second multiplier 41. And an adder 42 for adding these outputs.
That is, the cascade ΔΣ modulator 30 shown in FIG. 4 has a first-stage modulator (MOD1) 31, a second-stage modulator (MOD2) 33, and N differentiators (1-z ⁻¹ ) connected in cascade. N-order differentiator ((1-z ⁻¹ ) ^N ) 34 and a multiplier 41 for multiplying the gain by K ′. Here, N is also the order of MOD1.

MOD1 quantization noise -Q1 multiplied by K 'by the multiplier 32 is input to the next-stage modulator MOD2. -K'Q1 input to MOD2 becomes ^{-K'Q1 + (1-z -1)} L Q2 by passing through MOD2. Here, L is the order of MOD2. Further, by passing through a differentiator (1-z ⁻¹ ) ^N in the subsequent stage and a multiplier 41 for multiplying the gain by 1 / K ′, − (1-z ⁻¹ ) ^N Q1 + 1 / K ′ (1− z ⁻¹ ) is converted to ^{L + N} Q2.
When the output of MOD1 shown in FIG. 4 is P3 and the output of the differentiator is 1 / K times P4, the respective signals are expressed by the following equations (4) and (5).

  Since the final signal Y is the sum of P3 and P4, the transfer function of the cascade ΔΣ modulator according to the present invention is expressed by the following equation (6).

From Expressions (4) and (5), the quantization noise Q1 is canceled in the upper path P3 and the lower path P4. By providing an Nth-order differentiator (1-z ⁻¹ ) ^N having the same order as the order N of MOD1 in the subsequent stage of MOD2, the quantization noise Q1 can be canceled by adding the paths of P3 and P4. Therefore, the transfer function of Equation (6) does not appear at the output of the quantization noise Q1 of MOD1.

FIG. 5 is a circuit configuration diagram of the first modulator shown in FIG. In the figure, reference numeral 311 denotes a first arithmetic unit, 312 denotes a comparator (quantizer), 313 denotes a second arithmetic unit, and 314 denotes a delay circuit.
The first modulator (MOD1) 31 illustrated in FIG. 5 includes a first arithmetic unit 311 that adds the input signal X, a comparator 312 connected to the first arithmetic unit 311, and a comparator 312. A second arithmetic unit 313 that is connected and subtracts the output signal of the comparator 312; and a delay circuit 314 connected to the second arithmetic unit 313. Q1 is taken out.

That is, the comparator 312, the delay circuit H (z) 314, the first calculator 311, and the second calculator 313 are provided. By subtracting the signals before and after the comparator 312, the quantization noise -Q1 can be extracted.
MOD1 has a noise feedback type configuration in which the extracted -Q1 is fed back to the input signal after passing through H (z). The transfer function when the input of MOD1 is X and the output is Y is shown in the following equation (7).

-Q1 obtained by subtracting the signals before and after the comparator 312 shown in FIG. 5 is extracted and input to the MOD2 of the next stage.
The cascade ΔΣ modulator of Patent Document 1 described above inputs − (1-z ⁻¹ ) Q1 obtained by shaping the quantization noise Q1 to the next-stage MOD2, whereas the cascade ΔΣ modulator according to the present invention is The difference is that the quantization noise -Q1 is input to the next-stage MOD2.

From the equation (6) of the transfer function of the cascade ΔΣ modulator according to the present invention, the noise shaping order of the equation (6) is (L + N) compared to the equation (3) of the transfer function of Patent Document 1 described above. ) And higher by the Nth order than the Lth order of the formula (3). Therefore, when it is desired to obtain an equivalent S / N ratio, the order L of MOD2 can be reduced by -N orders, and the area of MOD2 can be reduced, that is, the digital area can be reduced.
From the above-described transfer function of Equation (6), the coefficient of Q2 is reduced by increasing the input gain K ′ as much as possible in the new cascade configuration, so that a high SN ratio can be realized.

In order to make the input gain K ′ as large as possible, it is preferable that the power of the signal input from MOD1 to MOD2 is small. Alternatively, the input gain can be increased by lowering the order of MOD2 and increasing the stability of the system.
In Patent Document 1 described above, the quantization noise shaped is input to the next-stage modulator, whereas in the cascade configuration according to the present invention, only the quantization noise is input to the next-stage. Therefore, the total signal power is small. Therefore, the input gain K ′ can be increased as compared with the conventional one.
In the cascade ΔΣ modulator according to the present invention, since a differentiator is connected to the subsequent stage of MOD2, when it is desired to realize an equivalent S / N ratio, the order of MOD2 can be lowered accordingly. Therefore, the input gain K ′ can be increased as compared with the conventional one.

Since the differentiator is connected to the subsequent stage of MOD2, the number of bits after the output of the differentiator is larger than the number of bits of MOD2. However, since K ′ can be made larger than the conventional one, when trying to obtain an equivalent S / N ratio, the output bit of MOD2 can be lowered by that amount, and the number of analog segments should be made equivalent to the conventional one. Can do. If the number of output bits of MOD1 is B1, and the number of output bits of the differentiator immediately after MOD2 is B2, the number of bits of the final output Y is √ (B1 ² + B2 ² ).

As described above, the cascade ΔΣ modulator according to the present invention can reduce the digital area with the same S / N ratio and the number of analog segments as the conventional one.
Next, the number of analog segments (analog area) and the digital area when a single secondary 8-bit precision ΔΣ modulator is configured by the conventional technique shown in FIG. 3 and the cascade technique according to the present invention will be compared.

FIG. 6 is a circuit configuration diagram of optimization of a digital-analog converter for realizing a secondary 8-bit precision S / N ratio using the cascade ΔΣ modulator according to the present invention. In order to realize an S / N ratio with a secondary 8-bit accuracy, a primary 5-bit MOD1, a primary 4-bit MOD2, a primary differentiator, and a multiplier with a gain of 16 are provided.
That is, the first modulator 31 has a primary 5 bits, the first multiplier 32 has a gain of 16 times, the second modulator 33 has a primary 4 bits, the differentiator 34 has a primary, and the second multiplication. The device (41) has a gain of 1/16.

At this time, it was found from the system simulation that the input gain can be increased up to K ′ = 16. From equation (6) of the transfer function, doubling K ′ is equivalent to increasing the output bit by one, and both can improve the SN ratio by 6 dB. That is, K ′ = 16 has the effect of raising the output bit of MOD2 by 4 bits.
Further, since MOD2 is first-order, quantization noise Q2 only requires first-order shaping. However, by passing the first-order differentiator in the subsequent stage, a combined second-order shaping effect is obtained. Therefore, the SN ratio of the secondary 8-bit accuracy can be obtained from the primary 4 bits of MOD2 from Expression (6) of the transfer function.

The number of analog segments at this time is 5 bits for MOD1, 4 bits for MOD2, and 5 bits for the first-order differentiator immediately after MOD2, so the total number of analog segments is √ (5 ² +5 ² ) = 6 Just a bit. Therefore, the number of analog segments is the same as the conventional one.
Comparing the digital areas, the MOD2 of the cascade delta-sigma modulator according to the present invention is the primary 4 bits while the conventional MOD2 is the secondary 5 bits, so that both the order and the output bit can be reduced. Therefore, the digital area can be reduced. That is, the cascade ΔΣ modulator of the present invention has an effect that the digital area can be made smaller than that of the conventional one with the same precision SN ratio and the number of analog segments.

Since the quantization noise Q1 of MOD1 is ideally canceled, it does not appear in the output. Therefore, the order of MOD1 should be as small as possible because the area of MOD1 can be reduced.
When the output bit of MOD1 is small, the number of analog segments of MOD1 may be reduced. However, by increasing the power, the power of −Q1 input to MOD2 can be reduced, so that the input gain K ′ can be increased.

1, 2 Digital-analog (D / A) converters 10 and 30 Cascade ΔΣ modulators 11 and 31 First modulator (MOD1) at the first stage
12, 32 1st multiplier 13, 33 2nd second modulator (MOD2)
20, 40 Switched capacitor circuit 21, 41 Second multiplier 22, 42 Adder 34 Differentiator 311 First operator 312 Comparator (quantizer)
313 Second arithmetic unit 314 Delay circuit

Claims (4)

In a cascaded ΔΣ modulator having a cascade configuration and configured to reduce the number of output bits,
A first modulator to which an input signal is supplied;
A first multiplier connected to the first modulator and multiplying the quantization noise of the first modulator by K (K is an integer of 2 or more);
A second modulator connected to the first multiplier;
A plurality of differentiators connected to the second modulator and connected in cascade according to the order;
The cascade ΔΣ modulator, wherein the order of the first modulator and the order of the plurality of differentiators are the same value. The first modulator comprises:
A first computing unit for adding the input signals; a comparator connected to the first computing unit; a second computing unit connected to the comparator for subtracting an output signal of the comparator; 2. The cascade ΔΣ modulator according to claim 1, further comprising: a delay circuit connected to the second arithmetic unit, wherein quantization noise is extracted from the second arithmetic unit.   3. A digital-analog converter comprising the cascade ΔΣ modulator according to claim 1 and a switched capacitor circuit connected to the cascade ΔΣ modulator. The switched capacitor circuit is
A second multiplier connected to the differentiator and multiplying the output of the differentiator by 1 / K; an adder connected to the first modulator and the second multiplier and adding their outputs; The digital-analog converter according to claim 3, comprising:

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