EP2329356A1

EP2329356A1 - Apparatus and method for generating a random bit sequence

Info

Publication number: EP2329356A1
Application number: EP09781262A
Authority: EP
Inventors: Markus Dichtl; Bernd Meyer
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 2008-09-22
Filing date: 2009-07-30
Publication date: 2011-06-08
Also published as: US8410857B2; DE102008048292A1; WO2010031630A1; DE102008048292B4; US20110163818A1

Abstract

An apparatus (1) for generating a random bit sequence (ZZ) comprises a ring oscillator which includes a plurality of inverting digital devices (2-11) and on which an oscillator signal (OS) can be tapped. An intermediate storage element (14) monitors and stores fluctuating levels of the oscillator signal (OS). Furthermore, at least two controllable switch devices (12, 13) for simultaneously exciting at least two harmonic wave edges (OW1, OW2) of the ring oscillator are provided in a signal path of the ring oscillator. The phasing of the two harmonic wave edges (OW1, OW2) and a potential convergence thereof are subject to statistical fluctuations, which are used as a basis for the random bit generation. An apparatus and a method for generating random bit sequences are claimed. A corresponding random number generator can be used in particular as a FPGA for security applications, such as cryptographic methods. The apparatus (1) comprises substantially digital components, which are easy to produce in a standardized manner. A dedicated regulating circuit is not necessary. The apparatus is also robust toward exterior influences. The figures illustrate circuit diagrams of possible implementations and signal curves of the occurring signals.

Description

description

Apparatus and method for generating a random bit string

The present invention relates to apparatus and methods for generating random bits and random bit strings. This is for example used to implement a random number generator.

Random numbers, which occur in digital form as random bit sequences, are often required in security-relevant applications. For asymmetric authentication methods, for example, it is necessary to generate and use random numbers. Particularly in the case of RFID tags with security functionality, corresponding random numbers with particularly low hardware expenditure must be generated. It is desirable to use only digital logic circuits, which can be implemented with low cost.

In the past, random number generators have been used e.g. using analog noise sources whose signals are digitized. However, hybrid analog / digital circuits are expensive to implement.

Generating true random bit sequences usually requires a physical source of randomness, which is typically difficult to use in computer systems. Hardware random number generators use a physical process as a random source. Then, however, the physical system must be detected and measured by sensors, and then the random data can be extracted from the measured data. Examples of random physical processes include radioactive decay, semiconductor noise, free-running oscillators, or quantum states of photons. Although a good randomization of random data is achieved with it, the necessary measuring devices are extremely expensive, so that an application in mass-produced items, for example for a Simple encryption of data on RFID tags is not economical. In addition, in the case of purely electrical random number generators, the problem frequently arises that the correct mode of operation depends on the fact that analog electronic circuits must be set exactly to predefined operating points. Therefore, there are problems with manufacturing variations and changes in operating conditions such as temperature or other external influences. It is therefore disadvantageous since purely analog circuits are sensitive to disturbances and manipulations.

So-called pseudo-Zufauszahlen can be generated algorithmically. In this case, the algorithmically generated random bits or random numbers, although not actually random, should as far as possible not be distinguished from true random bits. In the case of pseudo-random bits, a microprocessor device CPU (= Central Processing Unit) is operated with a corresponding program which requires a so-called seed value (= seed) from a memory. From the seed's current value, the CPU calculates random bits and new seed values, which in turn are stored and override the old value. In order not to receive the same random bit or number sequences on different devices, the various devices are set to an individual start value in a personalization step.

Although pseudo-in-numbers provide enough random data for some applications, they can not completely replace physical random numbers. Because at least for the determination of an initial seed value real coincidence is needed. However, starting from the initial seed value, the pseudo-in-feed numbers are deterministic. The statistical quality of generated pseudo-random data depends strongly on the algorithm used and the length of the seed value. For example, standard C libraries use methods that use Fibonacci generators. Also feedback shift registers are partially used for the generation of pseudo-in-feed numbers. The abovementioned measures These are not suitable for cryptographic applications. An attacker could easily predict the random number sequence.

More sophisticated methods use cryptographically strong hash functions or encryption techniques to calculate random data and new seed values from a current seed value. In order to achieve sufficient quality in the generation of random numbers, therefore, particularly high-performance resources requiring CPUs are necessary.

It has also been proposed in the past to provide purely digital random number generators having digital electrical components in integrated circuits. For example, it has been proposed to use the use of jitter in ring oscillators for random number generation. Digital ring oscillators are usually formed from an odd number of inverters that are cyclically arranged or fed back together. The fluctuations of the period lengths are referred to as jitter. However, the jitter is usually small compared to the period length, so that the randomness of it accumulates only slowly over time. To generate random numbers faster, Fibonacci or Gallois ring oscillator variants have been proposed, by means of which faster random number sequences can be generated.

Although the digitally implemented random number generators can be manufactured cheaply, for example as FPGAs or in ASICs (Application Specific Integrated Circuits), manufacturing variations of the corresponding components disturb the process of random number generation. In order to compensate statistical defects in the random data, which are generated for example by physical noise sources, also algorithmic post-processing is performed. The measured data are compressed in order to increase the entropy. To avoid fluctuations in the frequency distribution Cryptographically strong hash functions can also be used.

Overall, the known methods and generators for random bit generation or the corresponding hardware-moderate implementations result in a number of disadvantages which generally preclude their use in mass products.

It is therefore an object of the present invention to provide an improved apparatus and method for generating random bits.

This object is achieved by a device having the features of patent claim 1 and by a method according to patent claim 14.

Accordingly, an apparatus for generating a random bit sequence comprises a ring oscillator comprising a plurality of inverting digital devices, at which an oscillator signal can be tapped off. A buffer element is provided for storing levels of the oscillator signal, and at least two controllable switching devices are provided in a signal path of the ring oscillator, preferably to simultaneously excite at least two harmonics or edges of a harmonic of the ring oscillator.

The latch element monitors and stores the fluctuating levels of the oscillator signal. Since the simultaneously generated harmonic edges are out of phase with each other, they potentially converge in statistical variations. The resulting waveforms are unpredictable and serve as the basis of random bit generation.

In a method for generating a random bit sequence, the steps are provided:

Providing a ring oscillator comprising digital switching elements; Exciting at least two edges of one or more harmonics of the ring oscillator as an oscillator signal which fluctuates between two predetermined logic levels;

Picking up the oscillator signal; and

Determining a random bit in response to a number of level crossings of the oscillator signal in a predetermined period.

For example, starting from a static state with suitably selected initial conditions, which can be determined by the controllable switching devices, a metastable vibration state of the ring oscillator in the form of a harmonic wave can be set. The phase position of the two edges of the harmonic is subject to statistical fluctuations. As a rule, the two edges of the harmonic coincide after a certain period of time. If the ring oscillator has an even number of inverters, it will stop. If an odd number of inverters is provided, the ring oscillator drops to its fundamental frequency and continues to oscillate stable.

As a random bit, for example, a number of rising or falling oscillator signal edges can be used within the predetermined time period. In particular, the buffer element, which may be configured for example as a flip-flop, is suitable for counting signal edges. Further, if this determined or stored number undergoes a modulo operation, a random bit results.

For example, a control device can determine several random bits one after the other at the buffer element, which then delivers a random bit sequence or a binary random number. In the apparatus, the controllable switching devices may be implemented as AND gates, for example. AND gates are easily implemented in a standardized manner and, depending on the logic level of an input signal, serve as a closed switch or block the signal path within the ring oscillator.

In an analogous manner, the controllable switching device can be embodied as an OR gate, in which case a logic L level leads to the oscillation of the circuit.

As an embodiment, a control device is furthermore provided which generates such a start signal for the controllable switching devices and the buffer element, that each controllable switching device generates a harmonic edge of the oscillator signal and the buffer element is reset. This allows a metastable state of vibration to be achieved from a static state.

Furthermore, the control device can pick up a logic level of a random bit at an output of the buffer element, the start signal for generating a plurality of random bits being generated, and the plurality of random bits being output as a random bit sequence from the control device. The approach has, for example, the advantage that no further control circuit is required to find or maintain a metastable state of the ring oscillator. Rather, the generation of super waves results in this metastable state, which serves as the basis for the generation of random bitumen.

In one embodiment, an equal number of inverting digital devices are provided between the controllable switching devices. This symmetrical arrangement has the advantage that interferences are symmetrized and the statistical randomness is improved. In yet further embodiments of the apparatus for generating a random bit sequence, a further buffer element is coupled to the ring oscillator such that parasitic electrical influences of the buffer elements are present symmetrically with respect to the inverting digital devices. The capacitive load of the inverting devices or switching devices embodied, for example, as logic gates, is thus largely symmetrical, so that the respective harmonic wave is maintained for a particularly long time and the statistically random phase relationship between the two harmonics is more favorable. The second buffer element, for example designed as a flip-flop, serves, for example, only for the symmetrization of the oscillator part of the circuit, the output of which is not used.

The inverting digital devices and the controllable switching devices may be implemented as two logic gates, e.g. NAND gates are integrated. A NAND gate combines on the one hand an inverting function of the continuous signal and on the other hand a switching function, depending on the combination of the logical input signals. The device for generating random bits can therefore be made particularly compact.

Instead of the NAND gates, NOR gates can also be used, in which case the transition to the logical value H starts the oscillation of the circuit.

It is also conceivable that a delay device is connected between an input of a logic gate, in particular a NAND gate (or the NOR gate) and an output of the respective other NAND gate (or NOR gate). The delay time through the delay device, for example a chain of driver circuits, should be longer than the switching time of the NAND gate (or NOR gate). Otherwise, the two harmonics would fall practically directly on each other. In a development, the device is embodied as FPGA (= field programmable gate array or field programmable gate arrangement). The completely digitally implemented device makes corresponding programming particularly easy. Furthermore, the apparatus and method are suitable for implementation in an ASIC.

The proposed device and the method have the advantage that they are particularly easy to implement circuitry. Only a small number of electronic digital components are required. This makes it particularly suitable to use corresponding random number generators in mass business.

Further advantageous embodiments of the invention are the subject of the dependent claims and the embodiments of the invention described below. In the following, the invention will be explained in more detail by means of exemplary embodiments with reference to the following figures. It shows:

FIG. 1 shows a circuit diagram of a first embodiment of a device for generating random bit sequences;

Figures 2-5 possible waveforms of oscillator signals and random bit signals;

FIG. 6 shows an equivalent circuit diagram for a ring oscillator which can be used in embodiments of devices for generating random bits;

FIG. 7 shows a circuit diagram of a second embodiment of a device for generating random bit sequences; FIGS. 8, 9: possible signal forms of oscillator signals; and

FIG. 10 shows a circuit diagram of a third embodiment of a device for generating random bit sequences.

In the figures, identical or functionally identical elements have been given the same reference numerals, unless stated otherwise.

FIG. 1 shows a random bit generator as a device for generating random bit sequences. The random bit generator 1 comprises a ring oscillator, which is constructed from serially interconnected inverters 2-11. In this case, an upper branch of five inverters 2-6 and a lower branch of five inverters 7-11 is shown. The two branches are connected to each other cyclically, with an AND gate 12, 13 being used as the controllable switching devices. The AND gates each have two inputs 18, 19, 21, 22 and an output 20, 23rd

In each case an input 21, 19 of the AND gates 12, 13 is coupled via a suitable line to a control device 50, which generates a control signal ST. The signal path of the ring oscillator thus comprises the inverters 2-11 and the two AND gates 12, 13. At the signal path, a corresponding oscillator signal OS can be tapped off.

For detecting and storing the oscillator signal OS, a buffer element 14, which is designed as a flip-flop coupled. The flip-flop 14 has a clock input 15, a reset input 16 and a data output 17. The reset input 16 is coupled to the control output 51 of the control device 50 and, like the inputs 21 and 19 of the AND gates 12, 13, receives the start signal ST , The oscillator signal OS is fed to the clock input 15 of the flip-flop 14. At the data output 17 of the flip-flop 14, a random bit can be For example, tap, which is guided to an input 52 of the control device 50.

The control device 50 generates the start signal ST in such a way that, starting from the AND gates 12, 13, in each case one edge of a harmonic arises in the signal path. At this time, a first harmonic edge passes from the output 23 of the AND gate 12 through the inverters 2-6, and a second harmonic wave passes from the output 20 of the second AND gate 13 through the inverters 7-11. For example, the start signal ST may be set at logical L level or 0 level, for example. Then, at the output 23, 20 of the AND gate 12, 13 is always a logical L level or 0. A vibration of the ring oscillator does not result. If the start signal ST is set to logic H level or 1, the AND gates 12, 13 operate as closed switches. That is, input 22 is logically connected to the output 23 of the AND gate 12 and the input 18 is logically connected to the output 20 of the AND gate 13. At the same time resetting of the flip-flop 14th

There are now two harmonics edges in the signal path of the ring oscillator. At the start, a logical 1 is present at the input of the first inverter 2. At the same time, a harmonic edge, starting from a logic 1, at the output 20 of the AND gate 13 or input of the inverter 7 through the. In the inverters of the follower inverter 3-6 results then at the input 18 of the AND gate driven lower inverter chain. This leads to a logic 0 at the output of the inverter 11. Thus, the two harmonic flanks are out of phase. The oscillator signal therefore comprises superposed edges of a harmonic signal.

Due to the superposition of the two edges of the harmonic no stable logic signal is given by the oscillator signal OS. At the clock input 15 of the flip-flop 14 therefore oscillates an irregular oscillating logic signal. The oscillator signal can be in this metastable vibrational state be understood as an analog signal with random properties.

A topologically and functionally equivalent arrangement can also be achieved by replacing two inverters with NAND gates in a ring oscillator constructed from inverters. These should preferably be provided at opposite positions of the ring in order to achieve symmetrical signal properties against interference. It is also conceivable, in order to generate more than two harmonics, to provide a plurality of controllable switches, which generate harmonic edges by suitable supply of a start signal.

For a more detailed explanation of the mode of operation of the embodiment of a random number generator in FIG. 1, waveforms of the oscillator signal OS and the random bit signal ZB are plotted over time t in FIGS. In the figure 2, for example, the oscillator signal is applied to the clock input 15 of the flip-flop 14 over time. Logical L level corresponds to a level of 0 V and an H level, that is a logic 1, about 3.3 V in the following representations of signal curves.

It can be seen that as soon as the start signal ST is set to logic 1, the oscillator signal begins to oscillate irregularly at the output of the inverter 6. It can be seen that two harmonic edges OW1 and OW2 are shifted from one another and present with different amplitude over time. From about 300 ns, the two edges OWl and OW2 of the harmonic have gone together and swing stable. The ring oscillator thus stops.

Basically, a ring oscillator with an even number of inverters, as shown in FIG. 1, has a fixed point and stops after a certain period of time. The waveform up to the stalling of the ring oscillator serves as a random basis for the generation of the random bit. Because the flip-flop 14 counts as a clock divider the number of Vibrations modulo 2. That is, the present at the data output 17 level coincidentally corresponds to the number of resulting in the waveform of Figure 2 rising or falling signal edges. Another random element results from the strongly fluctuating amplitudes, so that, for example, in the range between 200 and 300 ns there is no well-defined logic level at the input 15 of the buffer or flip-flop 14.

FIG. 3 shows the oscillator signal course once more over time. The curve of FIG. 3 corresponds to a different start than that of FIG. 2. It can be seen that once again there are two harmonic edges OW1, OW2, which converge towards one another and lead the oscillator into a stable state after approximately 300 ns. However, the waveforms of Figure 2 and Figure 3 differ randomly from each other.

Figures 4 and 5 show the time course of Zufallsbitsignals ZB at the output 17 of the flip-flop 14. Due to the random oscillator waveform at the clock input 15 of the flip-flop 14, both logical H and logical L-level at the output 17 of Flip-flops 14. The waveform in the figure 4 for the random bit ZB results in random dependence on the oscillator signal OS at the clock input 15th

After a predetermined period, for example 400 ns, when the ring oscillator has reached its stable state, a random bit, which in the case of FIG. 4 has a logic H level, can be detected. This is done, for example, by the control device 15, which via its

Input 52 is coupled to the output 17 of the flip-flop 14.

FIG. 5 shows a similar signal curve. However, the logic level of the resulting random bit after 400 ns is a logical L level which is approximately 0V. It is now possible, for example, to specify a period of time in which the ring oscillator, after which two harmonic edges have been generated by the start signal, generally assumes a stable state reached. The meanwhile randomly resulting signal waveforms or signal edges are used to determine a random bit. The quality of the randomness of the generated random bit ZB essentially depends on the non-determinable, time-shifted course of the generated harmonic. The two harmonic edges pass through the ring oscillator arrangement phase-shifted. On the one hand, the switching properties, in particular switching times of the two AND gates 12, 13, play a role, as do the delay characteristics of inverters 2-11.

In the figure 6, therefore, an equivalent circuit diagram for a corresponding ring oscillator is made. In a simple embodiment of a ring oscillator 100, which is suitable for use in a random bit generator, one each

Inverter 6, 11 and a delay line 26, 27 connected in series. These two delay and inverter sections are cyclically interconnected by two switches 24, 25. The two switches can be opened or closed by a start signal ST. This is done essentially simultaneously.

If the two controllable switches 24, 25 open, there is no oscillation. Rather, stable logic levels are present at the input and output of a respective inverter 6, 11. However, if the switches are closed, for example, a signal edge, starting from the output of the inverter 6 (a well-defined H or L level, passes through the delay line 27 and is inverse-converted by the second inverter 11. The thus-inverted harmonic signal then passes through a delay line 26 again and in turn is inverted by the inverter 6. Thus, two harmonic edges in the signal path circulate as oscillator signal OS. Preferably, the switching times of the controllable switches 24, 25 are less than the signal delay through the delay lines 26, 27.

By tapping the oscillator signal OS and counting the resulting signal edges by the two superimposed Harmonic edges, then, as has been explained, for example, with reference to Figure 1, a random bit determined. By repeatedly triggering the harmonics and resetting the corresponding latch element, such as a flip-flop, a random bit sequence is then generated.

Figure 7 shows a random bit generator as a random bit generating device in which inverting elements are integrated in NAND gates. The random bit generator 101 comprises a chain of driver circuits 36-40, which in principle constitute a delay path. A second corresponding delay line is made up of five further drivers 41-45. The result is an upper branch and a lower branch, which are connected to each other via a NAND gate 28 and 29, respectively. The NAND gates 28, 29 each have two

Signal inputs 30-33 and an inverting output 34, 35 on. In comparison to FIG. 6, the NAND gates 28, 29 correspond to a combination of the controllable switches 24, 25, each having an inverter 6, 11.

At first inputs 30, 33 of the NAND gates 28, 29, a start signal ST is performed. Between the output 34 of the first NAND gate 28 and the second input 32 of the second NAND gate 29, the upper delay line of drivers 36- 40 is connected. Between the output 35 of the second NAND gate 29 and the second input 31 of the first NAND gate 28, the lower branch of the five drivers 41-45 is coupled. At the output of the driver 40, the oscillator signal OS is tapped and fed to a clock input 15 of a flip-flop 14. A reset input 16 of the flip-flop 14 is also connected to the start signal ST, and the data output 17 of the flip-flop supplies a random bit ZB. The operation is similar with respect to the circuit described in Figure 1. As soon as the start signal is set to 1, the flip-flop 14 is reset and at the output 34 or 35 of the NAND gates start phase-shifted harmonic edges of the resulting ring oscillator, which in the signal path, the NAND gates 28, 29 and the driver circuits 36- 45 Has. Even with these few digital elements, random bits of high quality can be generated.

FIG. 8 shows an exemplary waveform of the oscillator signal OS at the input of the flip-flop 14 for the random bit generator 101. It can be seen that after approximately 450 ns the ring oscillator has a stable L level at the output of the driver 40 or input 32 of the NAND gate 29. This is the stable state for the ring oscillator.

FIG. 9 shows a similar signal curve for the oscillator signal after a further start over time. In the case of the "run" shown in FIG. 9, the two harmonics generated already coincide earlier or converge, so that the stable state of the oscillator is reached after about 370 ns, by counting the resulting signal edges, for example in the given period of time between 0 and 450 ns, a random bit ZB is then derived, which can be tapped off at the output 17 of the flip-flop 14.

Furthermore, a further variant of a random bit generator is shown in FIG. The random bit generator 102 has substantially the same elements as shown in FIG. 1, but only three inverters 2-4 and 5-7 are connected in series at the top and bottom branches. Elements which have already been explained in FIG. 1 will not be discussed here. The random bit generator 102 has, in addition to a first buffer element 14 or a flip-flop, a second flip-flop 46, which preferably has an identical structure to the first flip-flop 14. The clock input 47 of the second flip-flop 46 is coupled to the output of the last inverter 7 in the lower inverter chain or to the input of the first AND gate 12. The clock input 15 of the first flip-flop 14 is to the last inverter 4 of upper inverter chain and guided to the input of the second AND gate 13. The second flip-flop 46 also has a reset input 48 to the, as also to the reset input 16 of the first flip-flop 14, the start signal ST is performed.

The second flip-flop 46 serves to symmetrize the oscillator part of the circuit. The data output 49 is not used. Due to the achieved symmetrical situation, a generated harmonic by the first or second AND gate 12, 13 is maintained for a particularly long time. This results in a larger number of signal edges, which can potentially be detected by the flip-flop 14, which lead to the random bit value ZB.

The presented random bit generators have the particular advantage that only a small number of digital electronic components is necessary, which can be easily implemented in the integrated circuits. Furthermore, the proposed approach can be easily described in a common hardware description language such as VHDL. This makes it easy to use standard logical components from cell libraries to IC applications. As a result, the corresponding components can also be synthesized and used as FPGA applications. Since the random number generators operate entirely digitally, no analog circuit components or corresponding manufacturing processes are necessary in the production of corresponding integrated circuits.

Since the harmonics pass through the same digital components of the respective ring oscillator in succession, changes due to the environmental conditions or electrical properties of the electronics affect the signal edges in the same way. The vibration processes are therefore particularly robust against external influences, with regard to manufacturing variations and aging processes. Thus, in particular a use in mass production, for example, RFIDs is suitable.

Although the present invention has been explained with reference to some embodiments, it is not limited thereto. but variously modifiable. In particular, other than imaginary numbers of inverters may be provided in the oscillators. It is also possible to generate more than two harmonic edges by means of suitable controllable switches in a signal path of a ring oscillator. This results in a further randomization of the oscillator signal in the transient process. Furthermore, it is possible to generate several harmonics of different order and flank many harmonics to be used as randomizing elements. In addition to the illustrated flip-flops as intermediate storage elements, other digital storage forms can be used.

Claims

claims

1. Device (1) for generating a random bit sequence (ZZ) comprising a plurality of inverting digital devices (2-11) comprising a ring oscillator on which an oscillator signal (OS) can be tapped, a buffer element (14) for storing levels of the oscillator signal (OS ) and with at least two controllable switching devices (12, 13) provided in a signal path of the ring oscillator for the simultaneous excitation of at least two harmonic edges (OW1, OW2) of the ring oscillator.

2. Device (1) according to claim 1, wherein the ring oscillator comprises an even number of serially connected inverters (2-11) as inverting digital devices.

3. Device (1) according to claim 1 or 2, wherein the controllable switching means (12, 13) are designed as logic gates, in particular as an AND gate or as an OR gate.

4. Device (1) according to one of claims 1-3, wherein the buffer element (14) detects and stores a number of rising and / or falling oscillator signal edges.

5. Device (1) according to any one of claims 1-3, wherein a control device (50) such a start signal (ST) for the controllable switching devices (12, 13) and the buffer element (14) generates that each controllable switching device (12, 13) in each case generates a harmonic edge of the oscillator signal (OS) and the buffer element (14) is reset.

6. Device (1) according to claim 4 and 5, wherein the control device (50) at an output of the latching element (14) a logic level of an accessory ifbits (ZB) generates the start signal (ST) to generate a plurality of random bits and outputs the plurality of random bits (ZB) as a random bit sequence (ZZ).

7. Device (1) according to any one of claims 1-6, wherein in each case an equal number of inverting digital devices (2-11) are provided between the controllable switching devices (12, 13).

8. Device (1) according to one of claims 1-7, wherein the controllable switching devices (12, 13) in a first switching state block an oscillation of the ring oscillator and in a second switching state open a signal path, the inverting digital devices (2-11 ).

9. Device (101) according to one of claims 1-8, wherein the inverting digital devices and the controllable switching devices are integrated as at least two cyclically interconnected logic gates.

10. Device (101) according to claim 9, wherein between an input (32) of a logic gate (29) and an output (34) of the respective other logic gate (28), a delay means (36-40) is connected.

11. Device (102) according to one of claims 1-10, wherein a further buffer element (46) is coupled to the ring oscillator in such a way that parasitic influences of the buffer elements (14, 46) are symmetrical with respect to the inverting digital devices (2-7 ) are present.

12. Device (1) according to any one of claims 1-11, wherein the buffer element (14) is designed as a flip-flop.

13. Device (1) according to one of claims 1 - 12, wherein the device is designed as an FPGA.

14. A method for generating a random bit sequence comprising:

- providing a ring oscillator (1) comprising digital switching elements;

- Exciting at least two harmonic edges (OWL, OW2) of the ring oscillator as an oscillator signal (OS), which varies between two predetermined logic levels;

- Picking up the oscillator signal (OS); and - determining a random bit (ZB) in response to a number of level transitions of the oscillator signal (OS) in a predetermined period of time.

15. The method of claim 14, wherein the predetermined period is selected such that the harmonic waves (OWL, OW2) converge within the predetermined period of time and cause a stable oscillation of the ring oscillator (1).

16. The method of claim 14 or 15, wherein the random bit is determined by counting the rising and / or falling oscillator signal edges within the predetermined period, in particular a number of signal edges is subjected to a modulo operation.

17. The method according to any one of claims 14-16, wherein successively a plurality of random bits (ZB) are determined which provide a random bit sequence or a binary random number (ZZ).