WO2014191201A1

WO2014191201A1 - Generation of random bits

Info

Publication number: WO2014191201A1
Application number: PCT/EP2014/059739
Authority: WO
Inventors: Markus Dichtl
Original assignee: Siemens Aktiengesellschaft
Priority date: 2013-05-31
Filing date: 2014-05-13
Publication date: 2014-12-04
Also published as: DE102013210147A1

Abstract

The invention relates to a device and to a method for generating random bits by means of an electronic oscillating circuit having a plurality of representation apparatuses. Signal changes propagating in the oscillating circuit are stopped by means of switch-off apparatuses. The waiting time until a possible restart of a random number generator is reduced.

Description

description

Generating Random Bits The present invention relates to generating random bits with an electronic oscillator circuit comprising a plurality of imaging devices. For example, a random bit sequence is generated which is used as a binary random number. The proposed devices and methods for generating random bits serve, for example, the implementation of random number generators.

In safety - relevant applications, such as asymmetric authentication methods, random bit sequences are necessary as binary random numbers. It is desired, in particular for mobile applications to operate as little hardware as possible. Known measures to generate random numbers use analogous random sources. Furthermore, ring oscillators and their modifications are used as random number generators.

As analog random sources, noise sources such as e.g. the noise of zener diodes, amplified and digitized. Digital is connected with analog circuit technology.

For ring oscillators, which are made up of an odd number of inverters connected in series, random jitter results from fluctuating throughput times of the signals through the inverters. These jitter, that is to say an irregular fluctuation in the state changes of the signals sent by the inverters, can be accumulated in the case of multiple passes through the ring oscillator circuit, so that ultimately a random analog signal is produced.

To generate true random numbers, the prior art approach known by Marco Bucci and Raimondo Luzzi is known to enter a reset mode or restart mode. to lead. By means of permanently repeated restarts of random number generators from identical starting conditions, statistical independence is ensured ("Design of

Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings).

In order to ensure identical starting conditions upon a restart, preferably all the vibration states resulting from the generation of previous random bits should be decayed. Therefore, a waiting time is necessary in which the generator does not vibrate, so that a still existing oscillation completely subsides. Against this background, it is an object of the present invention to provide an improved apparatus and method for generating random bits.

This object is achieved by an apparatus and method for generating random bits. Advantageous embodiments and further developments are specified in the subclaims.

The advantages mentioned below need not necessarily be achieved by the subject-matter of the independent patent claims. Rather, it may also be advantages, which are achieved only by individual embodiments or developments. According to the invention, an apparatus for generating random bits comprises an electronic oscillating circuit comprising a plurality of imaging devices, wherein a random signal having a random level profile can be tapped off in an oscillating mode at an output node of the oscillating circuit, wherein at least two of the plurality of imaging devices are designed as activatable shutdown devices and wherein the at least two Shutdown devices in an activated state generate a respective output signal and the output signal in the oscillating circuit propagates signal change stops.

The proposed device makes it possible to quickly stop a vibration state within an oscillating circuit and thereby reduce a waiting time within which an initial state is assumed. A switch-off signal acting on a single point of the oscillating circuit, which suppresses a signal change at this location, can not influence further imaging devices located in the oscillating circuit until the signal change has propagated once in the entire oscillating circuit and a second time to the Deployment signal giving shutdown device passes. With a length m of the oscillating circuit, ie for example m digital imaging devices, such as inverters within a ring oscillator, at least m-1 oscillation states with full amplitude between the values of logical 0 and logic 1 occur when applying a stopping signal.

The proposed device now makes it possible to stop the vibration at several points within the oscillating circuit. Thus, by halting at several points almost simultaneously, complete decay of vibrational states can advantageously be accelerated. Only when all the vibration states resulting from the generation of previous random bits have subsided do a random number generator assume identical starting conditions. Identical start conditions are required when restarting a random number generator to ensure the statistical independence of the generated random bits.

This means that the waiting time is reduced until a random number generation generator is ready to reboot. Thus, the proposed device shortens the waiting time and thus increases the data rate of random bit generation. In the present application, an activated state is understood to be a state in which a signal is present at the respective cut-off device, ie, is present, which is a specifiable mode of operation of the electronic device

Oscillating circuit triggers. Therefore, it is spoken by an activatable shutdown device. The operation causes the stopping of the electronic oscillating circuit. When activated, the electronic oscillator circuit changes from a vibrating to a non-vibrating state.

Also, the initiation of the opposite effect is possible via the turn-off device by the activated state is terminated via an application start signal and the electronic see oscillating circuit changes from a non-vibrating to a vibrating state. The respective shutdown device is then no longer activated.

According to an advantageous development, the respective switch-off device has at least one first input and one second input and one output for the respective output signal, wherein the respective second input has a switch-off functionality, so that after application of a switch-off signal at the respective second input the respective Outgoing signals of the turn-off device after a delay time are independent of respective input signals of the respective first inputs.

Thus, an existing vibration state is interrupted within the oscillating circuit by the respective output signal, that is stopped at least two locations within the oscillating circuit. It may take a short time, regardless of input signals to existing other inputs of the turn-off the respective output signal in the activated state is constant and the decay of the

Vibration causes. The delay time is predetermined by the technology in which the electronic oscillation circuit is realized. According to an advantageous embodiment, the oscillating circuit is designed digitally or analogously. As components of a circuit, analog elements such as inverting amplifiers can be installed. Furthermore, the use of completely digital components in the apparatus for generating random bits is also advantageous, since an inexpensive implementation is possible.

According to an advantageous embodiment, the respective shutdown device is designed as a logic gate or realized by lookup tables. In Ringoszillatorschaltungen, this term being the simple ring oscillators as well as Fibonacci- and

Galoisringoszillatoren, a number of logic gates is fed back. In this case, all the gates are in a feedback loop formed by the other gates, so that a signal change at the output of a gate can potentially return to an input of the gate after the path via the feedback loop formed from other gates. Logical functions performed by the mapping devices can also be realized by look-up tables or so-called lookup tables. Lookup tables are particularly applicable to field programmable gate arrays, FPGAs for short. Instead of implementing gates with a corresponding desired functionality, tables are stored which look up the outputs in their memory depending on the input bits. For example, for a number of z input bits, the LUT has 2 addresses. According to an advantageous embodiment, the oscillating circuit is designed as a ring oscillator circuit, wherein of the plurality of imaging devices a number n as Inverter is formed and disposed between the at least two defeat means.

In ring oscillator circuits, the jitter arising from randomly fluctuating throughput times of the signals by the inverters is utilized. This is true for simple ring oscillators as well as for Fibonacci and

Galoisring oscillators to. If necessary, statistical defects in the random bits are compensated by algorithmic postprocessing. Thereby a compression of the measured data takes place, so that the entropy per output bit increases. An oscillation circuit of any length can be realized, wherein a number n of inverters, which do not stop the oscillation, can be arranged between stopping elements, such as, for example, NAND gates. If an additional expenditure of hardware is necessary due to the introduction of the at least two shutdown devices, then this additional expenditure can be compensated for via the number of the at least two shutdown devices on the one hand and the distance between the at least two multiple digital imaging devices within the oscillating circuit on the other hand.

According to an advantageous embodiment, the respective shutdown device is formed as a NAND gate or as an AND gate.

If a logic 1 is present at the respective second input for the embodiment with a NAND gate, then the NAND gate acts in an inverting manner and the oscillation is not interrupted. It is then present at the respective output of the inverted value of the respective first input. If a logical 0 is present at the respective second input, the respective output signal of the NAND gate is in each case a logical 1, that is to say no signal change occurs at this NAND gate. A NAND gate thus has two functionalities, those of the inverting element within the ring and that of the stopping element, driven by an external one

Switch-off signal. If an AND gate is installed as a shutdown device, this converts the shutdown functionality. When a logical 0 is applied, the AND gate is in the activated state and stops a progressive signal change, since for each

Input signal is a 0 is output. When a logical 1 is applied, the gate acts as a non-inverting element within the ring without further functionality. According to an advantageous development, the device is part of an FPGA device or an ASIC device.

The proposed device is particularly advantageous in an implementation of the oscillating circuit on a programmable logic gate array in the application field or a so-called Field Programmable Gate Array, or FPGA for short. Despite the introduction of the at least two turn-off devices for switching the signal change propagating in the oscillating circuit on or off, there is hardly any increased expenditure of hardware resources. On FPGAs, logical functions are realized by lookup tables or lookup tables of fixed input width. Standard is an input width of 4 or 6 bits. For example, as the input width of an inverter is 1 bit, it can be extended to a two-input NAND gate without increased lookup table consumption.

For the implementation on an application-specific integrated circuit, a so-called Application Specific Integrated Circuit, ASIC, a suitable choice of the number of at least two defeat devices or a suitable choice of the number n of non-stopping logic gates between the two defeat devices is a compromise. miss between hardware overhead and increased data rate in random bit generation.

According to an advantageous development, the device further comprises an intermediate coupled to the output node. memory element which stores a logic level in response to the random signal.

It is possible, for example, to form a buffer element as a flip-flop. T-flip-flops change, for example, the internally stored logic state at each rising or falling signal edge of the coupled random signal. That is to say, if the random signal fluctuates irregularly between two logic levels, the buffer element supplies a random bit value that depends on the indeterminable number of, for example, rising or falling edges of the random signal. The final random bit is then taken at the output of the T flip-flop at any given time, for example periodically clocked.

Furthermore, it is also possible to use D-flip-flops which take over the random output signal of the oscillating circuit when a positive or a negative signal edge occurs at its clock input. This clock input can, for example, be assigned a periodic signal, so that random bits are sampled periodically.

According to an advantageous embodiment, the oscillating circuit is designed as a Galois ring oscillator or a Fibonacci ring oscillator.

Fibonacci and Gallois ring oscillators advantageously rapidly generate random waveforms.

According to an advantageous embodiment, a period of time can be predetermined, within which a signal change propagating in the electronic oscillating circuit subsides after the application of a switch-off signal.

Thus, the construction of an electronic oscillating circuit can be carried out over a predefinable period of time or a predefinable number of gate transit times to the request to the data rate of random number generation.

According to an advantageous embodiment, the switch-off signal at the respective switch-off device can be predetermined almost simultaneously for the respective switch-off devices by a control device.

The simultaneous switch-off at all available shut-off devices represents a maximum time saving.

According to an advantageous embodiment, the switch-off signal can be predetermined almost simultaneously with a scan signal. Random bits can be picked up by the sampling or sample signal and at the same time the switch-off signal is given without any further loss of time. This represents an energetically particularly favorable variant of the device. The invention furthermore comprises a method for generating random bits with an electronic oscillating circuit comprising a plurality of imaging devices, wherein in one

Vibration mode at an output node of the oscillator circuit, a random signal with a random level characteristic is tapped, wherein at least two of the plurality of imaging devices are configured as activatable shutdown devices and wherein by the at least two turn-off devices in an activated state, a respective output signal is generated and by the output signal in the oscillatory circuit propagating signal changes are stopped.

The invention will be explained in more detail below with exemplary embodiments with reference to the figures. FIG. 1 shows a schematic representation of a ring oscillator circuit according to a first exemplary embodiment of the invention; Figure 2 is a schematic representation of an output signal at an output of a shutdown device according to the prior art; Figure 3 is a schematic representation of an output signal within an electronic oscillating circuit according to the prior art;

FIG. 4 a schematic representation of an output signal within an electronic oscillating circuit according to a second exemplary embodiment of the invention;

Figure 5 is a schematic representation of a ring oscillator circuit according to a third embodiment of the invention;

Figure 6 is a schematic representation of an embodiment of the invention for use in a Mehrspurringoszillator.

The proposed device is advantageously realized on an FPGA. In particular, the electronic oscillating circuit 20 may be a Fibonacci ring oscillator which, for example, has the length 31. So there are 31 gates provided. The Fibonacci

Ring oscillator consists of several imaging devices up to 2 _m , wherein at least two of the several imaging devices are configured as a shutdown device 2, 2_, for example as a NAND gate. For example, according to FIG. 1, the first imaging device is known as NAND

Gate and thus designed as a shutdown device 2 ^.

In this case, the turn-off devices 2 ^, 2_ each have a first input El, El *, which supplies an output signal of a previous imaging device located in the ring as an input signal. In each case, a second input E2, E2 * is provided, which switches on and off Switching functionality fulfilled. For this purpose, the respective shutdown device 2 _] ^, 2_ in the activated state forms a fixed respective output signal A ^ -, A_. In the case of the NAND gate, the oscillation is maintained by an applied logic 1, if a logic 0 is applied, the oscillation on the output signal of the NAND gate is stopped. In particular, the oscillation can be restarted by applying a logical 1 after a phase in which a logic 0 was applied, so that the electronic oscillating circuit is switched on again.

Between the shutdown devices 2 ^ -, 2_ can imaging devices 3] _- 3 _n lie that have no Abschaltefunktionalität.

The output signal A 1 - of the switch-off device 2 ^ changes from a logical value 1 to a logical value 0 after a short delay time after application of the switch-off signal with logic value 0. A logical value 0 also remains as output signal A 1 - a logic value 0 ,

To illustrate the operation of a random number generator in the restart mode according to the prior art, Figure 2 shows an output signal of the first designed as a NAND gate inverter, ie according to Figure 1 of the turn-off device 2] ^, within the Fibonacci ring oscillator. The diagrams in FIGS. 2 to 4 each show a voltage signal plotted against time. In FIG. 2, the switch-off signal was preset at the NAND gate at a time TO. According to the prior art, the remaining imaging devices within the Fibonacci ring oscillator are designed as inverters without switch-off functionality. Figure 3 shows the associated Ausgangssigna1 observed on the 3] _ Inverter. Applicant's investigations using a 31-length Fibonacci ring oscillator on a Spartan 3 FPGA from Xilinx have shown that in ren and devices of the prior art, a waiting time T2 of just under 20 ns after the time TO of the signal change at the output of the shutdown device 2 ^ passes, within which the oscillation stops at full amplitude.

This gives a lower limit for the time that has to lie between two random bit production processes and which can not be shortened according to the prior art if the random number generator is operated in a restart mode.

According to a second embodiment of the invention, all inverters within the Fibonacci ring oscillator are realized by NAND gates. Thus, an existing vibration can be stopped at each of the facilities.

FIG. 4 clearly shows how, almost immediately after the edge of the output signal at the first imaging device 2__, ie at the first NAND gate and thus the turn-off device 2], the output signal of the 3χ. NAND gates responded. The

Vibration is almost immediately suppressed. Within a period T, the amplitude of the oscillation has completely decreased. Investigations by the applicant with the Fibonacci ring oscillator of length 31 already described have shown that the waiting time can be significantly reduced until the oscillation has completely decayed.

In a third embodiment of the invention, not all mapping devices 2 -_ to 2 _{m are} configured as NAND gates within a ring oscillator circuit, but in particular a number n of inverters as mapping devices 3 _] _ to 3 _{n can be} provided between two NAND gates. In the case of a ring oscillator with a length m = 9, for example, every third of the digital imaging devices up to 2 g according to FIG. 5 can be a NAND gate. There are then n = 2 inverters installed between the NAND gates and the ring oscillator stops shortly after the application of a logical 0 at the NAND gates after about n + 1, ie 3, gate cycle times.

A gate cycle time is predetermined by the time duration that a signal change from the time of the input at a gate to the time at which the resulting from the signal change at the input signal change of an output signal of the gate arrives at the input of a subsequent gate, maximum requires. In the case of signal changes at an input which do not change an output signal, the gate cycle time is defined as zero. After a maximum of three gate cycle times, the ring oscillator is thus stopped. For complex vibration circuit designs is in a

Variant given a maximum time T, within which the oscillation should be decayed. Again, it can be specified that the propagating signal change meet within n + 1 gate cycle times on a gate with Abschaltfunktionalität.

In a multi-lobe oscillator according to FIG. 6, there are three channels or three tracks, which are fed to a respective imaging device 2 _... , 22, 23, 24. A first imaging device has three inputs and three outputs.

Signals from the three channels are respectively combined for each imaging device 2 _] , 22, 23, 24 and evaluated, for example, with loop-up tables LUT. Each lookup table LUT provides an output bit, whereby the output bit of each lookup table LUT is influenced by a change of a logic state on one of the three input signals. This duplicates a jitter that is used as a random source.

Between two imaging devices 2 _] _, 22 may be provided a first turn-off device 2 ^, wherein the first turn-off device 2 _] ^, for example, designed such that in each of the three channels via an AND gate AND a signal change is inhibited at this gate. A second The shut-off device 2_ is mounted between a third imaging device 23 and a fourth imaging device 24 in the form of AND gates AND in each of the three channels and jointly driven via an external signal S with the first shut-off device 2.

Claims

claims

1. An apparatus for generating random bits with a plurality of imaging devices (2] _ - 2 _m ) comprising electronic oscillating circuit (20), wherein in a vibration mode at an output node (3) of the oscillating circuit (20) a random signal (OS) with a random level profile can be tapped, wherein at least two of the plurality of imaging devices as activatable shutdown devices (2 ^, 2_) are configured and wherein the at least two turn-off devices (2 ^ -, 2] _) in an activated state, a respective output signal (A _] ^, A_) and the output signal (A ^ -, A_) in the

Oscillation circuit (20) propagating signal change stops.

2. Apparatus according to claim 1, wherein the respective turn-off device (2 _] ^, 2_) each have at least one first input

(El, El *) and in each case a second input (E2, E2 *) and in each case an output for the respective output signal (Α ^ -, A_), wherein the respective second input (E2, E2 *) has a Abschaltefunktionalität in that, after applying a switch-off signal at the respective second input (E2, E2 *), the respective output signals (A ^ -, A_) of the switch-off device are independent of respective input signals of the respective first inputs (El, El *) after a delay time.

3. Apparatus according to claim 1 or 2, wherein the oscillating circuit (20) is executed digitally and / or analog.

4. Device according to one of the preceding claims, wherein the respective turn-off device (2 ^, 2_) is designed as a logic gate or by look-up tables (LUT) is realized.

5. Device according to one of the preceding claims, wherein the oscillating circuit (20) is designed as a ring oscillator circuit and wherein of the plurality of imaging devices (2 _] _ - 2 _m ) a number n is formed as an inverter, and between the at least two defeat devices (2 ^ -, 2_) is arranged.

6. Device according to one of the preceding claims, wherein the respective turn-off device (2 ^ -, 2_) is designed as a NAND gate or as an AND gate.

7. Device according to one of the preceding claims, wherein the device is part of an FPGA device or an ASIC device.

8. Device according to one of the preceding claims, further comprising a buffer element (4), which is coupled to the output node (3) and which stores a logic level as a function of the random signal (OS).

9. Device according to one of the preceding claims, wherein the oscillating circuit (20) is designed as a Galois ring oscillator or a Fibonacci ring oscillator.

10. Device according to one of the preceding claims, wherein a period of time (T) can be predetermined, within which decays after applying a switch-off signal in the electronic oscillator circuit (20) propagating signal change.

11. Device according to one of claims 2 to 10, wherein the switch-off signal to the respective turn-off device (2 ^ -, 2_) almost simultaneously for the respective turn-off devices (2 _] ^, 2_) can be predetermined by a drive means.

12. Device according to one of claims 2 to 11, wherein the switch-off signal can be predetermined almost simultaneously with a sampling signal.

13. A method for generating random bits with a plurality of imaging devices (2 _] _ - 2 _m ) comprising electronic

Oscillating circuit (20), wherein in a vibration mode at an output node (3) of the oscillating circuit (20) a random signal (OS) is tapped with a random level profile,

wherein at least two of the plurality of imaging devices are configured as activatable shutdown devices (2 ^, 2] _), and wherein a respective one of the at least two shutdown devices (2] ^, 2_) in an activated state

Output signal (A ^ -, A] _) is generated and by the output signal (A ^ -, A_) in the oscillating circuit (20) propagating

Signal change stopped.

14. The method according to claim 13, wherein the respective switch-off device (2 ^ -, 2_) each have at least one first input

(El, El *) and in each case a second input (E2, E2 *) and in each case an output for the respective output signal (Α ^, A_), wherein through the respective second input

(E2, E2 *) a Abschaltefunktionalität is executed, so that after applying a shutdown signal at the respective second input (E2, E2 *) the respective outputs respective output signals (A ^, A_) of the respective turn-off device (2] ^, 2_) provide which are independent of respective input signals of the respective first inputs (El, El *) after a delay time.

15. The method of claim 13 or 14, wherein the oscillating circuit (20) is executed digitally and / or analog.

16. The method of any of claims 13 to 15, wherein the respective turn-off device (2 ^, 2 _] _) is formed as a logic gate or by look-up tables (LUT) is realized.

17. The method according to any one of claims 13 to 16, wherein the oscillating circuit (20) is formed as a ring oscillator circuit and wherein of the plurality of imaging devices (2] _ - 2 _m ) a number n is formed as an inverter and between the at least two defrosting devices (2 ^ -, 2_) is arranged.

18. The method according to any one of claims 13 to 17, wherein the respective turn-off device (2 ^ -, 2_) is formed as a NAND gate or as an AND gate.

19. The method according to any one of claims 13 to 18, wherein the method is carried out on an FPGA device or an ASIC device.

20. The method according to any one of claims 13 to 19, wherein an intermediate node to the output node (3) coupled

(4) stores a logic level in response to the random signal (OS).

21. The method according to any one of claims 13 to 20, wherein the oscillating circuit (20) as a Galois ring oscillator or a

Fibonacci ring oscillator is running.

22. The method according to any one of claims 13 to 21, wherein after applying a switch-off signal in the oscillating circuit (20) propagating signal change within a predetermined period of time (T) decays.

23. The method according to any one of claims 14 to 22, wherein the switch-off signal at the respective turn-off device (2 ^ -, 2_) is set almost simultaneously by a driving device.

24. The method according to any one of claims 14 to 23, wherein the turn-off signal is set almost simultaneously with a sampling signal.