JP3439606B2 - Ring oscillation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to, for example, a complementary type M
A large scale integrated circuit (hereinafter referred to as "CMOS") such as an OS (hereinafter referred to as "CMOS")
The present invention relates to a ring oscillation circuit composed of logic gates (referred to as "LSI"), and particularly to a ring oscillation circuit having a large frequency variation suitable for use in random number generation and the like.

[0002]

2. Description of the Related Art A ring oscillator circuit is a circuit that oscillates by directly returning the output side of a logic gate to the input side using a logic circuit such as CMOS, and uses analog elements such as capacitors and resistors. Instead, the oscillation frequency is determined by the delay time of the logic gate and the wiring. FIG. 2 is a circuit diagram showing a configuration of a conventional ring oscillator circuit. This ring oscillator circuit has an odd number of inverters 1, 2, ..., K connected in cascade, and the output side of the final stage inverter K is connected to the input side of the first stage inverter 1. There is. Then, the output signal OUT of this ring oscillation circuit is output to the output side of the inverter K.

Each of the inverters 1 to K is a circuit which inverts a signal applied to the input side and outputs it. Therefore, for example, when a "H" level signal is applied to the input side of the inverter 1 by applying a power supply voltage or the like, an "L" level signal is output to the output side of the final stage inverter K connected in an odd number of stages. Is output. Since this "L" level signal is given as an input signal to the inverter 1, this time, an "H" level signal is output to the output side of the inverter K. In this way, the output signal OUT output to the output side of the inverter K alternates between "L" level and "H" level. The speed of this change, that is, the oscillation frequency is determined by the delay time of the loop of the inverters 1 to K connected in a ring shape, but the circuit constants of these inverters 1 to K are affected by changes in temperature and power supply voltage. Since it is easy, the oscillation frequency of the ring oscillation circuit is unstable. The ring oscillator circuit may be applied to random number generation or noise signal generation by utilizing the simple circuit configuration of the ring oscillator circuit and the instability of the oscillation frequency. For example,
In the case of random number generation, the number of output pulses of the ring oscillator circuit is counted for a certain period of time, and the count value is used as a random number.

[0004]

However, the conventional ring oscillator circuit has the following problems. In random number generation, the more unstable the oscillation frequency, the more uniform the random number can be obtained. In order to increase the frequency fluctuation of the ring oscillator circuit, it is necessary to increase the number of inverter stages. However, when the number of stages of the inverter is increased, the oscillation frequency is lowered, and it is difficult to obtain effective random numbers in a short time. The present invention provides a ring oscillation circuit that solves the problems of the above-mentioned conventional techniques and that can obtain an output signal with large frequency fluctuation without lowering the oscillation frequency.

[0005]

In order to solve the above-mentioned problems, the first invention of the present invention comprises an LSI logic gate or the like, and an oscillation with a large frequency fluctuation due to mutual interference.
In a ring oscillator circuit for generating a signal , 2M +
1 (where M is a positive integer) inverting amplifiers are cascade-connected, and the first intermediate signal is output from the 2m−1 (where m is a positive integer not more than M) inverting amplifier. A first series circuit that outputs a first oscillation signal from the inverting amplifier at the final stage and 2N + 1 (where N is a positive integer) inverting amplifiers are connected in cascade, and 2n−1 (where n is N). Output a second intermediate signal from the inverting amplifier of the following positive integer),
Second output of the second oscillation signal from the inverting amplifier at the final stage
And a series circuit of. Furthermore, the ring oscillator circuit has a logic circuit for the first oscillation signal and the second intermediate signal .
The logical product or logical sum signal of the first stage of the first series circuit
A logical product or a logical sum of the first logic gate given to the inverting amplifier and the second oscillation signal and the first intermediate signal ;
A second logic gate for providing a signal to the first stage inverting amplifier of the second series circuit .

A second invention, the first logic gate in the first aspect of the present invention, the first oscillation signal and the second intermediate when activated by a first control signal for oscillation mode control The logical product of the signals or the logical sum of the signals is
The configuration is applied to the first stage inverting amplifier of the series circuit .
Further, the second logic gate, the logical product or logical sum of the second oscillation signal and the first intermediate signal when activated by a second control signal for oscillation mode control
The signal is given to the inverting amplifier at the first stage of the second series circuit . A third aspect of the invention is composed of an LSI logic gate or the like, and has a large frequency fluctuation due to mutual interference.
In a ring oscillating circuit for generating a signal, an odd number (three or more) of series circuits each inputting an interference signal and outputting an intermediate signal are connected in a ring shape.
And a ring circuit of, respectively connected to each of the series circuits,
Enter the intermediate signal given to the interference signal to the series circuit
And a plurality of second ring circuits.

Each of the series circuits has a first ring signal and a first logical product of the interference signals.
Connected to the output side of the first logic gate and connected to the output side of the first inverting amplifier group, which is connected to the output side of the first logic gate and connected in an odd number in series And a second inverting amplifier group connected in cascade to output the first ring signal to the series circuit in the subsequent stage. Further, each of the second ring circuits has a second
The logical product or logical sum of the ring signal and the intermediate signal
And a second logic gate that is connected to the output side of the second logic gate to connect the interference signal to the first logic gate.
An odd number of cascaded third inverting amplifier groups, and an even number of cascade connected third inverting amplifier groups are connected to the output side of the third inverting amplifier group to provide the second ring signal to the second logic gate. And a fourth inverting amplifier group.

According to the first aspect of the invention, since the ring oscillator circuit is constructed as described above, the following operation is performed.
The output signal of the first series circuit including an odd number of cascaded inverting amplifiers is fed back to the input side of the first stage inverting amplifier of the first series circuit via the first logic gate, and A ring oscillator circuit is constructed. Similarly second
A second ring oscillation circuit is configured by the serial circuit of and the second logic gate. Further, the first ring oscillation circuit outputs a first intermediate signal, and this intermediate signal is applied to the input side of the second logic gate of the second ring oscillation circuit. A second intermediate signal is output from the second ring oscillator circuit, and this intermediate signal is applied to the input side of the first logic gate of the first ring oscillator circuit. Therefore, the first
The ring oscillator circuit and the second ring oscillator circuit oscillate while giving mutual interference.

According to the second aspect of the invention, the first and second control signals for controlling the oscillation mode are applied to the first and second logic gates of the first aspect of the invention, respectively. . Therefore, the first and second signals are generated by the external signal.
The ring oscillator circuit is controlled to oscillate and stop. According to the third aspect of the present invention, a first series circuit including a first logic gate, an odd number of cascade-connected first inverting amplifier groups, and an even number of cascade-connected second inverting amplifier groups. The circuit
The first ring oscillation circuit is configured by connecting an odd number of rings. And for this first ring oscillator circuit,
An odd number of second ring oscillator circuits are connected so as to interfere with each other as in the first invention. As a result, the first ring oscillation circuit oscillates while interfering with the plurality of second ring oscillation circuits.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIG. 1 is a circuit diagram of a ring oscillator circuit showing a first embodiment of the present invention. This ring oscillation circuit has a first ring oscillation section 10 and a second ring oscillation section 20,
These ring oscillating units 10 and 20 are composed of LSI logic gates and the like. The first ring oscillator 10 includes a first series circuit including an odd number of cascaded inverting amplifiers (for example, CMOS inverters) 11 _{1 to} 11 _{2M + 1} (where M is a positive integer), and 2 It is composed of an input AND gate 12. The output side of the final stage inverter 11 _{2M + 1} is connected to the input terminal A of the AND gate 12, and this A
The output terminal D of the ND gate 12 is the inverter 11 of the first stage.
Connected to the input side of ₁ . Second ring oscillator 20
The odd number of inverters 21 ₁ to 21 connected in cascade
_It is composed of a second series circuit composed of _{2N + 1} (where N is a positive integer) and a 2-input AND gate 22. The output side of the final stage inverter 21 _{2N + 1} is the AND gate 22
Of the AND gate 22. The output terminal D of the AND gate 22 is connected to the input side of the _first- stage inverter 21 ₁ .

Further, the cascade-connected inverters 11 ₁ ...
The first intermediate signal IS1 is output from the output side of the odd-numbered inverter 11 _2m-1 of 11 _{2M + 1} , and this intermediate signal I
S1 is applied to the input terminal B of the AND gate 22. In addition, cascade connected inverters 21 _{1 to} 21 _{2N + 1}
The second intermediate signal IS2 is output from the output side of the odd-numbered inverter 21 _{2n-1 in} the
It is applied to the input terminal B of the ND gate 12. Then, the first and second oscillation signals (for example, output signals) OUT1 and OUT2 are output to the output sides of the inverter 11 _{2M + 1} and the inverter 21 _{2N + 1} , respectively. Next, the operation will be described. An output signal OUT1 and an intermediate signal I are input to the input terminals A and B of the AND gate 12, respectively.
S2 is given. Further, the output signal OUT2 and the intermediate signal IS are applied to the input terminals A and B of the AND gate 22, respectively.
1 is given.

Here, the input terminal A of the AND gate 12,
B and the logical value of the signal of the output terminal D,
The logical values of the signals at the input terminals A and B and the output terminal D of the AND gate 22 are "X", "Y", and "Z", respectively. AND gate 12
In, the following expression (1) is established. “W” = “U” · “V” (1) However, “·”: logical product On the other hand, the output signal “W” of the AND gate 12 is given to the input side of the inverter 11 ₁ and odd-numbered stages. Inverter 11
Since it is inverted by _{1 to} 11 _{2M + 1} , the following (2)
The formula holds. “U” = “W /” (2) However, “/”: Similarly to the inversion, by the odd-numbered inverters 21 _{1 to} 21 _2n-1 ,
The following expression (3) is established. “V” = “Z /” (3) Therefore, in the AND gate 12, the following expression (4) is established from the expressions (1) to (3). “W” = “W /” · “Z /” (4) In the AND gate 22, the following expression (5) is established. “Z” = “X” · “Y” (5) The output signal “Z” of the AND gate 22 is the inverter 21.
It is given to _one input side of the odd-numbered stage inverters 21 ₂₁ to
Since it is inverted and output by 1 _{2N + 1} , the following expression (6) is established. “X” = “Z /” (6) Similarly, by the odd-numbered stages of inverters 11 _{1 to} 11 _2m-1 ,
The following expression (7) is established. “Y” = “W /” (7) Therefore, in the AND gate 22, the following expression (8) is established from the expressions (5) to (7). “Z” = “Z /” · “W /” (8) As shown in equations (4) and (8), AND gate 1
It can be seen that the logical values "W" and "Z" of the output signals 2 and 22 are oscillating while interfering with each other.

Here, it is assumed that the output side of the even-numbered inverter 11 _2m of the cascade-connected inverters 11 _{1 to} 11 _{2M + 1} is connected to the input terminal B of the AND gate 22, and the cascade-connected inverters are connected. It is assumed that the output side of the even-numbered inverter 21 _2n of 21 _{1 to} 21 _{2N + 1} is connected to the input terminal B of the AND gate 12. The relationship between the input and output signals of the AND gate 12 is as shown in the following expression (9). “W” = “U” · “V” = “W /” · “Z” (9) Similarly, the relationship between the input / output signals of the AND gate 22 is as shown in the following equation (10). . “Z” = “X” · “Y” = “Z /” · “W” (10) Here, when the equation (10) is substituted into the equation (9), the following (1)
Equation (1) is obtained. "W" = "W /"-{"Z /"-"W"} = "W /"-"Z /"-"W" = "W /"-"W"-"Z /" = {" W / "·“ W ”} ·“ Z / ”=“ 0 ”·“ Z / ”=“ 0 ”(11) When the formula (11) is substituted into the formula (10),“ Z ”=“ 0 "
Becomes

This means that the output signals of the AND gates 12 and 22 are fixed at "0" and no oscillation is performed. Thus, the ring oscillator circuit of this embodiment has the following advantages (i) and (ii). (I) It has two ring oscillators 10 and 20, and the inverters 11 _2m-1 of odd-numbered stages of each ring oscillator 10 and 20 are
21 _2n-1 intermediate signals IS1 and IS2 receive AND gate 1
Since they interfere with each other via 2 and 22, output signals OUT1 and OUT2 having large fluctuations in the oscillation frequency can be obtained. For example, the result of computer simulation analysis of the operation of a circuit in which the inverters 11 ₁ , ..., 21 ₁ , ... Of the ring oscillators 10 and 20 of FIG.
It has been confirmed that a pulse having a pulse width corresponding to a frequency of 150 kHz to 2.1 MHz is output to UT1 and OUT2 while randomly changing. (Ii) Since it is composed of only logic circuits without using analog elements such as capacitance and resistance, it is easy to apply to digital LSI and the like.

Second Embodiment FIG. 3 is a circuit diagram of a ring oscillator circuit showing a second embodiment of the present invention. Elements common to those in FIG. 1 are designated by common reference numerals. . The ring oscillating circuit of the second embodiment has a 2-input AND gate 1 in each of the ring oscillating units 10 and 20 in place of the ring oscillating units 10 and 20 shown in FIG.
Ring oscillators 10A and 20A are provided, in which 2 and 22 are replaced with 2-input OR gates 13 and 23. The other circuits are the same as those in FIG. The outline of the operation of the ring oscillator circuit of FIG. 3 is as follows. Here, the logical values of the signals at the input terminals A and B and the output terminal D of the OR gate 13 are set to "U", "V", and "W", respectively, and the input terminals A and B and the output of the OR gate 23 are output. The logical values of the signal at the terminal D are "X", "Y", and "Z", respectively.

In the OR gates 13 and 23, the following expression (12) is established. “W” = “U” + “V” = “W /” + “Z /” “Z” = “X” + “Y” = “Z /” + “W /” (12) “+”: Logical sum Therefore, the following expression (13) is established. “W” = “W /” + “{“ Z / ”+“ W / ”} /” = “W /” + “Z” / “W” “Z” = “Z /” + “{“ W / “+“ Z / ”} /” = “Z /” + “Z” · “W” (13) As shown by the equation (13), the logical value of the output signal of the OR gates 13 and 23 is “ It can be seen that W ”and“ Z ”are oscillating while mutually interfering with each other.

Here, it is assumed that the output side of the even-numbered inverter 11 _2m of the cascaded inverters 11 _{1 to} 11 _{2M + 1} is connected to the input terminal B of the OR gate 23, and the cascaded inverters are connected. It is assumed that the output side of the even-numbered inverter 21 _2n of 21 _{1 to} 21 _{2N + 1} is connected to the input terminal B of the OR gate 13. The relationship between the input / output signals of the OR gates 13 and 23 is as shown in the following expression (14). “W” = “U” + “V” = “W /” + “Z” “Z” = “X” + “Y” = “Z /” + “W” (14) Therefore, the following Equation (15) holds. “W” = “W /” + “Z /” + “W” = “W /” + “W” + “Z /” = “1” + “Z /” = “1” “Z” = “Z / ”+“ W / ”+“ Z ”=“ Z / ”+“ Z ”+“ W / ”=“ 1 ”+“ W / ”=“ 1 ”(15) This is the OR gate 13 , 23 are fixed at "1", which means that oscillation is not performed. As described above, in the ring oscillation circuit of the second embodiment, the two ring oscillation units 10A and 20A are
Since the oscillators oscillate while interfering with each other through the R gates 13 and 23, the output signal OUT with a large fluctuation in oscillation frequency
1 and OUT2 can be obtained. Further, it can be applied when it is more convenient to use an OR gate due to the configuration of the LSI.

Third Embodiment FIG. 4 is a circuit diagram of a ring oscillator circuit showing a third embodiment of the present invention. Elements common to those in FIG. 1 are designated by common reference numerals. . The ring oscillating circuit of the third embodiment has ring oscillating units 10B and 20B having a configuration different from that of the ring oscillating units 10 and 20 of FIG. The ring oscillator 10B has the same inverters 11 _{1 to} 11 as those in FIG.
_{It is} composed of a first series circuit composed of _{2M + 1} and a 3-input AND gate 14 different from that shown in FIG. Ring oscillator 2
0B is composed of a second series circuit composed of inverters 21 _{1 to} 21 _{2N + 1} similar to that of FIG. 1 and a 3-input AND gate 24 different from that of FIG. And AND gate 1
Control signals CTRL1 and CTRL2 for controlling the oscillation mode are applied to the input terminals C of 4 and 24, respectively. The other circuits are the same as those in FIG.

FIG. 5 shows control signals CTRL1 and CTRL2 of the ring oscillator circuit of FIG. 4 and control signals CTRL1 and CTRL1 thereof.
It is a figure which shows the relationship of the output of the ring oscillation parts 10B and 20B corresponding to CTRL2. Control signals CTRL1, CTR
If both L2 are "0", the ring oscillator 10B,
Both 20B stop oscillation. Control signal CTRL
If 1 is "0" and the control signal CTRL2 is "1", the ring oscillating unit 10B stops oscillation and the ring oscillating unit 20B
Oscillates independently. If the control signal CTRL1 is "1" and the control signal CTRL2 is "0", the ring oscillator 10B
Oscillates independently, and the ring oscillating unit 20B stops oscillating. Further, if both the control signals CTRL1 and CTRL2 are "1", the ring oscillators 10B and 20B have the same configuration as in FIG.
Similar to the ring oscillator circuit, they oscillate by interfering with each other. As described above, the ring oscillator circuit according to the third embodiment has three inputs A
Since the ND gates 14 and 24 are included, it is possible to control the oscillation mode and there is an advantage that the frequency variation amount can be switched.

Fourth Embodiment FIG. 6 is a circuit diagram of a ring oscillator circuit showing a fourth embodiment of the present invention. This ring oscillator circuit includes a first ring circuit (for example, a ring oscillator) 30 and three sets of second ring circuits (for example, a ring oscillator) 40, 50, 60. The ring oscillator 30 includes three series circuits 3
0A, 30B and 30C are connected in a ring shape. The series circuit 30A includes a first logic gate (for example, a 2-input AND gate) 31A, a first inverting amplifier group (for example, an odd inverter circuit) 32A in which an odd number of inverters are connected in cascade, and an even number of inverters. And a second inverting amplifier group (for example, an even inverter circuit) 33A connected in cascade. Similarly, the series circuit 30
B is an AND gate 31B and an odd inverter circuit 32.
B and an even inverter circuit 33B.
The series circuit 30C includes an AND gate 31C, an odd inverter circuit 32C, and an even inverter circuit 33C.

The output side of the AND gate 31A of the series circuit 30A is connected to the input side of the odd number inverter circuit 32A. The output side of the odd inverter circuit 32A is connected to the input side of the even inverter circuit 33A. The output side of the even-numbered inverter circuit 33A is the AN of the series circuit 30B.
It is connected to the first input terminal of the D gate 31B. The connection relationship between the series circuits 30B and 30C is the series circuit 3
Same as 0A. The ring oscillator 40 includes a second logic gate (for example, a 2-input AND gate) 41, a third inverting amplifier group (for example, an odd inverter circuit) 42 in which an odd number of inverters are connected in cascade, and an even number of inverters. And a fourth inverting amplifier group (for example, an even inverter circuit) 43 connected in cascade. The output side of the odd inverter circuit 32A of the series circuit 30A is connected to the first input terminal of the AND gate 41, and the input side of the odd inverter circuit 42 is connected to the output side of the AND gate 41. The output side of the odd inverter circuit 42 is commonly connected to the second input terminal of the AND gate 31A in the series circuit 30A and the input side of the even inverter circuit 43. The output side of the even inverter circuit 43 is connected to the second input terminal of the AND gate 41.

The ring oscillating units 50 and 60 have the same structure as the ring oscillating unit 40.
In the same state as 0, the series circuit 30 of the ring oscillator 30
B and 30C, respectively. The output signal OUT of the ring oscillator circuit is output from the output side of the even-numbered inverter circuit 33C of the ring oscillator unit 30. The operation of the ring oscillating circuit of the fourth embodiment is similar to that of the ring oscillating circuit of FIG. 1 in that a plurality of ring oscillating units (for example, the ring oscillating units 30 and 40) interfere with each other and oscillate. It is almost the same. However, the second ring circuit (that is, the ring oscillating unit 40, which is connected to the first ring circuit (that is, the ring oscillating unit 30))
Since there are three (50, 60), there is an advantage that the output signal OUT having a larger frequency fluctuation can be obtained as compared with the ring oscillation circuit of FIG. The present invention is not limited to the above embodiment, and various modifications can be made. Examples of this modification include the following (a) to (e).

(A) As an inverting amplifier, the inverter 1
11 ₁ , ..., 21 ₁ , ... are used, but not limited to an inverter, any active circuit such as NOR, NAND or the like which inverts and outputs an input signal can be used in any circuit. can do. (B) In the ring oscillator circuit of FIG. 4, the 3-input AND gates 14 and 24 are used, but a ring oscillator circuit having a similar function can be configured by using a 3-input OR gate. In that case, the control signals CTRL1, CTR
The relationship between the value of L2 and the outputs of the ring oscillators 10A and 20A is different from that shown in FIG. (C) The ring oscillation circuit of FIG. 6 includes three sets of ring oscillation units 40, 50, 60, but an arbitrary odd number of ring oscillation units 40, ... Can be provided. By providing a large number of ring oscillating units 40, ..., A ring oscillating circuit having a larger frequency change can be configured. (D) In FIGS. 1, 3, 4, and 6, the output signal OU
Although T is taken out from the output side of a specific inverter 11, the same output signal can be obtained even if this output signal OUT is taken out from the output side of any circuit element forming the ring. (E) The random number generation has been described as an application example of the ring oscillation circuit of the present invention. However, in addition to the random number generation in a game machine or a cryptographic device, it can be used as a broadband noise generator by converting an output signal into an analog amount. It can be applied.

[0024]

As described in detail above, according to the first aspect of the invention, the first ring oscillation circuit including the first series circuit and the first logic gate, the second series circuit, and The second ring oscillation circuit including the second logic gate outputs the intermediate signal to the other side so as to interfere with each other via the first and second logic gates. Therefore, it is possible to obtain an oscillation signal with a large frequency change. According to the second invention, a control signal for controlling the oscillation mode is applied to each of the first and second logic gates in the first invention. Therefore, it is possible to control the oscillation and stop of the ring oscillation circuit. According to the third invention, an odd number (three or more) of the second ring oscillation circuits are connected to the first ring oscillation circuit so as to interfere with each other. Therefore, it is possible to obtain an oscillation signal with a larger frequency change than in the first invention.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a ring oscillator circuit showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional ring oscillator circuit.

FIG. 3 is a circuit diagram of a ring oscillator circuit showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a ring oscillator circuit showing a third embodiment of the present invention.

5 is a diagram showing a relationship of outputs of the ring oscillator corresponding to the control signal of FIG.

FIG. 6 is a circuit diagram of a ring oscillator circuit showing a fourth embodiment of the present invention.

[Explanation of symbols]

10, 10A, 10B, 20, 20A, 20B, 30,
40, 50, 60 ring oscillators 11 ₁ , 11 ₂ , ..., 21 ₁ , 21 ₂ , ...
Inverters 12, 14, 22, 24, 31A, 31B, 31C
AND gates 13 and 23
OR gates 30A, 30B, 30C
Series circuit 32A, 32B, 32C
Odd inverter circuit 33A, 33B, 33C
Even inverter circuit

Claims (3)

(57) [Claims] 1. Mutual interference causes a large frequency fluctuation.
A ring oscillator circuit for generating a swing signal, wherein 2M + 1 (where M is a positive integer) inverting amplifiers are cascade-connected, and 2m-1 (where m is a positive integer not more than M) stages thereof. A first series circuit that outputs a first intermediate signal from the eye inverting amplifier and a first oscillating signal from the final stage inverting amplifier and 2N + 1 (where N is a positive integer) inverting amplifiers A second intermediate signal is output from the inverting amplifier of the 2n−1th stage (where n is a positive integer equal to or less than N) of the cascade connection and a second oscillation signal is output from the inverting amplifier of the final stage. Two serial circuits, and a logical product of the first oscillation signal and the second intermediate signal .
Or the signal of the logical sum is added to the inversion of the first stage of the first series circuit.
A first logic gate applied to the width divider, and a logical product of the second oscillation signal and the first intermediate signal .
Or the signal of the logical sum is inverted and increased in the first stage of the second series circuit.
A ring oscillator circuit comprising: a second logic gate provided to the width device . 2. A logical product of the first oscillation signal and the second intermediate signal when the first logic gate is activated by a first control signal for controlling an oscillation mode, or
The OR signal is used as the first stage inverting amplifier of the first series circuit.
The second logic gate is configured to provide a logical product or a logical sum of the second oscillation signal and the first intermediate signal when activated by the second control signal for controlling the oscillation mode . Signal
2. The ring oscillator circuit according to claim 1, wherein the ring oscillator circuit is configured to be applied to the first stage inverting amplifier of the second series circuit. 3. A frequency variation is large due to mutual interference.
A first ring circuit, which is a ring oscillation circuit for generating a swing signal, in which an odd number (three or more) of series circuits each of which receives an interference signal and outputs an intermediate signal are connected in a ring shape. A plurality of second circuit elements connected to the respective series circuits and adapted to input the intermediate signal to give the interference signals to the series circuits.
And a ring circuit of each of the series circuits, the first ring signal and the interference signal.
A first logic gate that takes a logical product or a logical sum of, and an odd number of cascaded first inverting amplifier groups connected to the output side of the first logic gate and outputting the intermediate signal,
An even number of cascaded second inverting amplifier groups connected to the output side of the first inverting amplifier group and outputting the first ring signal to the series circuit in the subsequent stage, The ring circuit is connected to a second logic gate that obtains a logical product or a logical sum of a second ring signal and the intermediate signal , and an output side of the second logic gate to connect the interference signal to the first logic. odd number cascaded third inverting amplifier group, said third inverting amplifier group output being connected to the side the second the second ring signal applied to the gate
And an even number of fourth inverting amplifier groups connected in cascade to each other.