EP2282249B1 - Current mirror system - Google Patents

Current mirror system Download PDF

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Publication number
EP2282249B1
EP2282249B1 EP10184332.4A EP10184332A EP2282249B1 EP 2282249 B1 EP2282249 B1 EP 2282249B1 EP 10184332 A EP10184332 A EP 10184332A EP 2282249 B1 EP2282249 B1 EP 2282249B1
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Prior art keywords
transistor
current
current mirror
controlled
mirror assembly
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EP10184332.4A
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German (de)
French (fr)
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EP2282249A1 (en
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Jakob Jongsma
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Ams Osram AG
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Ams AG
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the present invention relates to a current mirror arrangement.
  • Current mirrors can be applied in different circuit techniques or integration techniques, for example in MOS, metal oxide semiconductor, circuit technology.
  • FIGS. 2a, 2b show in it FIGS. 2a, 2b respective amplifier stages 12A, 12B that generate complementary bias currents. These will be the in FIGS. 3a, 3b supplied shown temperature compensation stages. At outputs MIRN, MIRP, temperature and supply voltage compensated bias currents are provided.
  • FIG. 1 shows an exemplary, known current mirror, which has two transistors 2, 3 connected to a reference potential terminal 1.
  • the transistors 2, 3 of the Stromspielgels are each of the n-type conductivity and connected directly to each other at their control terminals.
  • the input-side transistor 2 of the current mirror has a controlled path, which is connected with a first terminal to the gate terminal of the transistor 2 and with another terminal to the reference potential terminal 1.
  • the one with the Gate terminal of the transistor 2 connected terminal of the controlled path of the transistor 2 is further connected via a current source 4 to a supply potential terminal 5.
  • the transistor 3 of FIG. 1 has a controlled path, on the one hand to the reference potential terminal 1 and on the other hand to a terminal of another transistor. 6 connected is.
  • the further transistor 6 is connected to the supply potential connection 5 with a further connection of its controlled path and of the p-conductivity type.
  • the control terminal of the transistor 6 is connected to that terminal of its controlled path, which is connected to the transistor 3.
  • the circuit according to FIG. 1 serves to generate two bias signals, namely on the one hand a bias signal NBIAS for n-MOS devices and on the other hand, a bias signal PBIAS for p-MOS devices.
  • the bias signal NBIAS can be tapped off at the control terminals of the n-channel transistors 2, 3 at an output terminal 7.
  • Another output terminal 8, which is connected to the control terminal of the transistor 6, serves as an output for picking up the PBIAS signal.
  • FIG. 2 shows a development of the circuit of FIG. 1 which largely corresponds to this in the components used and their mode of operation, but is supplemented by a cascode stage 9, 10.
  • the cascode stage 9, 10 comprises two transistors, of which one each is connected in the current paths between the current source 4 and the transistor 2 and between the diode 6 and the transistor 3.
  • the transistors 9, 10 of the cascode stage, of which transistor 9 is connected as a diode in turn together form a current mirror.
  • FIG. 1 Opposite the circuit of FIG. 1 has the current mirror arrangement of FIG. 2 with cascode an improved match of the signals NBIAS and PBIAS with each other. Nevertheless, also in the circuit according to FIG. 2 no exact match of the bias signals for components of the opposite, that is to say complementary, conductivity type ensured.
  • NBIAS and PBIAS signals it is desirable to achieve an exact match between NBIAS and PBIAS signals, for example, to operate transistors of complementary conductivity type at matching operating points and / or to provide circuits with high symmetry and good matching.
  • the object of the present invention is to specify a current mirror arrangement which makes it possible to emit two bias currents which coincide very closely with one another and are suitable for driving integrated components of different conductivity types.
  • the proposed principle to provide two transistors of different conductivity type each for delivering a current suitable as a bias signal.
  • the first and the second transistor are driven so that they are not themselves the respective output transistor of a current mirror. Rather, the invention provides that the output transistor of a current mirror is designed as a controlled current source, which is connected between the first and the second transistor.
  • the proposed current mirror arrangement Due to the interconnection of the proposed current mirror arrangement, it is possible, at the first transistor and the second transistor exactly coincident currents to generate, which allow the respective control of complementary components in high-precision manner. In this case, with additional advantage of the circuit complexity compared to a conventional current mirror arrangement for providing complementary bias signals low. As a result, the proposed principle with relatively small chip area and thus be integrated cost.
  • the controlled current source which forms the output of the current mirror which drives the first and second transistors, is preferably designed as a so-called floating current source, ie for operation with a floating potential.
  • floating potential is sometimes referred to as floating potential.
  • the first transistor, the controlled current source and the second transistor are preferably arranged in a common current path.
  • the controlled current source arranged in the middle between the two transistors, which itself has floating potential, ensures that the currents through the first and second transistors are identical and thus a further improved match between the two emitted bias currents of the current mirror arrangement is present.
  • the two conductivity types of the transistors are preferably a p-conductivity type and an n-conductivity type. This means that the first transistor is preferably a p-channel transistor and the second transistor is a complementary n-channel transistor.
  • the first transistor and the second transistor are preferably each connected as a diode.
  • the first current and the second current are each tapped at the load connection of the first and second transistor connected to the controlled current source.
  • control connection of the respective transistor is connected to this tap node to form a diode.
  • the common current path which comprises the series connection of the first transistor, controlled current source and second transistor, is preferably connected between a supply potential terminal and a reference potential terminal.
  • the controlled current source itself is preferably also designed as a transistor, namely as a current source transistor, whose controlled path forms a series circuit with the controlled paths of the first and second transistors.
  • the controlled current source preferably forms the current mirror with a diode-connected transistor, wherein the diode-connected transistor is further preferably arranged in a further current path which is fed by an input-side current source.
  • the current source in the further current path serves as a reference current source.
  • the further current path further preferably includes a further diode, which is connected between the input-side transistor of the current mirror and the reference potential or supply potential connection.
  • a further transistor may be provided, which together with the second transistor forms a feedback current mirror, wherein the second transistor is connected as a diode.
  • the two current mirrors of this further developed current mirror arrangement form together a so-called Wilson current mirror.
  • the current mirror arrangement is preferably produced in integrated circuit construction.
  • the current mirror arrangement is preferably integrated in unipolar circuit technology, for example a metal-insulator-semiconductor structure.
  • the current mirror arrangement is preferably constructed in complementary MOS circuit technology.
  • the proposed current mirror arrangement also works in the complementary circuit variant, which means that all n-channel conductivity type MOS transistors are replaced by p-channel devices and vice versa.
  • FIG. 3 shows a current mirror arrangement according to the proposed principle with a first transistor 11, which is of a p-type conductivity, and with a second transistor 12, which is of an n-type conductivity.
  • the first and the second transistor 11, 12 each have a control terminal and one controlled path each. Between each one terminal of the controlled paths of the transistors 11, 12, a current source 13 is connected.
  • the free connection of the controlled path of the transistor 11 is connected to a supply potential connection 14 and the free connection of the controlled path of the second transistor 12 to a reference potential connection 15.
  • the connected to the current source 13 terminals of the controlled paths of the transistors 11, 12 are connected to the respective control terminal of the associated transistor 11, 12 to form a diode and at the same time form outputs 16, 17 of the current mirror assembly.
  • the first output 16 is designed to deliver a first one Current PBIAS, while the second output 17 is designed to deliver a second, the first complementary current NBIAS.
  • First and second currents serve as complementary BIAS signals.
  • the current source 13 is designed as a floating current source, that is to say with a floating potential.
  • a further current path is provided, which is designed to be traversed by a reference current I REF .
  • a reference current I REF To couple these two current paths is a in FIG. 3 not explicitly drawn current mirror provided, which is indicated by the fact that the controlled current source 13 is traversed by the n-times the reference current I REF of the first current path.
  • the letter n represents the mirror ratio of the current mirror.
  • the proposed circuit has a low component cost and is inexpensive to integrate with a small chip area and therefore.
  • FIG. 4 A development of the circuit of FIG. 3 for generating identical n-MOS and p-MOS currents by means of a current mirror arrangement FIG. 4 ,
  • the circuit of FIG. 4 agrees in the components used, their advantageous interconnection and operation largely with that of FIG. 3 and will not be repeated at this point.
  • the floating powered controlled current source 13 is at FIG. 4 is formed as a transistor 13 ', which forms the current mirror 18, 13' with an input transistor 18.
  • the input transistor 18 is connected as a diode.
  • the transistor 18 is of the n-channel type.
  • a current source 19 is provided, which connects a supply potential terminal 14 to a terminal of the controlled path of the diode transistor 18, which is also connected to its gate terminal.
  • Another transistor diode 20, also of the n-conductivity type connects the transistor 18 to the reference potential terminal 15.
  • the reference current source 19, the transistor 18 and the diode 20 together form a series circuit.
  • FIG. 5 shows a further embodiment of a development of a current mirror arrangement according to the proposed principle.
  • the circuit of FIG. 5 agrees in the components used, their interconnection with each other and their advantageous operation largely with that of FIG. 4 and will not be described again at this point.
  • the control terminal of there with reference numeral 20 ' provided transistor connected to the gate terminal of the second transistor 12.
  • the transistors 12, 20 ' together form a feedback current mirror, which together with the current mirror 18, 13', which operates in the forward direction, forms a Wilson current mirror.
  • the Wilson current mirror 18, 13 '; 12, 20 ' forms a closed loop.
  • bias signals PBIAS, NBIAS which can be tapped off at the outputs 16, 17 exactly match one another.

Description

Die vorliegende Erfindung betrifft eine Stromspiegelanordnung.The present invention relates to a current mirror arrangement.

Stromspiegel sind als Grundschaltungen mit Transistoren bekannt und beispielsweise in U. Tietze, Ch. Schenk: "Halbleiter-Schaltungstechnik", 10. Auflage 1993, S. 62 bis 63 , beschrieben.Current mirrors are known as basic circuits with transistors and, for example, in U. Tietze, Ch. Schenk: "semiconductor circuit technology", 10th edition 1993, pp 62 to 63 , described.

Stromspiegel können in unterschiedlichen Schaltungstechniken oder Integrationstechniken, beispielsweise in MOS, Metal Oxide Semiconductor, -Schaltungstechnik angewandt werden.Current mirrors can be applied in different circuit techniques or integration techniques, for example in MOS, metal oxide semiconductor, circuit technology.

In dem Dokument US 5,694,073 ist ein Schaltkreis angegeben, der Versorgungsspannung und Temperatur detektiert. Darin zeigen Figuren 2a, 2b jeweilige Verstärkerstufen 12A, 12B, die komplementäre Bias-Ströme erzeugen. Diese werden den in Figuren 3a, 3b gezeigten Temperatur-Kompensationsstufen zugeführt. An Ausgängen MIRN, MIRP werden temperatur- und versorgungsspannungskompensierte Bias-Ströme bereitgestellt.In the document US 5,694,073 a circuit is specified, which detects supply voltage and temperature. Show in it FIGS. 2a, 2b respective amplifier stages 12A, 12B that generate complementary bias currents. These will be the in FIGS. 3a, 3b supplied shown temperature compensation stages. At outputs MIRN, MIRP, temperature and supply voltage compensated bias currents are provided.

Figur 1 zeigt einen beispielhaften, bekannten Stromspiegel, der zwei gegen einen Bezugspotenzialanschluss 1 geschaltete Transistoren 2, 3 aufweist. Die Transistoren 2, 3 des Stromspielgels sind jeweils vom n-Leitfähigkeitstyp und an ihren Steueranschlüssen unmittelbar miteinander verbunden. Der eingangsseitige Transistor 2 des Stromspiegels hat eine gesteuerte Strecke, die mit einem ersten Anschluss mit dem Gate-Anschluss des Transistors 2 und mit einem weiteren Anschluss mit dem Bezugspotenzialanschluss 1 verbunden ist. Der mit dem Gate-Anschluss des Transistors 2 verbundene Anschluss der gesteuerten Strecke des Transistors 2 ist weiterhin über eine Stromquelle 4 an einen Versorgungspotenzialanschluss 5 geschaltet. FIG. 1 shows an exemplary, known current mirror, which has two transistors 2, 3 connected to a reference potential terminal 1. The transistors 2, 3 of the Stromspielgels are each of the n-type conductivity and connected directly to each other at their control terminals. The input-side transistor 2 of the current mirror has a controlled path, which is connected with a first terminal to the gate terminal of the transistor 2 and with another terminal to the reference potential terminal 1. The one with the Gate terminal of the transistor 2 connected terminal of the controlled path of the transistor 2 is further connected via a current source 4 to a supply potential terminal 5.

Auch der Transistor 3 von Figur 1 hat eine gesteuerte Strecke, die einerseits mit dem Bezugspotenzialanschluss 1 und andererseits mit einem Anschluss eines weiteren Transistors 6 verbunden ist. Der weitere Transistor 6 ist mit einem weiteren Anschluss seiner gesteuerten Strecke mit dem Versorgungspotenzialanschluss 5 verbunden und vom p-Leitfähigkeitstyp. Der Steueranschluss des Transistors 6 ist mit demjenigen Anschluss seiner gesteuerten Strecke verbunden, der mit dem Transistor 3 verbunden ist.Also, the transistor 3 of FIG. 1 has a controlled path, on the one hand to the reference potential terminal 1 and on the other hand to a terminal of another transistor. 6 connected is. The further transistor 6 is connected to the supply potential connection 5 with a further connection of its controlled path and of the p-conductivity type. The control terminal of the transistor 6 is connected to that terminal of its controlled path, which is connected to the transistor 3.

Die Schaltung gemäß Figur 1 dient zur Erzeugung zweier Bias-Signale, nämlich einerseits eines Bias-Signals NBIAS für n-MOS-Bauteile und andererseits eines Bias-Signals PBIAS für p-MOS-Bauteile. Das Bias-Signal NBIAS ist an den Steueranschlüssen der n-Kanal-Transistoren 2, 3 an einem Ausgangsanschluss 7 abgreifbar. Ein weiterer Ausgangsanschluss 8, der mit dem Steueranschluss des Transistors 6 verbunden ist, dient als Ausgang zum Abgreifen des PBIAS-Signals.The circuit according to FIG. 1 serves to generate two bias signals, namely on the one hand a bias signal NBIAS for n-MOS devices and on the other hand, a bias signal PBIAS for p-MOS devices. The bias signal NBIAS can be tapped off at the control terminals of the n-channel transistors 2, 3 at an output terminal 7. Another output terminal 8, which is connected to the control terminal of the transistor 6, serves as an output for picking up the PBIAS signal.

Figur 2 zeigt eine Weiterbildung der Schaltung von Figur 1, die dieser in den verwendeten Bauteilen und deren Funktionsweise weitgehend entspricht, jedoch um eine Kaskode-Stufe 9, 10 ergänzt ist. Die Kaskode-Stufe 9, 10 umfasst zwei Transistoren, von denen je einer in die Strompfade zwischen Stromquelle 4 und Transistor 2 sowie zwischen Diode 6 und Transistor 3 geschaltet sind. Dabei bilden die Transistoren 9, 10 der Kaskode-Stufe, von denen Transistor 9 als Diode verschaltet ist, selbst wiederum gemeinsam einen Stromspiegel. FIG. 2 shows a development of the circuit of FIG. 1 which largely corresponds to this in the components used and their mode of operation, but is supplemented by a cascode stage 9, 10. The cascode stage 9, 10 comprises two transistors, of which one each is connected in the current paths between the current source 4 and the transistor 2 and between the diode 6 and the transistor 3. In this case, the transistors 9, 10 of the cascode stage, of which transistor 9 is connected as a diode, in turn together form a current mirror.

Gegenüber der Schaltung von Figur 1 hat die Stromspiegelanordnung von Figur 2 mit Kaskode eine verbesserte Übereinstimmung der Signale NBIAS und PBIAS miteinander. Gleichwohl ist auch bei der Schaltung gemäß Figur 2 keine exakte Übereinstimmung der Bias-Signale für Bauteile vom entgegengesetzten, das heißt komplementären, Leitfähigkeitstyp gewährleistet.Opposite the circuit of FIG. 1 has the current mirror arrangement of FIG. 2 with cascode an improved match of the signals NBIAS and PBIAS with each other. Nevertheless, also in the circuit according to FIG. 2 no exact match of the bias signals for components of the opposite, that is to say complementary, conductivity type ensured.

Vielmehr können auch die Bias-Signale bei der Schaltung von Figur 2 bemerkenswert voneinander abweichen.Rather, the bias signals in the circuit of FIG. 2 remarkably different from each other.

Es ist jedoch in vielen Anwendungen wünschenswert, eine exakte Übereinstimmung zwischen NBIAS- und PBIAS-Signal zu erzielen, um beispielsweise Transistoren von komplementärem Leitfähigkeitstyp in je übereinstimmenden Arbeitspunkten zu betreiben und/oder Schaltungen mit hoher Symmetrie und gutem Matching zu schaffen.However, in many applications, it is desirable to achieve an exact match between NBIAS and PBIAS signals, for example, to operate transistors of complementary conductivity type at matching operating points and / or to provide circuits with high symmetry and good matching.

Aufgabe der vorliegenden Erfindung ist es, eine Stromspiegelanordnung anzugeben, die es ermöglicht, zwei Bias-Ströme abzugeben, die sehr genau miteinander übereinstimmen und zur Ansteuerung von integrierten Bauteilen unterschiedlichen Leitfähigkeitstyps geeignet sind.The object of the present invention is to specify a current mirror arrangement which makes it possible to emit two bias currents which coincide very closely with one another and are suitable for driving integrated components of different conductivity types.

Erfindungsgemäß wird die Aufgabe durch eine Stromspiegelanordnung gelöst, aufweisend die Merkmale des Anspruchs 1.According to the invention the object is achieved by a current mirror arrangement, comprising the features of claim 1.

Es entspricht dem vorgeschlagenen Prinzip, zwei Transistoren vorzusehen, die von unterschiedlichem Leitfähigkeitstyp sind und je zur Abgabe eines Stroms dienen, der als Bias-Signal geeignet ist. Der erste und der zweite Transistor werden dabei so angesteuert, dass sie nicht selbst der jeweilige Ausgangstransistor eines Stromspiegels sind. Vielmehr ist erfindungsgemäß vorgesehen, dass der Ausgangstransistor eines Stromspiegels als gesteuerte Stromquelle ausgeführt ist, die zwischen den ersten und den zweiten Transistor geschaltet ist.It is the proposed principle to provide two transistors of different conductivity type each for delivering a current suitable as a bias signal. The first and the second transistor are driven so that they are not themselves the respective output transistor of a current mirror. Rather, the invention provides that the output transistor of a current mirror is designed as a controlled current source, which is connected between the first and the second transistor.

Aufgrund der Verschaltung der vorgeschlagenen Stromspiegelanordnung ist es möglich, an dem ersten Transistor und dem zweiten Transistor exakt miteinander übereinstimmende Ströme zu generieren, die die jeweilige Ansteuerung komplementärer Bauteile in hochpräziser Weise ermöglichen. Dabei ist mit zusätzlichem Vorteil der Schaltungsaufwand gegenüber einer herkömmlichen Stromspiegelanordnung zur Bereitstellung von komplementären Bias-Signalen gering. Dadurch kann das vorgeschlagene Prinzip mit verhältnismäßig geringer Chipfläche und somit kostengünstig integriert werden.Due to the interconnection of the proposed current mirror arrangement, it is possible, at the first transistor and the second transistor exactly coincident currents to generate, which allow the respective control of complementary components in high-precision manner. In this case, with additional advantage of the circuit complexity compared to a conventional current mirror arrangement for providing complementary bias signals low. As a result, the proposed principle with relatively small chip area and thus be integrated cost.

Die gesteuerte Stromquelle, die den Ausgang des den ersten und zweiten Transistor ansteuernden Stromspiegels bildet, ist bevorzugt als so genannte floatende Stromquelle, also zum Betrieb mit schwebendem Potenzial, ausgelegt. Ein schwebendes Potenzial wird gelegentlich auch als schwimmendes Potenzial bezeichnet.The controlled current source, which forms the output of the current mirror which drives the first and second transistors, is preferably designed as a so-called floating current source, ie for operation with a floating potential. Floating potential is sometimes referred to as floating potential.

Der erste Transistor, die gesteuerte Stromquelle und der zweite Transistor sind bevorzugt in einem gemeinsamen Strompfad angeordnet. Dabei stellt die in der Mitte zwischen den beiden Transistoren angeordnete, gesteuerte Stromquelle, die selbst floatendes Potenzial hat, sicher, dass die Ströme durch ersten und zweiten Transistor identisch groß sind und somit eine noch weiter verbesserte Übereinstimmung zwischen den beiden abgegebenen Bias-Strömen der Stromspiegelanordnung vorliegt.The first transistor, the controlled current source and the second transistor are preferably arranged in a common current path. The controlled current source arranged in the middle between the two transistors, which itself has floating potential, ensures that the currents through the first and second transistors are identical and thus a further improved match between the two emitted bias currents of the current mirror arrangement is present.

Bei den beiden Leitfähigkeitstypen der Transistoren handelt es sich bevorzugt um einen p-Leitfähigkeitstyp und einen n-Leitfähigkeitstyp. Das bedeutet, dass der erste Transistor bevorzugt ein p-Kanal-Transistor und der zweite Transistor ein dazu komplementärer n-Kanal-Transistor ist.The two conductivity types of the transistors are preferably a p-conductivity type and an n-conductivity type. This means that the first transistor is preferably a p-channel transistor and the second transistor is a complementary n-channel transistor.

Der erste Transistor und der zweite Transistor sind bevorzugt je als Diode verschaltet.The first transistor and the second transistor are preferably each connected as a diode.

In einer vorteilhaften Weiterbildung wird der erste Strom und der zweite Strom jeweils an dem mit der gesteuerten Stromquelle verbundenen Lastanschluss des ersten bzw. zweiten Transistors abgegriffen.In an advantageous development, the first current and the second current are each tapped at the load connection of the first and second transistor connected to the controlled current source.

Mit diesem Abgriffsknoten ist jeweils weiter bevorzugt der Steueranschluss des jeweiligen Transistors zur Bildung einer Diode verbunden.In each case, the control connection of the respective transistor is connected to this tap node to form a diode.

Der gemeinsame Strompfad, der die Serienschaltung von erstem Transistor, gesteuerter Stromquelle und zweitem Transistor umfasst, ist bevorzugt zwischen einen Versorgungspotenzialanschluss und einen Bezugspotenzialanschluss geschaltet.The common current path, which comprises the series connection of the first transistor, controlled current source and second transistor, is preferably connected between a supply potential terminal and a reference potential terminal.

Die gesteuerte Stromquelle selbst ist bevorzugt ebenfalls als Transistor, nämlich als Stromquellentransistor, ausgebildet, dessen gesteuerte Strecke mit den gesteuerten Strecken des ersten und zweiten Transistors eine Serienschaltung bildet.The controlled current source itself is preferably also designed as a transistor, namely as a current source transistor, whose controlled path forms a series circuit with the controlled paths of the first and second transistors.

Die gesteuerte Stromquelle bildet bevorzugt mit einem als Diode verschalteten Transistor den Stromspiegel, wobei der als Diode verschaltete Transistor weiter bevorzugt in einem weiteren Strompfad angeordnet ist, der von einer eingangsseitigen Stromquelle gespeist wird. Die Stromquelle in dem weiteren Strompfad dient dabei als Referenzstromquelle.The controlled current source preferably forms the current mirror with a diode-connected transistor, wherein the diode-connected transistor is further preferably arranged in a further current path which is fed by an input-side current source. The current source in the further current path serves as a reference current source.

Der weitere Strompfad umfasst aus Symmetriegründen weiter bevorzugt eine weitere Diode, die zwischen den eingangsseitigen Transistor des Stromspiegels und Bezugspotenzial- oder Versorgungspotenzialanschluss geschaltet wird.For reasons of symmetry, the further current path further preferably includes a further diode, which is connected between the input-side transistor of the current mirror and the reference potential or supply potential connection.

Anstelle der weiteren Diode im weiteren Strompfad kann in einer alternativen Ausführungsform ein weiterer Transistor vorgesehen sein, der gemeinsam mit dem zweiten Transistor einen Rückkopplungs-Stromspiegel bildet, wobei der zweite Transistor als Diode verschaltet ist. Die beiden Stromspiegel dieser weitergebildeten Stromspiegelanordnung bilden miteinander einen so genannten Wilson-Stromspiegel.Instead of the further diode in the further current path, in an alternative embodiment, a further transistor may be provided, which together with the second transistor forms a feedback current mirror, wherein the second transistor is connected as a diode. The two current mirrors of this further developed current mirror arrangement form together a so-called Wilson current mirror.

Die Stromspiegel-Anordnung ist bevorzugt in integrierter Schaltungsbauweise hergestellt.The current mirror arrangement is preferably produced in integrated circuit construction.

Insbesondere ist die Stromspiegelanordnung bevorzugt in unipolarer Schaltungstechnik integriert, beispielsweise einer Metall-Isolator-Halbleiter-Struktur.In particular, the current mirror arrangement is preferably integrated in unipolar circuit technology, for example a metal-insulator-semiconductor structure.

Die Stromspiegelanordnung ist bevorzugt in komplementärer MOS-Schaltungstechnik aufgebaut.The current mirror arrangement is preferably constructed in complementary MOS circuit technology.

Die vorgeschlagene Stromspiegelanordnung funktioniert alternativ auch in der komplementären Schaltungsvariante, das bedeutet, dass alle MOS-Transistoren vom n-Kanal-Leitfähigkeitstyp durch Bauteile mit p-Kanal ersetzt werden und umgekehrt.Alternatively, the proposed current mirror arrangement also works in the complementary circuit variant, which means that all n-channel conductivity type MOS transistors are replaced by p-channel devices and vice versa.

Die Erfindung wird nachfolgend anhand von mehreren Ausführungsbeispielen in Zusammenhang mit den Figuren näher erläutert.The invention will be explained in more detail with reference to several embodiments in conjunction with the figures.

Es zeigen dabei:

Figur 1
eine Stromspiegelanordnung gemäß Stand der Technik,
Figur 2
eine Stromspiegelanordnung gemäß Stand der Technik mit Kaskode-Stufe,
Figur 3
das Grundprinzip der vorgeschlagenen Stromspiegelanordnung anhand eines Schaltplans,
Figur 4
eine Weiterbildung der Schaltung von Figur 3 anhand eines Schaltplans und
Figur 5
eine Weiterbildung der Schaltung von Figur 3 mit Wilson-Stromspiegel.
It shows:
FIG. 1
a current mirror arrangement according to the prior art,
FIG. 2
a current mirror arrangement according to the prior art with cascode stage,
FIG. 3
the basic principle of the proposed current mirror arrangement based on a circuit diagram,
FIG. 4
a development of the circuit of FIG. 3 based on a circuit diagram and
FIG. 5
a development of the circuit of FIG. 3 with Wilson current mirror.

Figuren 1 und 2 wurden bereits in der Beschreibungseinleitung erläutert. Deren Beschreibung soll daher an dieser Stelle nicht noch einmal wiederholt werden. Figures 1 and 2 were already explained in the introduction to the description. Their description should therefore not be repeated again at this point.

Figur 3 zeigt eine Stromspiegelanordnung gemäß dem vorgeschlagenen Prinzip mit einem ersten Transistor 11, der von einem p-Leitfähigkeitstyp ist, und mit einem zweiten Transistor 12, der von einem n-Leitfähigkeitstyp ist. Der erste und der zweite Transistor 11, 12 haben je einen Steueranschluss und je eine gesteuerte Strecke. Zwischen je einen Anschluss der gesteuerten Strecken der Transistoren 11, 12 ist eine Stromquelle 13 geschaltet. Der freie Anschluss der gesteuerten Strecke des Transistors 11 ist mit einem Versorgungspotenzialanschluss 14 und der freie Anschluss der gesteuerten Strecke des zweiten Transistors 12 mit einem Bezugspotenzialanschluss 15 verschaltet. Die mit der Stromquelle 13 verbundenen Anschlüsse der gesteuerten Strecken der Transistoren 11, 12 sind mit dem jeweiligen Steueranschluss des zugehörigen Transistors 11, 12 zur Bildung einer Diode verbunden und bilden zugleich Ausgänge 16, 17 der Stromspiegelanordnung. Der erste Ausgang 16 ist ausgelegt zur Abgabe eines ersten Stroms PBIAS, während der zweite Ausgang 17 zur Abgabe eines zweiten, zum ersten komplementären Stroms NBIAS ausgelegt ist. Erster und zweiter Strom dienen als komplementäre BIAS-Signale. Gemäß Figur 1 ist die Stromquelle 13 als floatende Stromquelle, also mit schwebendem Potenzial, ausgeführt. FIG. 3 shows a current mirror arrangement according to the proposed principle with a first transistor 11, which is of a p-type conductivity, and with a second transistor 12, which is of an n-type conductivity. The first and the second transistor 11, 12 each have a control terminal and one controlled path each. Between each one terminal of the controlled paths of the transistors 11, 12, a current source 13 is connected. The free connection of the controlled path of the transistor 11 is connected to a supply potential connection 14 and the free connection of the controlled path of the second transistor 12 to a reference potential connection 15. The connected to the current source 13 terminals of the controlled paths of the transistors 11, 12 are connected to the respective control terminal of the associated transistor 11, 12 to form a diode and at the same time form outputs 16, 17 of the current mirror assembly. The first output 16 is designed to deliver a first one Current PBIAS, while the second output 17 is designed to deliver a second, the first complementary current NBIAS. First and second currents serve as complementary BIAS signals. According to FIG. 1 the current source 13 is designed as a floating current source, that is to say with a floating potential.

Zusätzlich zu dem Strompfad 11, 13, 12 ist ein weiterer Strompfad vorgesehen, der dazu ausgelegt ist, von einem Referenzstrom IREF durchflossen zu werden. Zur Kopplung dieser beiden Strompfade ist ein in Figur 3 nicht explizit eingezeichneter Stromspiegel vorgesehen, was dadurch angedeutet ist, dass die gesteuerte Stromquelle 13 von dem n-fachen Referenzstrom IREF des ersten Strompfades durchflossen ist. Der Buchstabe n repräsentiert dabei das Spiegelverhältnis des Stromspiegels.In addition to the current path 11, 13, 12, a further current path is provided, which is designed to be traversed by a reference current I REF . To couple these two current paths is a in FIG. 3 not explicitly drawn current mirror provided, which is indicated by the fact that the controlled current source 13 is traversed by the n-times the reference current I REF of the first current path. The letter n represents the mirror ratio of the current mirror.

Durch die Verschaltung gemäß Figur 3 ist sichergestellt, dass die Ströme in dem p-Kanal-Transistor 11 und in dem n-Kanal-Transistor 12 identisch groß sind und damit auch die von den Transistoren bereitgestellten und an den Ausgängen 16, 17 abgreifbaren, komplementären Bias-Signale PBIAS, NBIAS exakt identisch groß sind. Die vorgeschlagene Schaltung hat dabei einen geringen Bauteilaufwand und ist mit geringer Chipfläche und daher kostengünstig integrierbar.Due to the interconnection according to FIG. 3 it is ensured that the currents in the p-channel transistor 11 and in the n-channel transistor 12 are identical, and thus also provided by the transistors and at the outputs 16, 17 can be tapped, complementary bias signals PBIAS, NBIAS exactly the same size. The proposed circuit has a low component cost and is inexpensive to integrate with a small chip area and therefore.

Eine Weiterbildung der Schaltung von Figur 3 zur Erzeugung identischer n-MOS- und p-MOS-Ströme mittels einer Stromspiegelanordnung zeigt Figur 4. Die Schaltung von Figur 4 stimmt in den verwendeten Bauteilen, deren vorteilhafter Zusammenschaltung und Funktionsweise weitgehend mit derjenigen von Figur 3 überein und wird insoweit an dieser Stelle nicht noch einmal wiederholt.A development of the circuit of FIG. 3 for generating identical n-MOS and p-MOS currents by means of a current mirror arrangement FIG. 4 , The circuit of FIG. 4 agrees in the components used, their advantageous interconnection and operation largely with that of FIG. 3 and will not be repeated at this point.

Die floatend betriebene, gesteuerte Stromquelle 13 ist bei Figur 4 als Transistor 13' ausgebildet, der mit einem Eingangstransistor 18 den Stromspiegel 18, 13' bildet. Der Eingangstransistor 18 ist als Diode verschaltet. Ebenso wie der Transistor 13', der als Stromquelle arbeitet, ist der Transistor 18 vom n-Kanal-Typ. Zur Bereitstellung des Referenzstroms IREF ist eine Stromquelle 19 vorgesehen, die einen Versorgungspotenzialanschluss 14 mit einem Anschluss der gesteuerten Strecke des Diodentransistors 18 verbindet, der auch mit dessen Gate-Anschluss verbunden ist. Eine weitere Transistordiode 20, ebenfalls vom n-Leitfähigkeitstyp, verbindet den Transistor 18 mit dem Bezugspotenzialanschluss 15. Somit bilden die Referenzstromquelle 19, der Transistor 18 und die Diode 20 miteinander eine Serienschaltung.The floating powered controlled current source 13 is at FIG. 4 is formed as a transistor 13 ', which forms the current mirror 18, 13' with an input transistor 18. The input transistor 18 is connected as a diode. As well as the transistor 13 ', which operates as a current source, the transistor 18 is of the n-channel type. To provide the reference current I REF , a current source 19 is provided, which connects a supply potential terminal 14 to a terminal of the controlled path of the diode transistor 18, which is also connected to its gate terminal. Another transistor diode 20, also of the n-conductivity type, connects the transistor 18 to the reference potential terminal 15. Thus, the reference current source 19, the transistor 18 and the diode 20 together form a series circuit.

Man erkennt, dass ausgehend von einer Stromspiegelanordnung mit Kaskode-Stufe, wie in Figur 2 gezeigt, nur geringfügige Modifikationen und keinerlei zusätzliche Bauteile erforderliche sind, um gleichwohl mit Vorteil Bias-Ströme, die exakt miteinander übereinstimmen und zum Betrieb komplementärer Bauteile geeignet sind, gemäß der Schaltung von Figur 4 zu erzeugen.It can be seen that starting from a current mirror arrangement with cascode stage, as in FIG. 2 shown, only minor modifications and no additional components are required to nonetheless advantageously bias currents that match exactly and are suitable for operating complementary components, according to the circuit of FIG. 4 to create.

Figur 5 zeigt ein weiteres Ausführungsbeispiel einer Weiterbildung einer Stromspiegelanordnung gemäß vorgeschlagenem Prinzip. Die Schaltung von Figur 5 stimmt in den verwendeten Bauteilen, deren Verschaltung miteinander sowie ihrer vorteilhaften Funktionsweise weitgehend mit der von Figur 4 überein und wird insoweit an dieser Stelle nicht noch einmal beschrieben. FIG. 5 shows a further embodiment of a development of a current mirror arrangement according to the proposed principle. The circuit of FIG. 5 agrees in the components used, their interconnection with each other and their advantageous operation largely with that of FIG. 4 and will not be described again at this point.

Anstelle des als Diode verschalteten Transistors 20 ist bei Figur 5 der Steueranschluss des dort mit Bezugszeichen 20' versehenen Transistors mit dem Gate-Anschluss des zweiten Transistors 12 verbunden. Dadurch bilden die Transistoren 12, 20' miteinander einen Feedback-Stromspiegel, der zusammen mit dem Stromspiegel 18, 13', der in Vorwärtsrichtung arbeitet, einen Wilson-Stromspiegel bildet. Der Wilson-Stromspiegel 18, 13'; 12, 20' bildet einen geschlossenen Regelkreis.Instead of the diode-connected transistor 20 is at FIG. 5 the control terminal of there with reference numeral 20 ' provided transistor connected to the gate terminal of the second transistor 12. As a result, the transistors 12, 20 'together form a feedback current mirror, which together with the current mirror 18, 13', which operates in the forward direction, forms a Wilson current mirror. The Wilson current mirror 18, 13 '; 12, 20 'forms a closed loop.

Auch für das Ausführungsbeispiel gemäß Figur 5 gilt, dass die an den Ausgängen 16, 17 abgreifbaren Bias-Signale PBIAS, NBIAS exakt miteinander übereinstimmen.Also for the embodiment according to FIG. 5 It is true that the bias signals PBIAS, NBIAS which can be tapped off at the outputs 16, 17 exactly match one another.

Im Rahmen der Erfindung können alle gezeigten Ausführungsbeispiele auch in komplementärer Ausführung realisiert sein, das bedeutet, dass alle Transistoren vom n-Leitfähigkeitstyp durch p-MOS-Bauteile und umgekehrt ersetzt werden.In the context of the invention, all embodiments shown can also be realized in complementary execution, which means that all transistors of the n-conductivity type are replaced by p-MOS components and vice versa.

Selbstverständlich dienen die gezeigten Ausführungsbeispiele nicht zur Beschränkung der Erfindung, sondern lediglich zu illustrativen Zwecken.Of course, the embodiments shown are not intended to limit the invention, but only for illustrative purposes.

BezugszeichenlisteLIST OF REFERENCE NUMBERS

11
BezugspotenzialanschlussReference potential terminal
22
Transistortransistor
33
Transistortransistor
44
Stromquellepower source
55
VersorgungspotenzialanschlussSupply potential terminal
66
Transistortransistor
77
Ausgangoutput
88th
Ausgangoutput
99
Diodediode
1010
Transistortransistor
1111
Transistortransistor
1212
Transistortransistor
1313
gesteuerte Stromquellecontrolled power source
13'13 '
Transistortransistor
1414
VersorgungspotenzialanschlussSupply potential terminal
1515
BezugspotenzialanschlussReference potential terminal
1616
Ausgangoutput
1717
Ausgangoutput
1818
Diodediode
1919
ReferenzstromquelleReference current source
20'20 '
Transistortransistor

Claims (10)

  1. A current mirror assembly, comprising
    - a first transistor (11) of a first conductivity type and designed to deliver a first current (PBIAS),
    - a second transistor (12) of a second conductivity type and designed to deliver a second current (NBIAS),
    - a controlled current source (13) which is connected between the first transistor (11) and the second transistor (12) and forms the output of a current mirror,
    - a transistor (18) of the current mirror (18, 13'), the transistor (18) being interconnected as a diode and being arranged together with a reference current source (19) in a further current path,
    - and wherein the further current path (19, 18) comprises a transistor (20') forming a feedback current mirror (12, 20') together with the second transistor (12), the second transistor (12) being interconnected as a diode.
  2. The current mirror assembly according to claim 1,
    characterized in that
    the controlled current source (13) is designed to be operated with floating potential.
  3. The current mirror assembly according to claim 1 or 2,
    characterized in that
    the first transistor (11), the controlled current source (13) and the second transistor (12) are arranged in a common current path which is connected between a supply terminal and a reference potential terminal (14, 15).
  4. The current mirror assembly according to any of the claims 1 to 3,
    characterized in that
    the first conductivity type and the second conductivity type are complementary to each other.
  5. The current mirror assembly according to any of the claims 1 to 4,
    characterized in that
    the first transistor (11) and the second transistor (12) are each interconnected as a diode.
  6. The current mirror assembly according to any of the claims 1 to 5,
    characterized in that
    the first transistor (11) comprises a control terminal which is coupled to a terminal of the controlled section of the first transistor (11) as well as to a terminal of the controlled current source (13) and is provided with an output (16) for delivering the first current (PBIAS), and in that the second transistor (12) comprises a control terminal which is coupled to a terminal of the controlled section of the second transistor (12) as well as to a further terminal of the controlled current source (13) and is provided with an output (17) for delivering the second current (NBIAS).
  7. The current mirror assembly according to any of the claims 1 to 6,
    characterized in that
    the controlled current source is a current source transistor (13') whose controlled section forms a serial connection with the controlled sections of the first and second transistors (11, 12).
  8. The current mirror assembly according to any of the claims 1 to 7,
    characterized in that
    the controlled current source (13') forms the current mirror together with a transistor (18) interconnected as a diode.
  9. The current mirror assembly according to any of the claims 1 to 8,
    characterized in that
    the current mirror assembly is manufactured in integrated circuit design.
  10. The current mirror assembly according to any of the claims 1 to 9,
    characterized in that
    the current mirror assembly is integrated in complementarymetal-oxide-semiconductor circuit technology.
EP10184332.4A 2004-04-30 2005-04-15 Current mirror system Not-in-force EP2282249B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004021232A DE102004021232A1 (en) 2004-04-30 2004-04-30 Current mirror arrangement
EP05742902A EP1741016B1 (en) 2004-04-30 2005-04-15 Current balance arrangement

Related Parent Applications (3)

Application Number Title Priority Date Filing Date
EP05742902.9 Division 2005-04-15
EP05742902A Division EP1741016B1 (en) 2004-04-30 2005-04-15 Current balance arrangement
EP05742902A Division-Into EP1741016B1 (en) 2004-04-30 2005-04-15 Current balance arrangement

Publications (2)

Publication Number Publication Date
EP2282249A1 EP2282249A1 (en) 2011-02-09
EP2282249B1 true EP2282249B1 (en) 2015-10-07

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EP05742902A Expired - Fee Related EP1741016B1 (en) 2004-04-30 2005-04-15 Current balance arrangement

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EP (2) EP2282249B1 (en)
JP (1) JP2007535744A (en)
DE (1) DE102004021232A1 (en)
WO (1) WO2005109144A1 (en)

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US8680840B2 (en) * 2010-02-11 2014-03-25 Semiconductor Components Industries, Llc Circuits and methods of producing a reference current or voltage
JP5500108B2 (en) * 2011-03-16 2014-05-21 富士通セミコンダクター株式会社 Current mirror circuit and amplifier circuit having the same
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CN209248374U (en) * 2018-12-05 2019-08-13 北京矽成半导体有限公司 The fixed delay circuit not influenced by temperature voltage

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JP2007535744A (en) 2007-12-06
WO2005109144A1 (en) 2005-11-17
EP1741016B1 (en) 2012-09-19
DE102004021232A1 (en) 2005-11-17
US7872463B2 (en) 2011-01-18
EP2282249A1 (en) 2011-02-09
EP1741016A1 (en) 2007-01-10
US20080018320A1 (en) 2008-01-24

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