EP2074623A4 - MODULAR CONTROL STRUCTURE FOR A MEMORY AND A MEMORY SYSTEM - Google Patents

MODULAR CONTROL STRUCTURE FOR A MEMORY AND A MEMORY SYSTEM

Info

Publication number
EP2074623A4
EP2074623A4 EP07800456A EP07800456A EP2074623A4 EP 2074623 A4 EP2074623 A4 EP 2074623A4 EP 07800456 A EP07800456 A EP 07800456A EP 07800456 A EP07800456 A EP 07800456A EP 2074623 A4 EP2074623 A4 EP 2074623A4
Authority
EP
European Patent Office
Prior art keywords
memory
command structure
modular command
memory system
modular
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07800456A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP2074623A1 (en
Inventor
Jin-Ki Kim
Hakjune Oh
Hong Beom Pyeon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Priority to EP12158821A priority Critical patent/EP2487794A3/en
Publication of EP2074623A1 publication Critical patent/EP2074623A1/en
Publication of EP2074623A4 publication Critical patent/EP2074623A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
EP07800456A 2006-08-22 2007-08-20 MODULAR CONTROL STRUCTURE FOR A MEMORY AND A MEMORY SYSTEM Withdrawn EP2074623A4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP12158821A EP2487794A3 (en) 2006-08-22 2007-08-20 Modular command structure for memory and memory system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US83932906P 2006-08-22 2006-08-22
US90200307P 2007-02-16 2007-02-16
US89270507P 2007-03-02 2007-03-02
PCT/CA2007/001428 WO2008022434A1 (en) 2006-08-22 2007-08-20 Modular command structure for memory and memory system

Publications (2)

Publication Number Publication Date
EP2074623A1 EP2074623A1 (en) 2009-07-01
EP2074623A4 true EP2074623A4 (en) 2010-01-06

Family

ID=39106428

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07800456A Withdrawn EP2074623A4 (en) 2006-08-22 2007-08-20 MODULAR CONTROL STRUCTURE FOR A MEMORY AND A MEMORY SYSTEM

Country Status (5)

Country Link
EP (1) EP2074623A4 (ko)
JP (1) JP2010501915A (ko)
KR (2) KR101397229B1 (ko)
TW (1) TW200826104A (ko)
WO (1) WO2008022434A1 (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7904639B2 (en) 2006-08-22 2011-03-08 Mosaid Technologies Incorporated Modular command structure for memory and memory system
US20080201588A1 (en) 2007-02-16 2008-08-21 Mosaid Technologies Incorporated Semiconductor device and method for reducing power consumption in a system having interconnected devices
US7957173B2 (en) * 2008-10-14 2011-06-07 Mosaid Technologies Incorporated Composite memory having a bridging device for connecting discrete memory devices to a system
US8194481B2 (en) 2008-12-18 2012-06-05 Mosaid Technologies Incorporated Semiconductor device with main memory unit and auxiliary memory unit requiring preset operation
US8037235B2 (en) 2008-12-18 2011-10-11 Mosaid Technologies Incorporated Device and method for transferring data to a non-volatile memory device
CN102257568B (zh) 2008-12-18 2013-09-18 莫塞德技术公司 具有主存储单元和需要预设操作的辅存储单元的半导体设备
US20110258366A1 (en) * 2010-04-19 2011-10-20 Mosaid Technologies Incorporated Status indication in a system having a plurality of memory devices
TWI477966B (zh) * 2012-05-31 2015-03-21 Silicon Motion Inc 資料儲存裝置與快閃記憶體操作方法
JP6541998B2 (ja) * 2015-03-24 2019-07-10 東芝メモリ株式会社 メモリデバイス、半導体装置および情報処理装置
KR102514388B1 (ko) 2016-03-25 2023-03-28 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
KR102651425B1 (ko) 2016-06-30 2024-03-28 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
JP7458740B2 (ja) 2019-10-21 2024-04-01 キオクシア株式会社 メモリシステム及び制御方法
US11822793B2 (en) * 2022-04-04 2023-11-21 Western Digital Technologies, Inc. Complete and fast protection against CID conflict

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040148482A1 (en) * 2003-01-13 2004-07-29 Grundy Kevin P. Memory chain
US20040256638A1 (en) * 2000-01-05 2004-12-23 Richard Perego Configurable width buffered module having a bypass circuit
US20050120163A1 (en) * 2003-12-02 2005-06-02 Super Talent Electronics Inc. Serial Interface to Flash-Memory Chip Using PCI-Express-Like Packets and Packed Data for Partial-Page Writes
US20050120157A1 (en) * 2003-12-02 2005-06-02 Super Talent Electronics Inc. USB Smart Switch with Packet Re-Ordering for Interleaving among Multiple Flash-Memory Endpoints Aggregated as a Single Virtual USB Endpoint
US20060031593A1 (en) * 2004-08-09 2006-02-09 Sinclair Alan W Ring bus structure and its use in flash memory systems

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729683A (en) * 1995-05-18 1998-03-17 Compaq Computer Corporation Programming memory devices through the parallel port of a computer system
US6453365B1 (en) * 1998-02-11 2002-09-17 Globespanvirata, Inc. Direct memory access controller having decode circuit for compact instruction format
JP3973337B2 (ja) * 2000-02-08 2007-09-12 株式会社日立製作所 記憶素子及びそれを用いた記憶装置
US20020161941A1 (en) * 2001-04-30 2002-10-31 Sony Corporation And Electronics, Inc System and method for efficiently performing a data transfer operation
DE102005015828A1 (de) * 2004-06-11 2006-01-05 Samsung Electronics Co., Ltd., Suwon Hub, Speichermodul, Speichersystem, sowie dazugehörige Schreib- und Leseverfahren

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040256638A1 (en) * 2000-01-05 2004-12-23 Richard Perego Configurable width buffered module having a bypass circuit
US20040148482A1 (en) * 2003-01-13 2004-07-29 Grundy Kevin P. Memory chain
US20050120163A1 (en) * 2003-12-02 2005-06-02 Super Talent Electronics Inc. Serial Interface to Flash-Memory Chip Using PCI-Express-Like Packets and Packed Data for Partial-Page Writes
US20050120157A1 (en) * 2003-12-02 2005-06-02 Super Talent Electronics Inc. USB Smart Switch with Packet Re-Ordering for Interleaving among Multiple Flash-Memory Endpoints Aggregated as a Single Virtual USB Endpoint
US20060031593A1 (en) * 2004-08-09 2006-02-09 Sinclair Alan W Ring bus structure and its use in flash memory systems

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2008022434A1 *

Also Published As

Publication number Publication date
JP2010501915A (ja) 2010-01-21
TW200826104A (en) 2008-06-16
KR101397229B1 (ko) 2014-05-20
KR20130136004A (ko) 2013-12-11
KR20090046944A (ko) 2009-05-11
KR101514171B1 (ko) 2015-04-21
WO2008022434A1 (en) 2008-02-28
EP2074623A1 (en) 2009-07-01

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Effective date: 20091204

RIC1 Information provided on ipc code assigned before grant

Ipc: G11C 7/20 20060101ALI20091130BHEP

Ipc: G06F 13/42 20060101ALI20091130BHEP

Ipc: G11C 7/10 20060101AFI20091130BHEP

17Q First examination report despatched

Effective date: 20100309

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: MOSAID TECHNOLOGIES INCORPORATED

DAX Request for extension of the european patent (deleted)
RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

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