Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
  • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
  • H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
  • H04N3/15—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation
  • H04N3/155—Control of the image-sensor operation, e.g. image processing within the image-sensor
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
  • H04N25/768—Addressed sensors, e.g. MOS or CMOS sensors for time delay and integration [TDI]
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/50—Control of the SSIS exposure
  • H04N25/57—Control of the dynamic range
  • H04N25/58—Control of the dynamic range involving two or more exposures
  • H04N25/581—Control of the dynamic range involving two or more exposures acquired simultaneously
  • H04N25/583—Control of the dynamic range involving two or more exposures acquired simultaneously with different integration times
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
  • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

• the invention relates to linear image sensors with scrolling and signal integration (or TDI sensors, in English: “Time Delay Integration Linear Sensors”), in which an image of a line of points of a scene observed is reconstructed by adding successive images taken by several photosensitive lines successively observing the same line of the scene as the scene scrolls past the sensor.
• TDI sensors in English: “Time Delay Integration Linear Sensors”
• These sensors are used for example in scanners. They comprise a bar of several parallel lines of photosensitive pixels; the sequencing of the control circuits of the different lines (control of exposure time and then reading of the photogenerated charges) is synchronized with respect to the relative scrolling of the scene and the sensor, so that all the lines of the sensor see a single line of the observed scene. The signals generated by each line are then added point by point for each point of the observed line. The signal-to-noise ratio is improved in the ratio of the square root of the number N of lines of the sensor. This number N can be, for example, 16 or 32 for industrial control applications or earth observation applications from space, or even from 60 to 100 lines for medical applications (dental, mammography, etc.). .).
• CCDs charge-coupled image sensors
• the addition of point-to-point signals was accomplished simply by emptying in a line of pixels the charges generated and accumulated in the previous pixel line, in synchronism with the displacement. relative of the scene and the sensor.
• the last row of pixels, having accumulated N times the charges generated by the line observed, could then be transferred to an output register and converted, during a reading phase, into voltage or electric current.
• CMOS sensors active pixel sensors with transistors
• CMOS complementary-metal-oxide-semiconductor
• the active pixels of image sensors in CMOS technology most often comprise two isolated locations from one another, in which the photogenerated charges can be momentarily stored; these locations are on the one hand the photodiode in which charges are generated under the effect of light, and on the other hand an intermediate storage node which receives the charges of the photodiode at the end of an integration period charge and which is then used to produce an output voltage of the pixel; the output voltage of the pixel is related to the amount of charge present on the storage node.
• This decomposition of the pixel into two different charge storage locations is normally related to the need to read line by line the signals of the different pixels of a matrix of N lines, this reading being generally made from the storage nodes during a period of time. new integration of charges in the photodiodes.
• This type of structure is used here in a very different way, in a context of TDI sensors where one will not read line by line but only a reading of the sum of N lines having observed the same image line.
• a method of image capture, with scrolling and signal integration is therefore proposed for synchronously reading the same image line successively by N lines of P photosensitive pixels and the summation.
• pixel to pixel signals from the reading of the different lines during successive integration periods, in correspondence with the scrolling of the linear image in front of the N rows of pixels, a pixel being constituted by a circuit MOS transistor comprising at minus a photodiode, a charge storage node, and a charge-voltage conversion circuit for applying to a pixel output a voltage representing the amount of charges stored in the storage node, characterized in that, at the beginning of a photogenerated charge integration time, the output voltage of a pixel of a preceding line is applied to the photodiode of the pixel of an intermediate line of rank i, the photodiode is isolated, and charges are integrated therein. light, and finally, at the end of the integration time, the charges of the photodiode are transferred into the storage node.
• the charge discharged into the storage node will be practically the sum of the charges purely due to the illumination of the photodiode and of an initial charge which has been formed from the charge stored in the storage node of the pixel of the previous line; this last charge is itself an accumulation of photogenerated charges and an initial charge from a still previous line, and so on.
• the charge discharged into the storage node of a pixel of the last line will be equivalent to an accumulation of photogenerated charges in the N lines which observed the same image line. It is this last charge that will be converted into voltage to provide an electrical representation of the image line observed successively by the N lines.
• the load of the storage node is reset to a fixed value before the charges of the photodiode are transferred to this storage node.
• the circuit which converts the storage node loads into voltage may comprise a first follower transistor whose gate is connected to the storage node and whose source is connected to a current source; resetting the load of the storage node is performed by connecting the node to a reference voltage (Vref) whose value is preferably equal to the sum of the gate-source voltage drop of the first follower transistor and the voltage ( said "pedestal voltage") appearing across the photodiode when the latter is empty of charges and isolated.
• Vref reference voltage
• the method comprises a step of connecting the diode to a supply potential (Vdd) before the application to the photodiode of the output voltage of the pixel of the preceding line, for connecting the photodiode to the potential of this power supply during a fraction of the charge integrating period T and preventing during this fraction the integration of charges into the photodiode.
• Vdd supply potential
• the invention proposes a linear image sensor, scrolling and integration, allowing the synchronized reading of the same linear image successively by N lines of P photosensitive pixels and pixel-to-pixel summation signals from the reading of the different lines, during successive integration periods, in correspondence with the scrolling of the linear image in front of the N rows of pixels, a pixel consisting of a MOS transistor circuit comprising at least one photodiode , a charge storage node, a switch for transferring charge from the photodiode to the storage node at the end of an integration period, a switch for resetting the load of the storage node before this transfer, and a circuit charge-voltage conversion device for applying to a pixel output a voltage representing the charge stored on the storage node, characterized in that a pixel el of rank j in an intermediate rank line i its output connected to an input of the rank pixel j of the next higher rank line i + 1, and has an input connected to an output of the
• the pixel may include an exposure time adjusting transistor, connected between the photodiode and a supply voltage (Vdd) for connecting the photodiode to the potential of this power supply for a fraction of the charge integration period and preventing this fraction the integration of charges in the photodiode.
• Vdd supply voltage
• FIG. 1 represents a general diagram of TDI sensor enabling operation according to the method of FIG. the invention
• FIG. 2 represents the constitution of an active pixel that can be used to implement the invention
• FIG. 3 represents a control signal diagram of the sensor using the pixel of FIG. 2.
• This linear image sensor with scrolling and integration or TDI sensor comprises N lines of P pixels, the pixel of rank j of an intermediate line of rank i being designated by PiJ; i is an integer index ranging from 1 to N and j is an integer index ranging from 1 to P.
• the pixels are active pixels each having a few MOS transistors controlled by control signals.
• the control signals are global (control of all pixels at a time); it should be noted that it is not necessary in principle to provide control signals assigned to a single line at a time as is generally the case in CMOS matrix sensors with N lines of P pixels.
• the principle of the active pixel with MOS transistors that will be used in this TDI sensor is generally as follows: during an integration time, all the pixels integrate into a photodiode (which, in a conventional matrix, would be previously emptied of its charges but which according to the invention is filled with an initial charge) the charges that are produced by the light; then the charge of the photodiode is discharged into a charge storage node of the pixel which has been reset before this spill; then, the storage node load is converted to current or in voltage and applied to an output conductor, usually by a voltage follower transistor.
• the output conductor is a column driver common to all the pixels in the same column and the pixels are read line by line so that the column conductors receive the voltage generated by the nodes of the column. storing a single pixel line; this reading is done during a new load integration time in the photodiodes which are then isolated from the storage nodes.
• the output voltage of a pixel P (M) J of rank j of the rank row i-1 representing the charge accumulated on the storage node of this pixel at the end of a first integration period, is applied to the pixel PiJ of rank j of the line of rank i for the second integration period. More precisely, this output voltage of the pixel P (M) J is applied to the photodiode of the pixel of the line of rank i at the beginning of the integration time of the second period and it causes the initialization in the photodiode of a amount of initial charges proportional to this voltage.
• the photodiode will therefore, during the integration time, accumulate a charge which is the sum of this initial charge and a new photogenerated charge. At the end of the second integration period, it is this sum that will serve to generate an output voltage for the pixel of the line of rank i; the latter is used during the third integration period to define the initial charge of the photodiode pixel P (i + i) j of the next line. And so on.
• the integration periods are synchronized with the scrolling of the image, so that the line of rank i integrates, during an integration period, photogenerated charges by the same line of scene that has been observed by the row of rank i-1 during the previous integration period. In other words, during the duration T of a charge integration period, the relative displacement of the projected image on the sensor is equal to the pitch of the pixel lines.
• the last row of pixels will finally receive on the charge storage node of each pixel a quantity of charges which will be the result of an accumulation of charges generated by all the rows of pixels while they observed the same line of picture.
• this accumulation is not necessarily the exact sum of the charges of each line, this for reasons tending notably to non-unitary gains during the transfers or conversions charge-tension; but the result of this accumulation is very close to that of the sensors scrolling and integration of loads and it provides the same advantages, namely a significant improvement in the signal / noise ratio; the improvement is practically in a ratio equal to the square root of the number of lines N.
• a sequencer SEQ manages the succession of control signals of the pixels.
• An RS output register (which may be a multiplexer) receives the output voltages of the last row of pixels (of rank N) and supplies on an OUT output the analog voltages coming from this last line, or else digital voltages if the register comprises one or more analog-digital converters.
• FIG. 2 represents the implementation of the invention in the case where the structure of the pixel is inspired by five-transistor pixels of known type used in CMOS matrices.
• the modified pixel according to the invention comprises six MOS transistors T1 to T6 and a photodiode PD.
• the photodiode PD is connected in series with the transistor T1 between a ground and a supply voltage Vdd.
• the transistor T1 can be made conductive, for resetting the charges of the photodiode, by a general resetting signal GSH acting simultaneously on all the pixels of the array before the start of an integration time.
• the global control GSH makes it possible to adjust the exposure time Te within the charge integration period T since the photodiode can not integrate charges as long as the transistor T1 is conducting.
• This transistor T1 is optional if one does not wish to adjust the exposure time. It can also serve as an anti-dazzle drain.
• the node N1 connecting the photodiode and the transistor T1 accumulates charges during the integration time.
• This node N1 can be connected briefly to a charge storage node N2 by the transistor T2, at the end of an integration time, by a transfer control signal GTRA acting simultaneously on all the pixels of the matrix.
• the storage node N2 can be reset to a reference potential Vref (reset of the charges of the node N2) by the transistor T3 which receives a brief control signal LRES common to all the pixels.
• the LRES signal is transmitted at the end of each integration time, before the transmission of the GTRA signal.
• the node N2 is also connected to a charge-voltage conversion circuit comprising in this example two transistors T4, T5. More precisely, the node N2 is connected to the gate of the follower transistor T4 whose drain is at the potential Vdd and whose source copies (to a source gate voltage drop near) the potential taken by the gate, that is to say say the potential of the N2 storage node.
• the source of the transistor T4 is connected to an output Si of the pixel PiJ and it is this output which will be connected to the input (Ei + 1) of the pixel of rank j of the next line.
• a transistor T5 having its gate connected to a fixed potential Vgc common to all the pixels of the N lines, constitutes a current source connected between the source of T4 and ground so that the transistor T4 operates as a follower.
• the set of T4 and T5 forms a voltage follower circuit establishing on the source of T4 a voltage which copies, at the gate-source voltage (Vgs) near the transistor T4, the voltage present on the storage node.
• a capacitance Cs has been represented, connected between the node N2 and the mass; it may consist of armatures intentionally constructed in the form of capacitance, or by parasitic capacitances present between the node N2 and the mass. It is this which allows node N2 to act as a charge storage node.
• this signal is a reset signal of the charges of the storage node N2 and is transmitted at any time during the integration period, provided that it is posterior to the signal TL and earlier than the beginning of the GTRA signal which will follow and whose end marks the end of the load integration time;
• a short transfer signal GTRA which turns transistor T2 (for all pixels) and transfers to node N2 the charge stored in the photodiode, which is then the sum of the initial charge and the photogenerated charge during the integration time; by transferring the charge from the photodiode to the storage node, it is meant a distribution of the charges between the nodes N1 and N2 in proportion to the respective capacities of these two nodes, but in all cases the transferred charge on node N2 is proportional to the charge of the photodiode, always with the same coefficient of proportionality;
• a new signal GSH can be transmitted.
• the pixels of the first line are distinguished from the others in that their input Ei (drain of the transistor T6 controlled by the signal TL) is not connected to the output of a preceding pixel but is connected to a fixed potential for completely emptying the charges of the photodiode before the beginning of an integration time Te.
• Ei drain of the transistor T6 controlled by the signal TL
• Te fixed potential for completely emptying the charges of the photodiode before the beginning of an integration time Te.
• the sensor At the second integration time, the sensor having moved a line of pixels, it is the second pixel line that will receive the photogenerated charges by the same first image line. But the signal TL applied to the pixels of this second line causes the application to the photodiode of the voltage present at this time on the output of the pixel of the first line, that is to say a voltage resulting from the conversion charge- voltage of the quantity of charges present on the storage node N2.
• the pixels of the second line take at the beginning of the second integration time an initial charge dictated by the result of integration in the first line and add, during the second integration time, photogenerated charges in their photodiodes.
• the charge present in the photodiode is a sum of photogenerated charges by the first two lines over two integration times.
• the potential taken by a photodiode of the N I ⁇ m ⁇ line at the beginning of the integration time represents the equivalent of the presence of a charge accumulated on N-1 integration time. by the first N-1 lines of the sensor; and at the end of the N I ⁇ m ⁇ integration time, the charge present in the photodiode (and then in the storage node N2) of the last line represents the equivalent of the load accumulated on N integration time by the N lines of the sensor which have all observed the same image line.
• the voltage corresponding to this accumulation is reported by the follower transistor T4 of the last line to the output register where it can be extracted, or first converted into digital words and then extracted.
• the input of the pixels of the first line is connected to a fixed voltage.
• This fixed voltage may be a supply voltage Vdd, but for the symmetry of operation, it is preferable that it be generated by a circuit such as that of transistors T3, T4 and T5: a reference voltage Vref (the same as previously) is applied by a first transistor (equivalent of T3) to the gate of a follower transistor (equivalent of T4) charged by a current source (equivalent to T5).
• Vref the same as previously
• the initial voltage taken by the photodiodes of the first line is the same as the initial voltage that would take the photodiodes of any line in the total absence of illumination.
• Vref the reference voltage which is used to reset the potential of the storage node N2 is chosen in a particular way: if Vgs is called the gate-source voltage drop of the transistor T4 connected to the current source T5, then it is preferable that Vref is chosen equal to Vpdi + Vgs, Vpdi being the pedestal voltage (mentioned above) of the photodiode PD.
• This pedestal voltage which is the voltage across the empty photodiode charges, depends on the technology and can be for example of the order of 1 to 2 volts.
• the transfer efficiency or the conversion gain is not necessarily unitary, so that the progressive accumulation of charges in a node
• the storage of the N I ⁇ m ⁇ line is not exactly the sum of the photogenerated charges in the N lines.
• the ratio between the capacitance value Cd of the photodiode which accumulates the charges and the value of Cm capacity of the storage node also intervenes (in the ratio of these capabilities) to define the ratio between the transferred loads and the voltage taken by the storage node.
• the gain of the stage between the charge present in the photodiode of a stage at the end of an integration time and the equivalent charge applied to the photodiode of the following line at the beginning of the next integration time is of the form
• G Gt.Cd/Cm where Gt is the gain of the follower circuit.
• this gain G be as close as possible to 1 to perform the equivalent of an accumulation of charges on N lines.
• the invention has been described with respect to a six-transistor pixel structure (including current source transistor T5). But it can be used for example also with a five-transistor pixel, the transistor T1 exposure time setting being purely and simply deleted.

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• 2006
  • 2006-09-19 FR FR0608188A patent/FR2906081B1/fr not_active Expired - Fee Related
• 2007
  • 2007-08-17 JP JP2009527764A patent/JP2010504009A/ja active Pending
  • 2007-08-17 WO PCT/EP2007/058549 patent/WO2008034677A1/fr active Application Filing
  • 2007-08-17 US US12/440,681 patent/US20090268065A1/en not_active Abandoned
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