EP2040965A1

EP2040965A1 - Method for synchronizing components of a motor vehicle brake system, and electronic brake control system

Info

Publication number: EP2040965A1
Application number: EP07765198A
Authority: EP
Inventors: Markus BLÄSER
Original assignee: Lucas Automotive GmbH
Current assignee: ZF Active Safety GmbH
Priority date: 2006-07-14
Filing date: 2007-07-13
Publication date: 2009-04-01
Also published as: US20090292434A1; DE102006032726B4; WO2008006613A1; DE102006032726A1

Abstract

The invention relates to a method for synchronizing components of a motor vehicle brake system, having an electronic main control device (12) with a main timer (22) which is assigned thereto, at least one sub-control device (14, 16), which is subordinate to the main control device (12), with a timer (24, 26) which is assigned thereto, wherein the main control device (12) communicates with the at least one sub-control device (14, 16) in cycles, wherein the main control device (12) and the at least one sub-control device (14, 16) additionally increment in each case one cycle counter which is assigned thereto. It is provided here that the main control device (12) sends synchronizing data to the at least one sub-control device (14, 16), which data comprises a value of the cycle counter of the main control device (12), and that the at least one sub-control device (14, 16) receives said synchronizing data and sets its cycle counter to the received value of the cycle counter of the main control device (12) if the received value of the cycle counter of the main control device (12) differs from the value of the cycle counter of the sub-control device (14, 16).

Description

Method for synchronizing components of a motor vehicle brake system and electronic brake control system

The invention relates to a method for synchronizing components of a motor vehicle brake system having a main electronic control device with a main timer associated therewith, at least one subordinate control device having a timer associated therewith, the main control device communicating with the at least one sub-control device cyclically, and further wherein the lo Main control device and the at least one sub-control device each count up a cycle counter associated therewith.

In modern vehicle systems, especially in brake systems, increasingly important control functions are taken over by electronic devices i5. In this case, various electronic components, such as sensors for detecting vehicle parameters, and actuators and actuators together. These interacting components are each provided with timers, most of which are quartz-based. This makes the components in the purchase relatively expensive. Further

As a result of different operating frequencies of the interacting electronic components, undesirable delays in the control of brake system-bound driver assistance systems can occur. This too is undesirable since driver assistance systems should intervene in vehicle operation as far as possible without delay after detection of relevant vehicle parameters.

> 5

There is therefore a need for a method for synchronizing electronic components of a motor vehicle brake system and for an electronic brake control system, which works reliably while avoiding the disadvantages described above and allows the use of low-cost components. so

For this purpose, the method mentioned above is provided, wherein the main controller sends synchronization data to the at least one sub-controller comprising a value of the cycle counter of the main controller, and the at least one sub-controller i5 receives this synchronization data and sets its cycle counter to the received value of the cycle counter of the main controller , provided that the received value of the cycle counter of the main controller of the value of the cycle counter of the sub-controller is different. Thus, with little effort and low data throughput, synchronization of the main control device and the at least one sub-control device can be achieved.

5

As a result of this synchronization, the at least one sub-control device can be adjusted to the main control device with respect to its operating cycle, so that delays in response of the vehicle braking system, for example within the framework of activation of a driving assistance program, can be largely minimized.

In a development of the invention, it can be provided that in the case in which the received value of the cycle counter of the main control device differs from the value of the cycle counter of the at least one sub-control device i5, the at least one sub-control device generates, stores and / or sends an error signal Main controller sends. From this error signal, the main control device can derive or recognize whether a further fault diagnosis must be carried out with regard to the functioning of the sub-control device, and initiate this if necessary.

20

In a variant of the invention, it is provided that a clock of the timer associated with the at least one sub-control device can be set. As a result, if necessary, the timer of the sub-control device can be re-synchronized with respect to the timer of the main control device.

> 5 In particular, it may be provided in this context that the

Main control device at regular time intervals of predetermined length sends control signals to the at least one sub-control device and that the at least one sub-control device detects the time interval between successive control signals and the associated timer lo resynchronizes in accordance with the detected time interval when the detected time interval from the time interval of predetermined length. It is advantageous if the at least one sub-control device reduces the clock of its associated timer when the detected time interval is greater than the time interval of predetermined length; On the other hand, if the detected time interval is smaller than the time interval of predetermined length, the at least one sub-controller increases the clock of its associated timer. Such a procedure allows for additional fine synchronization, with regard to a very time-sensitive interaction of electronic components there is an increased need for a more accurate synchronization, which can not satisfy the method described above alone.

In a preferred embodiment according to the invention, the main control device and the at least one sub-control device communicate with one another via a bus system. This bus system is preferably an LJN bus system (LIN = Local Interconnect Network) or a bus system based on a LIN bus. Such a bus system is widely used in vehicle technology and can be used inexpensively. In particular, when using a bus system, it may be provided that the main control device allocates access rights to the bus to the at least one sub-control device. This provides control over communication with the main controller and communication between the components can be performed under controlled and well-defined conditions.

In an advantageous embodiment of the invention, the main control device can send data to the at least one sub-control device, wherein the data contain an identifier, which is the one

20 sub-control unit has been identified, to which the main controller has assigned write access rights and / or read access rights on the bus. As a result, the relevant sub-control device is informed of its access right status and can locally control access to the bus. In particular, it can be provided that the main control device at each time only one sub-control device

25 assigns write access rights to the bus. This will cause collisions

Write access as well as data loss and delays while writing to the bus are avoided.

Preferably, the main controller allocates read access rights to the bus of a plurality of the at least one jo sub-controller and the main controller. This allows efficient use of the bus bandwidth and allows a plurality of controllers to read information from the bus.

In a preferred embodiment, the inventive synchronization method is applied to an electronic control system having at least two sub-controllers. In certain applications in automotive engineering, for example in EPB systems (Electronic Park Brake System), it is desirable that two sub-controllers are provided for driving rear-wheel brake actuators, namely, for each rear wheel, a separate sub-controller for driving each of the rear-wheel associated Parkbremsaktuators. In this case, according to the invention, the main control device can be designed such that it sends synchronization data to a first of the sub-control devices at an even value of its cycle counter and synchronization data to a second one of the sub-control devices at an odd value of its cycle counter. This results in a uniform distribution of the communication cycles.

Preferably, the main timer of the main controller comprises a quartz crystal. Such crystals are known for their high accuracy and reliability and are therefore well suited as a basic timing for synchronization. For the timers associated with the at least one sub-controller, it may be provided that this comprises an RC circuit. Such RC circuits are inexpensive to buy and their clock can be adjusted easily during operation. Furthermore, it can be provided that the at least one sub-control device is designed as a sensor with a microcontroller, for example as a yaw rate sensor.

As already indicated above, it is also possible for the at least one sub-control device to be assigned to an actuator which is used, for example, in an EPB system.

As the main control means in the invention, for example, an ECU (Electronic Control Unit) can be used, which is designed so that it runs the software for an EPB monitoring and control system.

In a preferred development of the invention, it can be provided that the main control device can send an error request to the at least one sub-control device, whereupon the sub-control device sends data in a diagnostic mode to the main control device, which contains information about errors that have occurred. This makes a more accurate fault diagnosis possible, in particular conclusions about the time stability of the timers of the sub-control device can be made. The present invention further relates to an electronic control system for a motor vehicle brake system having a main control device with a main timer associated therewith, at least one sub-control device subordinate to the main control device with a timer associated therewith,

Wherein the main controller communicates with the at least one sub-controller cycle by cycle, and further wherein each of the main controller and the at least one sub-controller increments a cycle counter associated therewith, and the main controller and the at least one sub-controller are synchronized by a method as described above.

According to a further aspect of the invention, the object is achieved by a computer program product for carrying out the method steps described, wherein the computer program product runs on a processing unit.

15

BRIEF DESCRIPTION OF THE DRAWINGS

In the following, the invention will be described with reference to the accompanying drawings with reference to an exemplary embodiment. They show:

20

Hg.1 an inventive electronic control system;

Fig. 2 is a flowchart of a main loop of an under control device;

FIG. 3 shows a flow chart for a clock setting of the timer of FIG

Under control device;

4 shows the timing of a signal sequence;

to Fig.5 an example of a synchronization.

DETAILED FIGURE DESCRIPTION

In the following, an embodiment of the invention with reference to the figures i5 is shown in more detail. In the embodiment shown in Figure 1, the electronic components are part of an EPB (Electronic Park Brake) 10. The EPB system 10 comprises a main controller 12 with one of these associated main timer 22. Further, the EPB system 10 includes the sub-controllers 14 and 16, each having a timer 24 and 26 respectively. The main timer 22 has a quartz crystal and is clocked at a clock frequency of 4 MHz. The timers 24, 26 have adjustable RC elements to specify a clock frequency of 4 MHz.

The main controller 12 also communicates with other components of the vehicle electronics via a separate connection (not shown), such as a CAN bus, and may e.g. forward error signals supplied by the sub-controllers 14, 16 to a main processor (also not shown).

The sub-controllers 14 and 16 are each connected to and actuate actuators 34, 36 of the EPB system 10. It is provided that the actuator 34 is mounted on the left rear wheel and the actuator 36 on the right rear wheel of a motor vehicle and provided for activating or deactivating the parking brake function. Therefore, the sub-controller 14 is also referred to as a left sub-controller 14 and the sub-controller 16 as a right sub-controller 16. The actuators 34, 36 generate a parking braking force controlled by the sub-control devices 14, 16 and acting on the rear wheels.

The control devices 12, 14 and 16 communicate with each other via a bus system 18. In the present embodiment, this bus system is implemented as a LIN bus system. Where LIN-Bus stands for Local Interconnect Network-Bus

(local area network) and follows the LJN protocol. This protocol was developed for cost-effective communication for intelligent sensors and actuators in motor vehicles.

A LIN network includes a LIN master, in this case the

Main controller 12, and one or more LJN slaves, in this case the sub-controllers 14 and 16. The main controller 12 controls the timing of the data to be transmitted. In this case, the sub-control devices 14, 16 transmit data only when they are requested or authorized to do so by the main control device 14. FIG. 2 shows a flow chart of the main loop being traversed by the sub-controllers 14, 16. Only work steps are shown, which are connected to the communication and synchronization of the control devices 12, 14, 16; processes connected to a drive of the actuators 34, 36 by the sub-controllers 14, 16 are not shown.

After a start, an under control 14, 16 is initialized in step MO.

This step may include, among other things, writing registers, checking the operation of the sub-controller 14, 16, and the bus 18.

Thereafter, the sub-controller 14, 16 starts to cycle through one cycle of its main loop at step MIO. In this step, the sub-controller 14, 16 increments the value of its cycle counter.

In the case of the LIN bus, only 4 bits are provided for the transmission of the counter, which is why the counter can take values from 0 to 15 and is reset to 0 by 15 on a further increase. Therefore, throughout the scope of this description, increasing the value of a cycle counter also means that a threshold of the cycle counter is reached and the cycle counter is reset to zero; this also applies to other possible embodiments than those described here. In this case, the threshold value may depend on the number of bits provided for a cycle counter transmission.

In step M20, the sub-controller 14, 16 receives a control instruction set from the main controller 12. According to these instructions, the sub-controller 14, 16 can drive, for example, the actuator 34, 36. The control command set includes, among other things, the value of the cycle counter of the main controller 12.

Subsequently, the sub-controller 14, 16 receives a status instruction set from the main controller 12 in step M30. In this status instruction set, the main controller 12 may ask, for example, the status of the sub-controller 14, 16 or a diagnostic status. The status command set includes an identifier that is one of the

Sub-controllers 14, 16 grants write access to the bus 18. Should the main controller request a diagnosis, a branch is made to a diagnostic mode in step M40. In step M40, the sub-controller 14, 16 authorized to write to the bus 18 then transmits stored error values to the main storage device 12. After M40, step 5 M60 is then executed and the main loop is re-run.

If the main control unit does not request a diagnosis, the program branches to step M50 in step M40. In this step, the sub-controller 14, 16 authorized to write to the bus 18 sends a status report to the main controller 12. This status report contains information about the state of the actuator 34, 36 associated with the sub-controller 14, 16, among others Step M60 passed.

Step M60 causes a re-cycle of the main loop to begin at MIO i5. The main loop of the sub-controller 14, 16 thus essentially comprises the steps MIO to M60 and is in each case in 20ms lasting cycles.

After each of the steps of the main loop, one or more steps 20 may be inserted in which a cycle counter synchronization takes place. In this case, the value of the cycle counter received from the main controller 12 is compared with the value of the cycle counter of the sub-controller 14, 16. If these values differ from one another, the sub-control device 14, 16 sets its cycle counter to the value received from the main control device 12. .5 If the values are equal, no cycle counter synchronization is required. In the embodiment described here, it is provided that the sub-control device 14, 16 generates and stores an error signal after a synchronization of its cycle counter. This synchronization may, for example, be performed as a further step between steps M20 and M30, while thus the sub-controller 14, 16 is not busy with a bus access.

The main controller 12 also passes through a main loop of 20ms duration, whose swept steps are at least partially complementary to those of the main loop of the respective sub-controller 14, 16. Depending on the exact usage of a system described herein, it may be necessary to perform other subprocesses in addition to the diagnostic report and status report in main loop branches. The LJN bus system has a maximum data transfer rate of about 20 Kbit / s (with only 8 bytes being provided for the payload in a packet sent by an understeer device). Therefore, the s main control loop of the main controller 12 in this embodiment can not address both sub-controllers 14, 16 within one main loop cycle. Therefore, the main controller 12 addresses the sub-controllers 14, 16 alternately, passing a main loop cycle at even cycle count by communicating with the right lo sub-controller 16 and communicating with the left sub-controller 14 at odd cycle count. Of course, in other embodiments, a different distribution mode may also be used for the communication cycles according to the needs of the particular application.

15

FIG. 3 shows a flowchart for setting the timing of the timer of one of the sub-controllers 14, 16.

In this case, in a first step S10, a first data packet with control signals from 20 of the main control device 12 (abbreviated to HS in the figures) is received. These control signals signal the sub-controller 14, 16 to initiate step S20, at which a time measurement until receipt of a renewed control signal from the main controller 12 is started.

As soon as a second data packet with control signals has been received from the main controller 12 in a step S30, the time measurement is stopped in a step S40. In this case, a value t for the elapsed time between the reception of the two data packets sent by the main control device 12 is detected.

IO

In a step S50 it is now checked whether this time t, which has detected the sub-control device 14, 16, coincides with a predetermined interval of 20 ms, which is defined as the time interval between the transmission of the two data packets with control signals from the main control device 12. Of course, instead of 20 ms, any other suitable value for the time interval may be used; When setting up a system must be careful that both the sub-controller 14, 16 and the main controller 12 use the same predetermined value.

If the value t corresponds to a time of 20 ms, no post-synchronization by changing the clock frequency of the RC oscillator of the timer 24, 26 of the sub-controller 14, 16 is necessary and the synchronization procedure is terminated.

If t is not equal to 20 ms, it is checked in a next step S60 whether the detected time t is greater than 20 ms. If this is the case, the RC oscillator is the

Sub-controller 14, 16 clocked too fast and is slowed down in a step S70. Thereafter, the step S90 described below may be executed or the clock setting procedure is terminated. However, if the detected time t is less than 20 ms, the clock frequency of the RC oscillator is too small and in a step S80, the clock frequency of the RC oscillator is increased. Even after this

Step S90 may be executed, which generates an error signal which determines that a timing error is present or the timing adjustment procedure is terminated. After the step S90, the clock setting operation is ended.

Such a fine synchronization step by clock adjustment can be triggered, for example, by a branch in the main loop of the main control device 12. At this time, the main controller 12 may send a signal to the sub-controller 14, 16 indicating that fine-synchronization is being performed. Thereafter, the main controller 12 and the sub-controller 14, 16 go into the fine synchronization mode.

However, it is also possible to perform the fine synchronization without special triggering by the main controller 12: The main controller 12 sends a data set over the bus in each cycle of its main loop, which can be read by both sub-controllers 14, 16, even if due to the alternating addressing always only one sub-controller 14, 16 is allowed to respond. Thus, every 20 ms signals are available to the main control device 12, after which the sub-control devices 14, 16 can synchronize their timers. For this purpose, for example, a further step can be inserted into the main loop in FIG. 2 between the steps MIO and M20, which cyclically alternately starts or ends a time measurement. Furthermore, between the Steps M20 and M30, a further step is provided, which provides a branch into a process analogous to steps S50 to S90 as described above.

FIG. 4 shows a diagram for explaining the fine synchronization procedure shown in FIG. Here, the time sequence of the data exchange between the sub-control device 14, 16 and the main control device 12 is shown simplified.

Between the dashed lines there is a 20ms communication cycle. At this time, the main controller 12 sends out a control signal (sync signal) used for synchronizing the sub-controller 14, 16 abbreviated to US in the drawing. Upon arrival of the synchronization signal, the sub-controller 14, 16 starts a time measurement using its associated timer 24, 26. The main controller 12 then sends a data packet to the

Sub-controller 14, 16, which contains an identifier ID and a request, usually includes a status request. Thereafter, the sub-controller 14, 16 responds according to, for example, step M50. Until the end of this cycle of the main loop, which is indicated by the right dashed line in Figure 4, no signals between the main controller 12 and the sub-controller 14, 16 are replaced.

Upon transmission of another synchronization signal, a new cycle of the main loop of the main controller 12 begins. Upon receipt of this further synchronization signal or control signal, the sub-controller 14, 16 terminates the time measurement. Between the receipt of the two synchronization signals should have been measured by the sub-controller 14, 16 20ms; if this is not the case, a synchronization of the clock of the timer 24, 26 is carried out as described above.

Figure 5 illustrates a synchronization between the main controller 12 and the sub-controllers 14, 16 according to the method shown in Figures 3 and 4. The main controller generates cycles of 20 ms duration whose time interval is very stable due to the high-quality quartz crystal in the main timer 24. In the example shown in Figure 5, the sub-controller 16 initially has too high a clocking; the cycles passed by it have a time span of less than 20 ms (20 ms-Δt). The sub-controller 14 on the other hand, at the beginning there is too little timing; with her pass between two cycles 20 ms + Δ t. The arrows in Fig. 5 illustrate the receipt of timing signals from the main controller 12 to the sub-controller 16 and the sub-controller 14, respectively. After an under-controller 14, 16 has each received two consecutive such control signals, synchronization is made after the steps S50 to S90 carried out. As a result, after such a synchronization, the cycles are traversed at a distance of 20 ms in both the sub-controller 16 and the sub-controller 14. In this Figure 5, the cycle counter synchronization as described above is not considered.

Of course, a synchronization as set forth in this specification can be performed on a variety of electronic components.

In this case, the method according to the invention has the advantageous effect, in particular, that fast and reliable synchronization becomes possible without the need for a large number of expensive clocks. The method according to the invention can also be applied to components of an electronic braking system with arbitrary timers.

Claims

claims

A method of synchronizing components of a motor vehicle brake system comprising: a main electronic control device (12) having a main timer (22) associated therewith, at least one of the main control devices (12)

An understeer device (14, 16) having a timer (24, 26) associated therewith, said main controller (12) communicating with said at least one sub-controller (14, 16) in cycles, further comprising said main controller (12) and said at least one sub-controller (15). 14, 16) each increment a cycle counter associated therewith, characterized in that the main controller (12) sends synchronization data to the at least one sub-controller (14, 16) comprising a value of the cycle counter of the main controller (12),

20 and that the at least one sub-control device (14, 16) this

Receives synchronization data and sets its cycle counter to the received value of the cycle counter of the main controller (12), as far as the received value of the cycle counter of the main controller (12) is different from the value of the cycle counter of the sub-controller (14, 16).

> 5

2. The method according to claim 1, characterized in that the sub-control device (14, 16) further generates an error signal, if the received value of the cycle counter of the main control device (12) from the value of the cycle counter of the sub-control device (14, 16). so

3. The method according to claim 2, characterized in that the generated error signal from the sub-control device (14, 16) is stored.

4. The method according to any one of the preceding claims, characterized i5 characterized in that a clock of the at least one sub-control device (14, 16) associated timer (24, 26) can be adjusted.

5. The method according to claim 4, characterized in that the

Main control device (12) at regular time intervals of predetermined length control signals to the at least one sub-control device (14, 16) transmits and the at least one sub-control device (14, 16) detects the time interval between successive control signals and its associated timer lo (24, 26) in accordance with the detected time interval if the detected time interval differs from the time interval of predetermined length.

6. The method according to claim 5, characterized in that the at least one sub-control device (14, 16) reduces the clock of its associated timer (24, i5 26) when the detected time interval is greater than the time interval of predetermined length.

7. The method according to claim 5 or 6, characterized in that the at least one sub-control device (14, 16) the clock of its associated

2o timer (24, 26) increases when the detected time interval is smaller than the time interval of predetermined length.

8. The method according to any one of the preceding claims, characterized in that the main control device (12) and the at least one

.5 sub-control device (14, 16) via a bus system (18) communicate with each other.

9. The method according to claim 8, characterized in that the bus system (18) is a LIN bus system or LIN-based bus system.

10

10. The method according to claim 8 or 9, characterized in that the main control device (12) of the at least one subordinate control device (14, 16) assigns access rights to the bus (18).

t5 11. The method according to claim 10, characterized in that the

Main controller (12) sends data to the at least one sub-controller (14, 16) comprising an identifier identifying the at least one sub-controller that allocates write access rights and / or read access rights to the bus (18) to the main controller (12).

12. The method according to claim 11, characterized in that the main control device (12) always assigns only one of the at least one sub-control device (14, 16) write access riffsrechte on the bus (18).

5

The method of claim 11 or 12, characterized in that the main controller (12) allocates read access rights to the bus (18) to one or more of the at least one sub-controller (14, 16).

14. The method according to any one of the preceding claims, characterized in that the components of the motor vehicle brake system comprise at least two sub-control devices (14, 16).

15. The method according to claim 14, characterized in that the i5 main control device (12) at an even value of their cycle counter

Sending synchronization data to a first one of the sub-controllers (14, 16) and sending synchronization data to a second one of the sub-controllers (14, 16) at an odd value of its cycle counter.

20

16. The method according to any one of the preceding claims, characterized in that the main timer (22) comprises a quartz crystal.

17. The method according to any one of the preceding claims, characterized

25 characterized in that the at least one sub-control device (14, 16) associated timer (24, 26) comprises an RC circuit.

18. The method according to any one of the preceding claims, characterized in that the at least one sub-control device (14, 16) as a

3o sensor is formed with a microcontroller.

19. The method according to any one of claims 1 to 17, characterized in that the at least one sub-control device (14, 16) is associated with an actuator (34, 36) of an electronic parking brake system.

S5

20. The method according to claim 2 and one of the preceding claims, characterized in that the at least one sub-control device (14, 16) in a diagnostic mode sends error information to the main control device (12).

21. An electronic brake control system (10) for a motor vehicle brake system, comprising: a main electronic control device (12) with an associated 5 main timer (22), at least one of the main control device (12) subordinate sub-control device (14, 16) with an associated timer ( 24, 26), wherein the main control device (12) communicates with the at least one sub-control device (14, 16) cycle-wise, characterized in that the main control device (12) and the at least one sub-control device (14, 16) by a method according to one of preceding claims are synchronized.

A computer program product comprising program code means for performing an i5 method according to any one of claims 1 to 20 when the computer program product is run on a processing unit.