Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
  • H10W20/491—Antifuses, i.e. interconnections changeable from non-conductive to conductive
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/531—Shapes of wire connectors
  • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/541—Dispositions of bond wires
  • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/59—Bond pads specially adapted therefor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/931—Shapes of bond pads
  • H10W72/932—Plan-view shape, i.e. in top view
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/951—Materials of bond pads
  • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Definitions

• the invention relates to the field of integrated circuits, and in particular the field of adjusting or trimming an integrated circuit. Furthermore, the invention relates to a method of manufacturing an integrated circuit.
• the purpose of adjusting or trimming an integrated circuit is to optimize the performance of the circuit, for example in case there is a need to fit the different requirements of individual applications for which the integrated circuit is used.
• the adjusting or trimming of the integrated circuit may, for example, comprise the selective removal from or addition to the integrated circuit of a resistor or a capacitor.
• Commonly known examples of a method to adjust or trim the integrated circuit are laser cutting, fusing and digital programming of dedicated trimming circuits.
• US 6,914,275 discloses trimming circuitry configured to adjust selected physical and electrical characteristics of a semiconductor component or integrated circuit.
• the adjustment circuitry includes conductors, programmable links, such as fuses or anti- fuses, and can also include capacitors and inductance conductors.
• the integrated circuits can be placed in a selected state by using a laser or by applying programming signals.
• a disadvantage of this adjustment circuitry is that separate programming signals have to be generated and subsequently have to be input to the integrated circuit or that, in case of applying the laser, a, relatively costly, laser has to be used to set the integrated circuit in a selected state.
• the integrated circuit according to the invention comprises a substrate having a first electrode and a second electrode adjacent to and electrically isolated from the first electrode, and a selectively present conductive layer, which is deposited on the first electrode and the second electrode, to provide for a selected state in which the first electrode and the second electrode are electrically connected.
• the application of a conductive layer to set the integrated circuit in the selected state discards the need for applying a laser or a programming signal, thereby avoiding any unwanted damage to the integrated circuit by the laser, for example due to heat dissipation, or by the programming signals, for example in case of Near Field Communication antenna tuning where high voltage signals are required.
• the integrated circuit can, for example, be used to selectively optimize the performance of the integrated circuit by selectively adding, through the setting of the selected state, a semiconductor component or device to the integrated circuit.
• a plurality of adjustments for the integrated circuit are possible by setting the appropriate selected states resulting in a plurality of semiconductor components or devices that are selectively added to the integrated circuit.
• the conductive layer comprises a bond ball. Applying a bond ball to create a short between the first and second electrode is a simple method that, for example, can be embedded in a standard manufacturing bonding or packaging method of the integrated circuit.
• the second electrode is circle-shaped and the first electrode comprises a ring- shaped segment that partially surrounds the second electrode.
• This embodiment can, for example, be used for a circular shaped conductive layer.
• a method of manufacturing an integrated circuit according to the invention comprises the steps of: - providing a first electrode and a second electrode on a substrate, in which the first electrode is adjacent to and electrically isolated from the second electrode; and selectively depositing a conductive layer on the first and the second electrode to provide for a selected state in which the first and the second electrode are electrically connected.
• Fig. IA is a schematic top view of an embodiment of an integrated circuit according to the invention in an unselected state
• Fig. IB is a diagrammatic cross-sectional view, taken along the line A-A' of Fig. IA, of an embodiment of an integrated circuit according to the invention in an unselected state;
• Fig. 2A is a schematic top view of an embodiment of an integrated circuit according to the invention in a selected state
• Fig. 2B is a diagrammatic cross-sectional view, taken along the line A-A' of Fig. 2A, of an embodiment of an integrated circuit according to the invention in a selected state;
• Fig. 3A is a schematic electrical scheme of an embodiment of an integrated circuit according to the invention comprising a plurality of unselected states
• Fig. 3B is a schematic top view of an embodiment of an integrated circuit according to the invention comprising a plurality of unselected states
• Fig. 4A is a schematic electrical scheme of an embodiment of an integrated circuit according to the invention comprising a plurality of unselected and selected states
• Fig. 4B is a schematic top view of an embodiment of an integrated circuit, according to the invention comprising a plurality of unselected and selected states;
• Fig. 5A is a schematic electrical scheme of an embodiment of an integrated circuit according to the invention comprising a plurality of unselected states
• Fig. 5B is a schematic top view of an embodiment of an integrated circuit according to the invention comprising a plurality of unselected states
• Fig. 6A is a schematic electrical scheme of an embodiment of an integrated circuit according to the invention comprising a plurality of unselected and a selected states
• Fig. 6B is a schematic top view of an embodiment of an integrated circuit according to the invention comprising a plurality of unselected and a selected states
• Fig. 7A is a schematic top view of an embodiment of an integrated circuit according to the prior art.
• Fig. 7B is a schematic top view of an embodiment of an integrated circuit according to the invention comprising a plurality of unselected and selected states.
• Fig. IA shows a schematic top view and Fig. IB the corresponding schematic cross-section, taken along the line A-A' of Fig. IA, of an embodiment of an integrated circuit according to the invention in which the integrated circuit is in an unselected state.
• the integrated circuit comprises a first electrode 1 that surrounds a second electrode 2.
• the first electrode 1 comprises a segment of a ring-shaped structure
• the second electrode 2 comprises a circular structure.
• the first electrode 1 and the second electrode 2 comprise a conductive material, for example aluminum, are placed on a substrate 99 of, for example, silicon, and are electrically isolated by an insulator 99, which may be, for example, silicon dioxide.
• the unselected state is achieved by the fact that the first electrode 1 and the second electrode 2 are electrically isolated.
• a selected state is achieved for the integrated circuit according to the invention by depositing a conductive layer, in this case a bond ball 3, on the first electrode 1 and the second electrode 2, as can be seen in the schematic top view of Fig. 2A and the corresponding schematic cross-section of Fig. 2B, taken along the line A-A' of Fig. 2A.
• the bond ball 3 provides for an electrical connection between the first electrode 1 and the second electrode 2, and hence for the selected state of the integrated circuit.
• Fig. 3B shows a schematic top view of an embodiment of an integrated circuit according to the invention
• Fig. 3A shows the corresponding electrical scheme.
• the integrated circuit comprises, in this case, four programmable links 41, 42, 43, 44, which are all in an unselected state, also shown by the open switches of Fig. 3A.
• the four programmable links 41, 42, 43, 44 comprise first electrodes 11, 12, 13, 14, respectively, and second electrodes 21, 22, 23, 24, respectively. All first electrodes 11, 12, 13, 14 are electrically connected to a first node 100, which is, for example, connected to an output terminal of another integrated circuit that generates an input signal X, which is not shown in the Figure.
• the second electrodes 21, 22, 23, 24 are electrically connected to second nodes 201, 202, 203, 204, respectively.
• the second nodes 201, 202, 203, 204 are, for example, connected to input terminals of different integrated circuits.
• the corresponding programmable links 41 and 43 have to be set in the selected state, which is shown in the schematic top view of Fig. 4B and the corresponding electrical scheme of Fig. 4A.
• Programmable links 41 and 43 are set in the selected state by the, in this case, bond balls 31 and 33, respectively, which is illustrated by the closed switches in Fig. 4A.
• the signal X which is input on the first node 100, is passed on to the first nodes 201 and 203, whereas the first nodes 202 and 204 do not receive the signal X.
• Fig. 5B shows a schematic top view of another embodiment of an integrated circuit according to the invention, and Fig. 5A shows the corresponding electrical scheme.
• a capacitor value can be adjusted, for example, to fit the varying requirements of different customers of the integrated circuit.
• the integrated circuit comprises, in this case, three programmable links 41, 42, 43, which are all in an unselected state, also shown by the open switches of Fig. 5 A.
• the three programmable links 41, 42, 43 comprise first electrodes 11, 12, 13, respectively, and second electrodes 21, 22, 23, respectively.
• the first electrodes 11, 12, 13 are electrically connected via capacitors 91, 92, 93 to a first node 100, which is, for example, connected to an output terminal of another integrated circuit.
• the second electrodes 21, 22, 23 are all electrically connected to a second node 200, which is, for example, connected to an input terminal of yet another integrated circuit.
• a second node 200 which is, for example, connected to an input terminal of yet another integrated circuit.
• any one or combination of two, or all three programmable links 41, 42, 43 can be set in the selected state.
• the schematic top view of Fig. 6B and the corresponding electrical scheme of Fig. 6A show that, in this case, one programmable link 42 is set to the selected state by depositing a, in this case, bond ball 32 on first and second electrode 12 and 22, which is illustrated by the closed switch in Fig. 6A.
• Fig. 7A shows a schematic top view of an integrated circuit as is known in the art.
• the integrated circuit comprises, in this case, three sub-circuits 81, 82, 83, that are connected via electrodes, bond balls on the electrodes and wires to bondpads that surround the integrated circuit.
• the bondpads 51, 52, 53, 54, the corresponding wires and the corresponding electrodes 71, 72, 73, 74, respectively, are used to activate, using appropriate programming signals, the internal trimming circuitry of sub-circuit 82 to adjust the integrated circuit.
• the four bondpads 51, 52, 53, 54 are used for a different purpose, for example to enable a connection to an output terminal of another integrated circuit.
• Fig. 7B shows a schematic top view of the integrated circuit according to the invention in which, in this case, four programmable links 41, 42, 43, 44 are applied that enable the possibility of adjustment or trimming of the integrated circuit.
• the programmable links 41 and 43 are set to the selected state by depositing bond balls 31 and 33, respectively, on the programmable links 41 and 43. Note that the programmable links 42 and 44 stay in the unselected state, because no bond balls are deposited on the programmable links 42 and 44.
• the invention provides an integrated circuit comprising a substrate having a first electrode and a second electrode adjacent to and electrically isolated from the first electrode and a selectively present conductive layer, which is deposited on the first and the second electrode, to provide for a selected state in which the first and the second electrode are electrically connected.
• the possibility to choose for the selected state enables an adjustment or trimming of the integrated circuit, by, for example, selectively adding a semiconductor device to the integrated circuit.

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• Semiconductor Integrated Circuits (AREA)
• Design And Manufacture Of Integrated Circuits (AREA)

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Applications Claiming Priority (3)

Publications (1)

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• 2007
  • 2007-06-12 WO PCT/IB2007/052225 patent/WO2008001248A2/en not_active Ceased
  • 2007-06-12 EP EP07766731A patent/EP2038926A2/de not_active Withdrawn

Non-Patent Citations (1)

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