EP2012250A3 - Analog Dividierer - Google Patents

Analog Dividierer Download PDF

Info

Publication number
EP2012250A3
EP2012250A3 EP08103649A EP08103649A EP2012250A3 EP 2012250 A3 EP2012250 A3 EP 2012250A3 EP 08103649 A EP08103649 A EP 08103649A EP 08103649 A EP08103649 A EP 08103649A EP 2012250 A3 EP2012250 A3 EP 2012250A3
Authority
EP
European Patent Office
Prior art keywords
sawtooth
signal
triangular signal
input voltage
regulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP08103649A
Other languages
English (en)
French (fr)
Other versions
EP2012250A2 (de
EP2012250B1 (de
Inventor
Jalal Hallak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP2012250A2 publication Critical patent/EP2012250A2/de
Publication of EP2012250A3 publication Critical patent/EP2012250A3/de
Application granted granted Critical
Publication of EP2012250B1 publication Critical patent/EP2012250B1/de
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G06G7/161—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division with pulse modulation, e.g. modulation of amplitude, width, frequency, phase or form

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Dc-Dc Converters (AREA)
  • Inverter Devices (AREA)
  • Analogue/Digital Conversion (AREA)
  • Pulse Circuits (AREA)

Abstract

Die Erfindung betrifft einen Verfahren zum Betreiben eines Analog Dividierers, wobei ein Sägezahn- oder Dreieckssignal aus einer erste Eingangsspannung (U1) als Divisor gebildet wird, und wobei dieses Sägezahn- oder Dreieckssignal mittels eines ersten Komparators (KO1) mit einer zweiten Eingangsspannung (U2) als Dividend in der Weise verglichen wird, dass als ein erstes Vergleichssignal (SIG1OUT) ein pulsweitenmoduliertes Signal erzeugt wird, dessen Mittelwert als Quotienten der Division ausgegeben wird. Dabei wird das Sägezahn- oder Dreieckssignal mittels eines ersten und eines zweiten Reglers (REG1, REG2) gebildet und dem ersten Regler (REG1) die erste Eingangsspannung (U1) oder eine dazu proportionale Spannung und das Sägezahn- oder Dreieckssignal oder ein dazu proportionales Signal in der Weise zugeführt, dass der obere Spitzenwert des Sägezahn- oder Dreieckssignals der ersten Eingangsspannung nachgeregelt wird. Des Weiteren wird dem zweiten Regler (REG2) das Bezugspotenzial und das Sägezahn- oder Dreieckssignal in der Weise zugeführt, dass der untere Spitzenwert des Sägezahn- oder Dreieckssignals dem Wert des Bezugspotenzials nachgeregelt wird.
EP20080103649 2007-06-19 2008-04-22 Analog Dividierer Not-in-force EP2012250B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AT9432007A AT505446B1 (de) 2007-06-19 2007-06-19 Analog dividierer

Publications (3)

Publication Number Publication Date
EP2012250A2 EP2012250A2 (de) 2009-01-07
EP2012250A3 true EP2012250A3 (de) 2011-10-12
EP2012250B1 EP2012250B1 (de) 2013-11-13

Family

ID=39767140

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20080103649 Not-in-force EP2012250B1 (de) 2007-06-19 2008-04-22 Analog Dividierer

Country Status (2)

Country Link
EP (1) EP2012250B1 (de)
AT (1) AT505446B1 (de)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3024999A (en) * 1959-02-11 1962-03-13 Jr William J Heacock Electronic divider
US3278737A (en) * 1962-08-03 1966-10-11 Gulton Ind Inc Quotient circuit
EP0049334A2 (de) * 1980-10-03 1982-04-14 VDO Adolf Schindling AG Elektronischer Dividierer
US20040119622A1 (en) * 2002-12-23 2004-06-24 Karlquist Richard K. System and method for designing and using analog circuits operating in the modulation domain
JP2005157721A (ja) * 2003-11-26 2005-06-16 Yokogawa Electric Corp アナログ除算器
DE102005030599A1 (de) * 2005-06-30 2007-01-11 Siemens Ag Österreich Steuerungsverfahren für zweistufige Konverter

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3976894A (en) * 1975-02-03 1976-08-24 Raytheon Company Analog divider circuitry
DE202004019553U1 (de) * 2004-12-18 2005-03-03 Lerner, Zinoviy, Dipl.-Ing. Multiplizierer-Dividierer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3024999A (en) * 1959-02-11 1962-03-13 Jr William J Heacock Electronic divider
US3278737A (en) * 1962-08-03 1966-10-11 Gulton Ind Inc Quotient circuit
EP0049334A2 (de) * 1980-10-03 1982-04-14 VDO Adolf Schindling AG Elektronischer Dividierer
US20040119622A1 (en) * 2002-12-23 2004-06-24 Karlquist Richard K. System and method for designing and using analog circuits operating in the modulation domain
JP2005157721A (ja) * 2003-11-26 2005-06-16 Yokogawa Electric Corp アナログ除算器
DE102005030599A1 (de) * 2005-06-30 2007-01-11 Siemens Ag Österreich Steuerungsverfahren für zweistufige Konverter

Also Published As

Publication number Publication date
EP2012250A2 (de) 2009-01-07
EP2012250B1 (de) 2013-11-13
AT505446A1 (de) 2009-01-15
AT505446B1 (de) 2009-08-15

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