EP2005440A1 - Procédé pour faire fonctionner un dispositif de mémoire - Google Patents

Procédé pour faire fonctionner un dispositif de mémoire

Info

Publication number
EP2005440A1
EP2005440A1 EP07726878A EP07726878A EP2005440A1 EP 2005440 A1 EP2005440 A1 EP 2005440A1 EP 07726878 A EP07726878 A EP 07726878A EP 07726878 A EP07726878 A EP 07726878A EP 2005440 A1 EP2005440 A1 EP 2005440A1
Authority
EP
European Patent Office
Prior art keywords
block
memory
bit
blocks
bit pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP07726878A
Other languages
German (de)
English (en)
Inventor
Jens Liebehenschel
Joern Boettcher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP2005440A1 publication Critical patent/EP2005440A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Definitions

  • the invention relates to a method for operating a memory device, a device for operating a memory device, a memory device, a computer program and a computer program product.
  • Memory devices or storage media have a limited life, which is essentially determined by the number of writes. As the number of writes increases, the data retention time is shortened. Therefore, in the development of memory devices, it is an objective to use memory devices sparingly with respect to the relevant operations and thus to provide memory hardware and the like. a. to save by reducing the write operations. If necessary, other resources, such as RAM, ROM, or runtime, may be used to an appropriate extent. In this way, an extension of the life of memory devices is to be achieved.
  • the present invention relates to a method having the features of patent claim 1, a device having the features of patent claim 12, a memory device having the features of patent claim 13, a computer program having the features of patent claim 14 and a computer program product having the features of patent claim 15 ,
  • a memory area is usually divided into, for example, logical blocks of the same size. Blocks can assume different states, such as free or busy. Blocks contain at least one management information that does not necessarily have to be stored together with the data.
  • the data can be stored in linked lists of blocks. Each linked list consists of at least one block. As a rule, there is no fixed allocation of data and memory areas on the medium, so that the data are repeatedly stored in different blocks at different positions. As a result, the memory device is loaded more uniformly than with a fixed one
  • Assignment of data to blocks or memory areas is the case. Before writing data, it is necessary to search for free or empty blocks. When searching for the free blocks, no defective blocks should be selected. Overall, however, the largest possible number of free blocks should always be available.
  • a memory area, ie at least one memory cell, of a block is assigned a first bit pattern after performing an erase operation that is separate from a write operation. In the event of a tip over of at least one bit within this memory area, a state change can be detected for this block.
  • the device according to the invention for operating a memory device having a number of blocks is designed to assign a bit pattern to a memory area, ie at least one memory cell, of a block after performing an erase operation that is separate from a write operation, so that in the case of Tipping over of at least one bit within the memory area for this block a state change can be detected.
  • the invention also relates to a memory device which has a number of blocks and is adapted to assign a bit pattern to a memory area, thus at least one memory cell, of a block, after a deletion operation which is separate from a write operation, so that in the case of Tipping over of at least one bit within the memory area for this block a state change can be detected.
  • All steps of the method according to the invention can be carried out with the device according to the invention and the storage device according to the invention. Intermediate see the device according to the invention and the memory device according to the invention may be an interaction.
  • the device may be formed as a component of the memory device or the memory device as a component of the device.
  • the computer program with program code means according to the invention is designed to perform all the steps of a method according to the invention when the computer program is executed on a computer or a corresponding computing unit, in particular a device according to the invention.
  • the invention further relates to a computer program product with program code means which are stored on a computer-readable data carrier in order to perform all the steps of a method according to the invention when the computer program is executed on a computer or a corresponding arithmetic unit, in particular a device according to the invention.
  • a block is classified as deleted by introducing a new state and marked accordingly by assigning the first of two possible bit values or bits to the at least one memory cell of the block.
  • the erasure operation for a previous content of the block is performed separately from a new content write operation of that block, so that erase and write operations are performed, in particular independently of each other and separately from one another and not automatically or immediately after one another as otherwise usual.
  • Blocks generally have a plurality of memory cells, at least one block can be used for storing, in particular one particular - A -
  • non-volatile date this date can be stored by changing the content of memory cells of at least one block and deleted.
  • the method is particularly suitable for a memory device in which the probability that the first bit value will become the second bit value by tipping over is greater than the probability that the second bit value will be tipped over to become the first bit value.
  • the write operation and an assignment of the new state "erased” in particular so-called memory-related state changes of the block, which are usually caused by physical influences, can be better recognized by the at least one memory cell of the block first bit value is assigned.
  • a marking of the block as deleted or an assignment of the state "deleted” in connection with the deletion operation can occur after, in particular immediately after, the deletion operation and thus subsequently thereto.
  • this can also mean that the assignment of the state "deleted” can be implicitly carried out with the deletion process and thus as part of the deletion process.
  • the invention it is possible, in particular in the case of block-oriented memory devices or file systems, for example in EEPROMs, to increase the lifetime of such memory devices and thus to improve the availability of a service for managing and / or storing, for example, non-volatile data.
  • the presented method reduces the likelihood that physically defective blocks will be used to store data. In addition, it can be avoided that physically intact blocks are not used for storage.
  • a block of memory is automatically cleared in known procedures when new data is written to the block.
  • the blocks are automatically cleared in known procedures when new data is written to the block.
  • the block can assume the further state "erased” without influencing the number of write operations or accesses.
  • an assignment of this state or a corresponding marking of the block can be carried out when performing the deletion process.
  • the deleted block can be marked accordingly. This allows a particular situation to be coded.
  • the state “deleted” is marked by a specific bit pattern of the at least one memory cell of a memory area or of all the memory cells of the block and thus identified. By using the additional state “deleted", an extension of the lifetime of the memory device or a corresponding medium can be achieved. On the other hand, this is not possible if the delete and write operations are performed together.
  • the mark with the new state "cleared” as well as a separation of the erase and write operation at the memory device is used to increase the probability of the correct recognition of a state of blocks.
  • the framework conditions and a coding of the management information and the data of the respective block in the implementation of the method are suitably adapted.
  • a block may be marked intact, in which case the block is either free or busy. If the block undergoes the particular memory-related state change, which is an unintentional or unwanted state change which is not caused by intervention by a user, the block can furthermore be marked as defective or suspicious. These State change may be due to at least one error and make itself felt automatically by tilting at least one bit of the at least one memory device. Depending on a type or frequency of the error, the block is either classified as suspicious or defective and classified accordingly. An explicit mark as suspicious or defective can be made.
  • Blocks suspiciously marked or recognized may be observed for further development.
  • An at least originally intact block can hereby be marked as suspicious after the occurrence of a first error.
  • a block can only be marked as defective after two consecutive errors, with the second error having to appear suspicious in the state.
  • an embodiment described below is based on the assumption that the method is used for a block-oriented file system or a block-oriented memory device with a number of blocks.
  • Each block consists of data and administrative information which provides information about a status and type of the block as well as provides a pointer to the next block.
  • test data can be used. By determining such check data, for the block in which at least one bit is skewed, it can be checked whether the content of the block is in the state that has been written. The test data can thus be used to detect alleged storage-related state changes as well as state changes caused by an intended operation.
  • the state or status of the block is coded by the coding or a bit pattern of the memory cells.
  • the memory cells can assume the binary values one ("1") and zero ("0").
  • the memory cells may be assigned any suitable characters representing unique, preferably binary values.
  • a record consists of a first block and can contain several more blocks, depending on the length of a date.
  • each coding comprises eight memory cells, the coding being provided for defining and / or marking the state of the respective block.
  • all values for the memory cells of the encoding are ones.
  • the first memory cell of the coding is a one, the other memory cells are occupied with arbitrary bit values, with the exception of the free-block bit pattern.
  • the first memory cell of the coding has a zero, the other memory cells are ones.
  • a first memory cell encoding a further block of the data is a zero, the other memory cells are arbitrary, with the exception of the suspect block bit pattern.
  • the coding can be coded in the coding for the status whether the block concerned is a first block or another block within the data record. Furthermore, there is a coding of the ID, under which the date can be found in the memory device.
  • Occupied blocks therefore contain the value "logical O" on at least one memory cell, except for the first memory cell. These occupied blocks can be recognized in a further embodiment of the invention by determining the test data as correct or incorrect. Defective blocks look like suspicious blocks, but with the coding of defective blocks the value or bit value "0" is located at at least one other memory cell. If a block is to be marked as a free block, it is deleted. It is thus possible to exploit the additional state "erased" of the memory device by separating the erase and write operations. Marking a deleted and thus free block does not require write access. A write access occurs only when the deleted block is again described with data.
  • the method may also include the possibility that by providing the bit pattern according to which the first bit value is assigned to the at least one memory cell and thus the block is marked as deleted, the deletion operation is carried out automatically, so that marking the block is deleted may also correspond to or include the deletion operation.
  • the memory device or spared a medium because no write access is required to detect the state.
  • the coding of a suspect block differs from the coding of a free block only by a memory cell. This bit at the state marking, preferably first memory cell of the coding is also used to distinguish a first block of a data set and the other blocks for this record.
  • the error occurs at the state tagging memory cell of the free block coding, it may become a suspect block. If the error occurs at this memory-tagging memory cell on a suspect block, that block can be used without problems for each block of a data set except the first block.
  • the discrimination of the coding of the first and all further blocks is chosen so that, with much greater probability, a first block in a list may become another block than that of a further block becomes a first block.
  • codes in Table 1 can be used for other states.
  • the status that only consists of "0" is well suited for marking defective blocks in the case of certain memories.
  • a further function for cleaning up the memory device is provided.
  • This feature includes, for example, releasing incomplete chains and marking suspect blocks. In all the operations mentioned, it may be necessary to recognize or mark the status of blocks. A precise approach for implementing the invention may depend on non-functional requirements of the system.
  • the procedure can be specified in detail. In particular, it can be determined at what times and in which operations which types of blocks are marked as and which types of blocks may be used to store data.
  • a marking for the at least one memory cell of a respective coding, whereby the status of the block is displayed by these at least one memory cell, is selected according to the application such that, in particular taking account of bit-tilting and aborted delete and write operations, blocks are defective due to the particular memory-related state change, with high probability as defective and intact blocks are recognized as intact.
  • Errors can be, for example, physical errors in the storage hardware or incomplete writes caused by power interruptions or resets. Nevertheless, when a memory error is detected, either the corresponding block is often marked as defective and not reused or the error is ignored and the block is reused. In one embodiment of the present method, blocks may be marked as deleted and thus as free and further as intact, as suspicious and as defective. In this way it is possible to increase the availability of stored or stored data.
  • the method may also include a strategy for reviving or reactivating suspect blocks.
  • This strategy such as a revitalization on demand, after a period of time, and / or according to certain specifications, such that, for example, only a required number of blocks or all suspicious, non-defective blocks are revived.
  • a particular design of this strategy also depends on the non-functional requirements of the storage device.
  • An example of a weighting of non-functional requirements may include making a decision about whether data security or the lifetime of the storage device is more important. A possible question would be whether data loss with the consequence that a written datum can not be read or a memory leak with the consequence that a memory cell is erroneously recognized as being defective is more acceptable.
  • inverse prerequisites may exist:
  • the erased state of the memory cell corresponds to "0" and the probability of Bitkippern from “0” to “1” is greater than from “1” to "0".
  • the coding may, for example, vary with regard to a structure and / or with regard to the components of the management information and data. This may relate to a status, ie the type and state of the block, a reference to a next block of a date and / or a use and types of checksums and their arrangement. Furthermore, the coding may vary depending on a type of the block-oriented memory device. It may, for example, be provided to store the management information separately from the data. In contrast, in a storage device designed for this purpose, the management information can be stored together with the data.
  • the invention can be used in embedded systems, for example control devices in motor vehicles, which each have memory devices according to the invention and / or interact with them.
  • Figure 1 shows a schematic representation of an embodiment of a device and a memory device with a block in one embodiment of the method
  • the memory device 2 (dashed box) and device 4, shown schematically in FIG. 1, interact in carrying out the described embodiment of the method.
  • the memory device 2 has any number of blocks 6 which are provided for storing data.
  • FIG. 1 shows a block 6 in different states. The states are respectively marked by bit values associated with the memory cells 14 of the block 6.
  • the block 6 is described with a date. This is marked by the fact that the first memory cell of the coding 14, the bit value "0", d. H. logicO, the four further memory cells 14 are assigned the bit values "1010" for characterizing the data in this embodiment.
  • a content of the present block 6 is deleted by the device 4 and thus an erase operation 16 is performed.
  • the first memory cell 14 and the four further memory cells 14 of the block 6 are respectively assigned the bit value "1", ie logical.
  • the block 6 is marked as deleted, so that this deleted block 6 can be quickly identified in a search for free blocks to store new data.
  • a change of state 18 should occur for the block 6, which in this embodiment is a memory-dependent change of state 18, this change in state takes place by tilting the bit value from "1" to "1" in the present embodiment. 0 "noticeable in the first memory cell 14 of the block.
  • a probability for a memory-dependent tilting of a bit value from “1" to “0” is greater than from “0" to "1".
  • Such accidental or unintentional tilting is usually caused by an error in the corresponding memory cell 14. Due to the choice for coding the memory cells 14 or for a bit pattern of the memory cells 14 of the block, the error-related tilting of the bit value, for example, automatically and thus automatically becomes noticeable, as a result of which the change in state 18 of the block 6 can be well recognized.
  • a write operation 20 in which a new date is stored on the block 6 can take place.
  • the first memory cell 14 of the block 6 is assigned the value "0".
  • the further memory cells 14 are assigned bit values "0101" which characterize this new datum.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

La présente invention concerne un procédé pour faire fonctionner un dispositif de mémoire (2) présentant un certain nombre de blocs (6). Selon ce procédé, une configuration binaire est associée à une région de mémoire, c'est-à-dire au moins une cellule de mémoire (14) d'un bloc (6), après l'exécution d'une opération d'effacement (16) qui s'effectue séparément d'une opération d'écriture (20), de manière à pouvoir identifier un changement d'état (18) concernant ce bloc (6) en cas de retournement d'au moins un bit dans la région de mémoire.
EP07726878A 2006-03-24 2007-03-14 Procédé pour faire fonctionner un dispositif de mémoire Ceased EP2005440A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102006013763A DE102006013763A1 (de) 2006-03-24 2006-03-24 Verfahren zum Betreiben einer Speichereinrichtung
PCT/EP2007/052382 WO2007110327A1 (fr) 2006-03-24 2007-03-14 Procédé pour faire fonctionner un dispositif de mémoire

Publications (1)

Publication Number Publication Date
EP2005440A1 true EP2005440A1 (fr) 2008-12-24

Family

ID=38134769

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07726878A Ceased EP2005440A1 (fr) 2006-03-24 2007-03-14 Procédé pour faire fonctionner un dispositif de mémoire

Country Status (7)

Country Link
US (1) US8250321B2 (fr)
EP (1) EP2005440A1 (fr)
JP (1) JP2009531757A (fr)
KR (1) KR20080107426A (fr)
CN (1) CN101405816A (fr)
DE (1) DE102006013763A1 (fr)
WO (1) WO2007110327A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8799188B2 (en) * 2011-02-08 2014-08-05 International Business Machines Corporation Algorithm engine for use in a pattern matching accelerator
JP5581256B2 (ja) * 2011-03-28 2014-08-27 株式会社東芝 メモリシステム、コントローラ、およびメモリシステムの制御方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3485938B2 (ja) * 1992-03-31 2004-01-13 株式会社東芝 不揮発性半導体メモリ装置
US5761440A (en) * 1994-09-15 1998-06-02 International Business Machines Corporation System and method utilizing multiple search trees to route data within a data processing network
US5475693A (en) * 1994-12-27 1995-12-12 Intel Corporation Error management processes for flash EEPROM memory arrays
JPH11110304A (ja) * 1997-09-30 1999-04-23 Sanyo Electric Co Ltd マイクロコンピュータ
EP0926687B1 (fr) * 1997-12-22 2005-03-02 STMicroelectronics S.r.l. Auto test et correction d'erreurs de pertes de charge dans une mémoire flash, effacable et programmable par secteurs
WO2001022232A1 (fr) * 1999-09-17 2001-03-29 Hitachi, Ltd. Memoire dans laquelle le nombre de corrections d'erreurs est enregistre
US6671837B1 (en) * 2000-06-06 2003-12-30 Intel Corporation Device and method to test on-chip memory in a production environment
JP2003076604A (ja) * 2001-09-03 2003-03-14 Nec Access Technica Ltd フラッシュメモリのログ情報収集方式および方法
JP4188744B2 (ja) * 2003-04-08 2008-11-26 株式会社ルネサステクノロジ メモリカード
JP4172699B2 (ja) * 2003-04-25 2008-10-29 Ｔｄｋ株式会社 不揮発性半導体メモリ
JP4222879B2 (ja) 2003-05-30 2009-02-12 Ｔｄｋ株式会社 メモリコントローラ及びメモリコントローラを備えるフラッシュメモリシステム、並びに、フラッシュメモリの制御方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2007110327A1 *

Also Published As

Publication number Publication date
KR20080107426A (ko) 2008-12-10
US8250321B2 (en) 2012-08-21
CN101405816A (zh) 2009-04-08
DE102006013763A1 (de) 2007-09-27
WO2007110327A1 (fr) 2007-10-04
US20090319732A1 (en) 2009-12-24
JP2009531757A (ja) 2009-09-03

Similar Documents

Publication Publication Date Title
DE102012208141B4 (de) Ausgleich nachlassender Funktionsfähigkeit
DE102007006307A1 (de) Verfahren zum Betreiben eines nichtflüchtigen Speicherelements, Aufzeichnungsmedium und nichtflüchtigen Speicherelement
DE102005034611A1 (de) Speichersystem und zugehörige Betriebs- und Blockverwaltungsverfahren
EP1008993A2 (fr) Mémoire avec dispositif de auto-test et sa mèthode
DE3602112A1 (de) System zur speicherung von informationen
DE102006009214B4 (de) Verfahren und Vorrichtung zum Schreiben in eine Zielspeicherseite eines Speichers
DE60317801T2 (de) Verfahren und vorrichtung zur erkennung von fehlern während des schreibens in einen nichtflüchtigen speicher
DE102012101405B4 (de) Steuervorrichtung zum Steuern eines Datenlesens und - schreibens von und zu einem Flash-Speicher
EP2005440A1 (fr) Procédé pour faire fonctionner un dispositif de mémoire
DE102005016801B4 (de) Verfahren und Rechnereinheit zur Fehlererkennung und Fehlerprotokollierung in einem Speicher
DE3210616A1 (de) Rechner
EP1204917B1 (fr) Pile d'operandes et procede de mise en oeuvre d'une pile d'operande
DE10134654A1 (de) Verfahren zur Fehleranalyse von Speichermodulen
DE19959779A1 (de) Vorrichtung zum Erhalten von Fehlverhaltensinformationen sowie diese verwendende Halbleiterspeicher-Prüfvorrichtung
EP2002446B1 (fr) Procédé pour faire fonctionner un dispositif de mémoire comprenant le marquage de blocs de mémoire identifiées comme défectueux
DE2750126B2 (fr)
WO2004105042A1 (fr) Dispositif et procede pour traiter un etat d'une memoire
DE112015002881B4 (de) Speichervorrichtung, Flash-Speicher-Steuervorrichtung und Programm
DE102017119426A1 (de) Verfahren und vorrichtung zum test von speicherzellen
DE19701323C2 (de) Verfahren und Vorrichtung zur Aktualisierung der Betriebssoftware
WO2009103728A1 (fr) Procédé et dispositif de stockage de données d’information
DE102006013762A1 (de) Verfahren zum Betreiben einer Speichereinrichtung
DE102005013896B4 (de) Verfahren zur Datenverwaltung und Datenzugriffssystem zum Speichern von allen Verwaltungsdaten in einer Verwaltungsbank eines nicht-flüchtigen Speichers
DE2710502A1 (de) Anordnung zur kohaerenten leitung einer speicherhierarchie
DE102008002494A1 (de) Verfahren zum Aktualisieren eines Speichersegments, Datenverarbeitungsschaltung und Speichersegment

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20081024

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE ES FR GB IT

17Q First examination report despatched

Effective date: 20090203

DAX Request for extension of the european patent (deleted)
RBV Designated contracting states (corrected)

Designated state(s): DE ES FR GB IT

REG Reference to a national code

Ref country code: DE

Ref legal event code: R003

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 20130805